1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 7 * Copyright (C) 2000 Silicon Graphics, Inc. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 12 */ 13 #ifndef _ASM_MIPSREGS_H 14 #define _ASM_MIPSREGS_H 15 16 #include <linux/linkage.h> 17 #include <asm/hazards.h> 18 #include <asm/war.h> 19 20 /* 21 * The following macros are especially useful for __asm__ 22 * inline assembler. 23 */ 24 #ifndef __STR 25 #define __STR(x) #x 26 #endif 27 #ifndef STR 28 #define STR(x) __STR(x) 29 #endif 30 31 /* 32 * Configure language 33 */ 34 #ifdef __ASSEMBLY__ 35 #define _ULCAST_ 36 #else 37 #define _ULCAST_ (unsigned long) 38 #endif 39 40 /* 41 * Coprocessor 0 register names 42 */ 43 #define CP0_INDEX $0 44 #define CP0_RANDOM $1 45 #define CP0_ENTRYLO0 $2 46 #define CP0_ENTRYLO1 $3 47 #define CP0_CONF $3 48 #define CP0_CONTEXT $4 49 #define CP0_PAGEMASK $5 50 #define CP0_WIRED $6 51 #define CP0_INFO $7 52 #define CP0_BADVADDR $8 53 #define CP0_COUNT $9 54 #define CP0_ENTRYHI $10 55 #define CP0_COMPARE $11 56 #define CP0_STATUS $12 57 #define CP0_CAUSE $13 58 #define CP0_EPC $14 59 #define CP0_PRID $15 60 #define CP0_CONFIG $16 61 #define CP0_LLADDR $17 62 #define CP0_WATCHLO $18 63 #define CP0_WATCHHI $19 64 #define CP0_XCONTEXT $20 65 #define CP0_FRAMEMASK $21 66 #define CP0_DIAGNOSTIC $22 67 #define CP0_DEBUG $23 68 #define CP0_DEPC $24 69 #define CP0_PERFORMANCE $25 70 #define CP0_ECC $26 71 #define CP0_CACHEERR $27 72 #define CP0_TAGLO $28 73 #define CP0_TAGHI $29 74 #define CP0_ERROREPC $30 75 #define CP0_DESAVE $31 76 77 /* 78 * R4640/R4650 cp0 register names. These registers are listed 79 * here only for completeness; without MMU these CPUs are not useable 80 * by Linux. A future ELKS port might take make Linux run on them 81 * though ... 82 */ 83 #define CP0_IBASE $0 84 #define CP0_IBOUND $1 85 #define CP0_DBASE $2 86 #define CP0_DBOUND $3 87 #define CP0_CALG $17 88 #define CP0_IWATCH $18 89 #define CP0_DWATCH $19 90 91 /* 92 * Coprocessor 0 Set 1 register names 93 */ 94 #define CP0_S1_DERRADDR0 $26 95 #define CP0_S1_DERRADDR1 $27 96 #define CP0_S1_INTCONTROL $20 97 98 /* 99 * Coprocessor 0 Set 2 register names 100 */ 101 #define CP0_S2_SRSCTL $12 /* MIPSR2 */ 102 103 /* 104 * Coprocessor 0 Set 3 register names 105 */ 106 #define CP0_S3_SRSMAP $12 /* MIPSR2 */ 107 108 /* 109 * TX39 Series 110 */ 111 #define CP0_TX39_CACHE $7 112 113 /* 114 * Coprocessor 1 (FPU) register names 115 */ 116 #define CP1_REVISION $0 117 #define CP1_STATUS $31 118 119 /* 120 * FPU Status Register Values 121 */ 122 /* 123 * Status Register Values 124 */ 125 126 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ 127 #define FPU_CSR_COND 0x00800000 /* $fcc0 */ 128 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ 129 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ 130 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ 131 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ 132 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ 133 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ 134 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ 135 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 136 137 /* 138 * Bits 18 - 20 of the FPU Status Register will be read as 0, 139 * and should be written as zero. 140 */ 141 #define FPU_CSR_RSVD 0x001c0000 142 143 /* 144 * X the exception cause indicator 145 * E the exception enable 146 * S the sticky/flag bit 147 */ 148 #define FPU_CSR_ALL_X 0x0003f000 149 #define FPU_CSR_UNI_X 0x00020000 150 #define FPU_CSR_INV_X 0x00010000 151 #define FPU_CSR_DIV_X 0x00008000 152 #define FPU_CSR_OVF_X 0x00004000 153 #define FPU_CSR_UDF_X 0x00002000 154 #define FPU_CSR_INE_X 0x00001000 155 156 #define FPU_CSR_ALL_E 0x00000f80 157 #define FPU_CSR_INV_E 0x00000800 158 #define FPU_CSR_DIV_E 0x00000400 159 #define FPU_CSR_OVF_E 0x00000200 160 #define FPU_CSR_UDF_E 0x00000100 161 #define FPU_CSR_INE_E 0x00000080 162 163 #define FPU_CSR_ALL_S 0x0000007c 164 #define FPU_CSR_INV_S 0x00000040 165 #define FPU_CSR_DIV_S 0x00000020 166 #define FPU_CSR_OVF_S 0x00000010 167 #define FPU_CSR_UDF_S 0x00000008 168 #define FPU_CSR_INE_S 0x00000004 169 170 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ 171 #define FPU_CSR_RM 0x00000003 172 #define FPU_CSR_RN 0x0 /* nearest */ 173 #define FPU_CSR_RZ 0x1 /* towards zero */ 174 #define FPU_CSR_RU 0x2 /* towards +Infinity */ 175 #define FPU_CSR_RD 0x3 /* towards -Infinity */ 176 177 178 /* 179 * Values for PageMask register 180 */ 181 #ifdef CONFIG_CPU_VR41XX 182 183 /* Why doesn't stupidity hurt ... */ 184 185 #define PM_1K 0x00000000 186 #define PM_4K 0x00001800 187 #define PM_16K 0x00007800 188 #define PM_64K 0x0001f800 189 #define PM_256K 0x0007f800 190 191 #else 192 193 #define PM_4K 0x00000000 194 #define PM_8K 0x00002000 195 #define PM_16K 0x00006000 196 #define PM_32K 0x0000e000 197 #define PM_64K 0x0001e000 198 #define PM_128K 0x0003e000 199 #define PM_256K 0x0007e000 200 #define PM_512K 0x000fe000 201 #define PM_1M 0x001fe000 202 #define PM_2M 0x003fe000 203 #define PM_4M 0x007fe000 204 #define PM_8M 0x00ffe000 205 #define PM_16M 0x01ffe000 206 #define PM_32M 0x03ffe000 207 #define PM_64M 0x07ffe000 208 #define PM_256M 0x1fffe000 209 #define PM_1G 0x7fffe000 210 211 #endif 212 213 /* 214 * Default page size for a given kernel configuration 215 */ 216 #ifdef CONFIG_PAGE_SIZE_4KB 217 #define PM_DEFAULT_MASK PM_4K 218 #elif defined(CONFIG_PAGE_SIZE_8KB) 219 #define PM_DEFAULT_MASK PM_8K 220 #elif defined(CONFIG_PAGE_SIZE_16KB) 221 #define PM_DEFAULT_MASK PM_16K 222 #elif defined(CONFIG_PAGE_SIZE_32KB) 223 #define PM_DEFAULT_MASK PM_32K 224 #elif defined(CONFIG_PAGE_SIZE_64KB) 225 #define PM_DEFAULT_MASK PM_64K 226 #else 227 #error Bad page size configuration! 228 #endif 229 230 /* 231 * Default huge tlb size for a given kernel configuration 232 */ 233 #ifdef CONFIG_PAGE_SIZE_4KB 234 #define PM_HUGE_MASK PM_1M 235 #elif defined(CONFIG_PAGE_SIZE_8KB) 236 #define PM_HUGE_MASK PM_4M 237 #elif defined(CONFIG_PAGE_SIZE_16KB) 238 #define PM_HUGE_MASK PM_16M 239 #elif defined(CONFIG_PAGE_SIZE_32KB) 240 #define PM_HUGE_MASK PM_64M 241 #elif defined(CONFIG_PAGE_SIZE_64KB) 242 #define PM_HUGE_MASK PM_256M 243 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) 244 #error Bad page size configuration for hugetlbfs! 245 #endif 246 247 /* 248 * Values used for computation of new tlb entries 249 */ 250 #define PL_4K 12 251 #define PL_16K 14 252 #define PL_64K 16 253 #define PL_256K 18 254 #define PL_1M 20 255 #define PL_4M 22 256 #define PL_16M 24 257 #define PL_64M 26 258 #define PL_256M 28 259 260 /* 261 * PageGrain bits 262 */ 263 #define PG_RIE (_ULCAST_(1) << 31) 264 #define PG_XIE (_ULCAST_(1) << 30) 265 #define PG_ELPA (_ULCAST_(1) << 29) 266 #define PG_ESP (_ULCAST_(1) << 28) 267 268 /* 269 * R4x00 interrupt enable / cause bits 270 */ 271 #define IE_SW0 (_ULCAST_(1) << 8) 272 #define IE_SW1 (_ULCAST_(1) << 9) 273 #define IE_IRQ0 (_ULCAST_(1) << 10) 274 #define IE_IRQ1 (_ULCAST_(1) << 11) 275 #define IE_IRQ2 (_ULCAST_(1) << 12) 276 #define IE_IRQ3 (_ULCAST_(1) << 13) 277 #define IE_IRQ4 (_ULCAST_(1) << 14) 278 #define IE_IRQ5 (_ULCAST_(1) << 15) 279 280 /* 281 * R4x00 interrupt cause bits 282 */ 283 #define C_SW0 (_ULCAST_(1) << 8) 284 #define C_SW1 (_ULCAST_(1) << 9) 285 #define C_IRQ0 (_ULCAST_(1) << 10) 286 #define C_IRQ1 (_ULCAST_(1) << 11) 287 #define C_IRQ2 (_ULCAST_(1) << 12) 288 #define C_IRQ3 (_ULCAST_(1) << 13) 289 #define C_IRQ4 (_ULCAST_(1) << 14) 290 #define C_IRQ5 (_ULCAST_(1) << 15) 291 292 /* 293 * Bitfields in the R4xx0 cp0 status register 294 */ 295 #define ST0_IE 0x00000001 296 #define ST0_EXL 0x00000002 297 #define ST0_ERL 0x00000004 298 #define ST0_KSU 0x00000018 299 # define KSU_USER 0x00000010 300 # define KSU_SUPERVISOR 0x00000008 301 # define KSU_KERNEL 0x00000000 302 #define ST0_UX 0x00000020 303 #define ST0_SX 0x00000040 304 #define ST0_KX 0x00000080 305 #define ST0_DE 0x00010000 306 #define ST0_CE 0x00020000 307 308 /* 309 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate 310 * cacheops in userspace. This bit exists only on RM7000 and RM9000 311 * processors. 312 */ 313 #define ST0_CO 0x08000000 314 315 /* 316 * Bitfields in the R[23]000 cp0 status register. 317 */ 318 #define ST0_IEC 0x00000001 319 #define ST0_KUC 0x00000002 320 #define ST0_IEP 0x00000004 321 #define ST0_KUP 0x00000008 322 #define ST0_IEO 0x00000010 323 #define ST0_KUO 0x00000020 324 /* bits 6 & 7 are reserved on R[23]000 */ 325 #define ST0_ISC 0x00010000 326 #define ST0_SWC 0x00020000 327 #define ST0_CM 0x00080000 328 329 /* 330 * Bits specific to the R4640/R4650 331 */ 332 #define ST0_UM (_ULCAST_(1) << 4) 333 #define ST0_IL (_ULCAST_(1) << 23) 334 #define ST0_DL (_ULCAST_(1) << 24) 335 336 /* 337 * Enable the MIPS MDMX and DSP ASEs 338 */ 339 #define ST0_MX 0x01000000 340 341 /* 342 * Bitfields in the TX39 family CP0 Configuration Register 3 343 */ 344 #define TX39_CONF_ICS_SHIFT 19 345 #define TX39_CONF_ICS_MASK 0x00380000 346 #define TX39_CONF_ICS_1KB 0x00000000 347 #define TX39_CONF_ICS_2KB 0x00080000 348 #define TX39_CONF_ICS_4KB 0x00100000 349 #define TX39_CONF_ICS_8KB 0x00180000 350 #define TX39_CONF_ICS_16KB 0x00200000 351 352 #define TX39_CONF_DCS_SHIFT 16 353 #define TX39_CONF_DCS_MASK 0x00070000 354 #define TX39_CONF_DCS_1KB 0x00000000 355 #define TX39_CONF_DCS_2KB 0x00010000 356 #define TX39_CONF_DCS_4KB 0x00020000 357 #define TX39_CONF_DCS_8KB 0x00030000 358 #define TX39_CONF_DCS_16KB 0x00040000 359 360 #define TX39_CONF_CWFON 0x00004000 361 #define TX39_CONF_WBON 0x00002000 362 #define TX39_CONF_RF_SHIFT 10 363 #define TX39_CONF_RF_MASK 0x00000c00 364 #define TX39_CONF_DOZE 0x00000200 365 #define TX39_CONF_HALT 0x00000100 366 #define TX39_CONF_LOCK 0x00000080 367 #define TX39_CONF_ICE 0x00000020 368 #define TX39_CONF_DCE 0x00000010 369 #define TX39_CONF_IRSIZE_SHIFT 2 370 #define TX39_CONF_IRSIZE_MASK 0x0000000c 371 #define TX39_CONF_DRSIZE_SHIFT 0 372 #define TX39_CONF_DRSIZE_MASK 0x00000003 373 374 /* 375 * Status register bits available in all MIPS CPUs. 376 */ 377 #define ST0_IM 0x0000ff00 378 #define STATUSB_IP0 8 379 #define STATUSF_IP0 (_ULCAST_(1) << 8) 380 #define STATUSB_IP1 9 381 #define STATUSF_IP1 (_ULCAST_(1) << 9) 382 #define STATUSB_IP2 10 383 #define STATUSF_IP2 (_ULCAST_(1) << 10) 384 #define STATUSB_IP3 11 385 #define STATUSF_IP3 (_ULCAST_(1) << 11) 386 #define STATUSB_IP4 12 387 #define STATUSF_IP4 (_ULCAST_(1) << 12) 388 #define STATUSB_IP5 13 389 #define STATUSF_IP5 (_ULCAST_(1) << 13) 390 #define STATUSB_IP6 14 391 #define STATUSF_IP6 (_ULCAST_(1) << 14) 392 #define STATUSB_IP7 15 393 #define STATUSF_IP7 (_ULCAST_(1) << 15) 394 #define STATUSB_IP8 0 395 #define STATUSF_IP8 (_ULCAST_(1) << 0) 396 #define STATUSB_IP9 1 397 #define STATUSF_IP9 (_ULCAST_(1) << 1) 398 #define STATUSB_IP10 2 399 #define STATUSF_IP10 (_ULCAST_(1) << 2) 400 #define STATUSB_IP11 3 401 #define STATUSF_IP11 (_ULCAST_(1) << 3) 402 #define STATUSB_IP12 4 403 #define STATUSF_IP12 (_ULCAST_(1) << 4) 404 #define STATUSB_IP13 5 405 #define STATUSF_IP13 (_ULCAST_(1) << 5) 406 #define STATUSB_IP14 6 407 #define STATUSF_IP14 (_ULCAST_(1) << 6) 408 #define STATUSB_IP15 7 409 #define STATUSF_IP15 (_ULCAST_(1) << 7) 410 #define ST0_CH 0x00040000 411 #define ST0_NMI 0x00080000 412 #define ST0_SR 0x00100000 413 #define ST0_TS 0x00200000 414 #define ST0_BEV 0x00400000 415 #define ST0_RE 0x02000000 416 #define ST0_FR 0x04000000 417 #define ST0_CU 0xf0000000 418 #define ST0_CU0 0x10000000 419 #define ST0_CU1 0x20000000 420 #define ST0_CU2 0x40000000 421 #define ST0_CU3 0x80000000 422 #define ST0_XX 0x80000000 /* MIPS IV naming */ 423 424 /* 425 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) 426 * 427 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 428 */ 429 #define INTCTLB_IPPCI 26 430 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) 431 #define INTCTLB_IPTI 29 432 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) 433 434 /* 435 * Bitfields and bit numbers in the coprocessor 0 cause register. 436 * 437 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 438 */ 439 #define CAUSEB_EXCCODE 2 440 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 441 #define CAUSEB_IP 8 442 #define CAUSEF_IP (_ULCAST_(255) << 8) 443 #define CAUSEB_IP0 8 444 #define CAUSEF_IP0 (_ULCAST_(1) << 8) 445 #define CAUSEB_IP1 9 446 #define CAUSEF_IP1 (_ULCAST_(1) << 9) 447 #define CAUSEB_IP2 10 448 #define CAUSEF_IP2 (_ULCAST_(1) << 10) 449 #define CAUSEB_IP3 11 450 #define CAUSEF_IP3 (_ULCAST_(1) << 11) 451 #define CAUSEB_IP4 12 452 #define CAUSEF_IP4 (_ULCAST_(1) << 12) 453 #define CAUSEB_IP5 13 454 #define CAUSEF_IP5 (_ULCAST_(1) << 13) 455 #define CAUSEB_IP6 14 456 #define CAUSEF_IP6 (_ULCAST_(1) << 14) 457 #define CAUSEB_IP7 15 458 #define CAUSEF_IP7 (_ULCAST_(1) << 15) 459 #define CAUSEB_IV 23 460 #define CAUSEF_IV (_ULCAST_(1) << 23) 461 #define CAUSEB_PCI 26 462 #define CAUSEF_PCI (_ULCAST_(1) << 26) 463 #define CAUSEB_CE 28 464 #define CAUSEF_CE (_ULCAST_(3) << 28) 465 #define CAUSEB_TI 30 466 #define CAUSEF_TI (_ULCAST_(1) << 30) 467 #define CAUSEB_BD 31 468 #define CAUSEF_BD (_ULCAST_(1) << 31) 469 470 /* 471 * Bits in the coprocessor 0 config register. 472 */ 473 /* Generic bits. */ 474 #define CONF_CM_CACHABLE_NO_WA 0 475 #define CONF_CM_CACHABLE_WA 1 476 #define CONF_CM_UNCACHED 2 477 #define CONF_CM_CACHABLE_NONCOHERENT 3 478 #define CONF_CM_CACHABLE_CE 4 479 #define CONF_CM_CACHABLE_COW 5 480 #define CONF_CM_CACHABLE_CUW 6 481 #define CONF_CM_CACHABLE_ACCELERATED 7 482 #define CONF_CM_CMASK 7 483 #define CONF_BE (_ULCAST_(1) << 15) 484 485 /* Bits common to various processors. */ 486 #define CONF_CU (_ULCAST_(1) << 3) 487 #define CONF_DB (_ULCAST_(1) << 4) 488 #define CONF_IB (_ULCAST_(1) << 5) 489 #define CONF_DC (_ULCAST_(7) << 6) 490 #define CONF_IC (_ULCAST_(7) << 9) 491 #define CONF_EB (_ULCAST_(1) << 13) 492 #define CONF_EM (_ULCAST_(1) << 14) 493 #define CONF_SM (_ULCAST_(1) << 16) 494 #define CONF_SC (_ULCAST_(1) << 17) 495 #define CONF_EW (_ULCAST_(3) << 18) 496 #define CONF_EP (_ULCAST_(15)<< 24) 497 #define CONF_EC (_ULCAST_(7) << 28) 498 #define CONF_CM (_ULCAST_(1) << 31) 499 500 /* Bits specific to the R4xx0. */ 501 #define R4K_CONF_SW (_ULCAST_(1) << 20) 502 #define R4K_CONF_SS (_ULCAST_(1) << 21) 503 #define R4K_CONF_SB (_ULCAST_(3) << 22) 504 505 /* Bits specific to the R5000. */ 506 #define R5K_CONF_SE (_ULCAST_(1) << 12) 507 #define R5K_CONF_SS (_ULCAST_(3) << 20) 508 509 /* Bits specific to the RM7000. */ 510 #define RM7K_CONF_SE (_ULCAST_(1) << 3) 511 #define RM7K_CONF_TE (_ULCAST_(1) << 12) 512 #define RM7K_CONF_CLK (_ULCAST_(1) << 16) 513 #define RM7K_CONF_TC (_ULCAST_(1) << 17) 514 #define RM7K_CONF_SI (_ULCAST_(3) << 20) 515 #define RM7K_CONF_SC (_ULCAST_(1) << 31) 516 517 /* Bits specific to the R10000. */ 518 #define R10K_CONF_DN (_ULCAST_(3) << 3) 519 #define R10K_CONF_CT (_ULCAST_(1) << 5) 520 #define R10K_CONF_PE (_ULCAST_(1) << 6) 521 #define R10K_CONF_PM (_ULCAST_(3) << 7) 522 #define R10K_CONF_EC (_ULCAST_(15)<< 9) 523 #define R10K_CONF_SB (_ULCAST_(1) << 13) 524 #define R10K_CONF_SK (_ULCAST_(1) << 14) 525 #define R10K_CONF_SS (_ULCAST_(7) << 16) 526 #define R10K_CONF_SC (_ULCAST_(7) << 19) 527 #define R10K_CONF_DC (_ULCAST_(7) << 26) 528 #define R10K_CONF_IC (_ULCAST_(7) << 29) 529 530 /* Bits specific to the VR41xx. */ 531 #define VR41_CONF_CS (_ULCAST_(1) << 12) 532 #define VR41_CONF_P4K (_ULCAST_(1) << 13) 533 #define VR41_CONF_BP (_ULCAST_(1) << 16) 534 #define VR41_CONF_M16 (_ULCAST_(1) << 20) 535 #define VR41_CONF_AD (_ULCAST_(1) << 23) 536 537 /* Bits specific to the R30xx. */ 538 #define R30XX_CONF_FDM (_ULCAST_(1) << 19) 539 #define R30XX_CONF_REV (_ULCAST_(1) << 22) 540 #define R30XX_CONF_AC (_ULCAST_(1) << 23) 541 #define R30XX_CONF_RF (_ULCAST_(1) << 24) 542 #define R30XX_CONF_HALT (_ULCAST_(1) << 25) 543 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 544 #define R30XX_CONF_DBR (_ULCAST_(1) << 29) 545 #define R30XX_CONF_SB (_ULCAST_(1) << 30) 546 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 547 548 /* Bits specific to the TX49. */ 549 #define TX49_CONF_DC (_ULCAST_(1) << 16) 550 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 551 #define TX49_CONF_HALT (_ULCAST_(1) << 18) 552 #define TX49_CONF_CWFON (_ULCAST_(1) << 27) 553 554 /* Bits specific to the MIPS32/64 PRA. */ 555 #define MIPS_CONF_MT (_ULCAST_(7) << 7) 556 #define MIPS_CONF_AR (_ULCAST_(7) << 10) 557 #define MIPS_CONF_AT (_ULCAST_(3) << 13) 558 #define MIPS_CONF_M (_ULCAST_(1) << 31) 559 560 /* 561 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 562 */ 563 #define MIPS_CONF1_FP (_ULCAST_(1) << 0) 564 #define MIPS_CONF1_EP (_ULCAST_(1) << 1) 565 #define MIPS_CONF1_CA (_ULCAST_(1) << 2) 566 #define MIPS_CONF1_WR (_ULCAST_(1) << 3) 567 #define MIPS_CONF1_PC (_ULCAST_(1) << 4) 568 #define MIPS_CONF1_MD (_ULCAST_(1) << 5) 569 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 570 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) 571 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) 572 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) 573 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) 574 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) 575 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) 576 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) 577 578 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 579 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 580 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 581 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 582 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 583 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 584 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 585 #define MIPS_CONF2_TU (_ULCAST_(7) << 28) 586 587 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 588 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 589 #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 590 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 591 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 592 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 593 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 594 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 595 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 596 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 597 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 598 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 599 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 600 601 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 602 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 603 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 604 605 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 606 607 #define MIPS_CONF7_WII (_ULCAST_(1) << 31) 608 609 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 610 611 612 /* 613 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 614 */ 615 #define MIPS_FPIR_S (_ULCAST_(1) << 16) 616 #define MIPS_FPIR_D (_ULCAST_(1) << 17) 617 #define MIPS_FPIR_PS (_ULCAST_(1) << 18) 618 #define MIPS_FPIR_3D (_ULCAST_(1) << 19) 619 #define MIPS_FPIR_W (_ULCAST_(1) << 20) 620 #define MIPS_FPIR_L (_ULCAST_(1) << 21) 621 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 622 623 #ifndef __ASSEMBLY__ 624 625 /* 626 * Functions to access the R10000 performance counters. These are basically 627 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 628 * performance counter number encoded into bits 1 ... 5 of the instruction. 629 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware 630 * disassembler these will look like an access to sel 0 or 1. 631 */ 632 #define read_r10k_perf_cntr(counter) \ 633 ({ \ 634 unsigned int __res; \ 635 __asm__ __volatile__( \ 636 "mfpc\t%0, %1" \ 637 : "=r" (__res) \ 638 : "i" (counter)); \ 639 \ 640 __res; \ 641 }) 642 643 #define write_r10k_perf_cntr(counter,val) \ 644 do { \ 645 __asm__ __volatile__( \ 646 "mtpc\t%0, %1" \ 647 : \ 648 : "r" (val), "i" (counter)); \ 649 } while (0) 650 651 #define read_r10k_perf_event(counter) \ 652 ({ \ 653 unsigned int __res; \ 654 __asm__ __volatile__( \ 655 "mfps\t%0, %1" \ 656 : "=r" (__res) \ 657 : "i" (counter)); \ 658 \ 659 __res; \ 660 }) 661 662 #define write_r10k_perf_cntl(counter,val) \ 663 do { \ 664 __asm__ __volatile__( \ 665 "mtps\t%0, %1" \ 666 : \ 667 : "r" (val), "i" (counter)); \ 668 } while (0) 669 670 671 /* 672 * Macros to access the system control coprocessor 673 */ 674 675 #define __read_32bit_c0_register(source, sel) \ 676 ({ int __res; \ 677 if (sel == 0) \ 678 __asm__ __volatile__( \ 679 "mfc0\t%0, " #source "\n\t" \ 680 : "=r" (__res)); \ 681 else \ 682 __asm__ __volatile__( \ 683 ".set\tmips32\n\t" \ 684 "mfc0\t%0, " #source ", " #sel "\n\t" \ 685 ".set\tmips0\n\t" \ 686 : "=r" (__res)); \ 687 __res; \ 688 }) 689 690 #define __read_64bit_c0_register(source, sel) \ 691 ({ unsigned long long __res; \ 692 if (sizeof(unsigned long) == 4) \ 693 __res = __read_64bit_c0_split(source, sel); \ 694 else if (sel == 0) \ 695 __asm__ __volatile__( \ 696 ".set\tmips3\n\t" \ 697 "dmfc0\t%0, " #source "\n\t" \ 698 ".set\tmips0" \ 699 : "=r" (__res)); \ 700 else \ 701 __asm__ __volatile__( \ 702 ".set\tmips64\n\t" \ 703 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 704 ".set\tmips0" \ 705 : "=r" (__res)); \ 706 __res; \ 707 }) 708 709 #define __write_32bit_c0_register(register, sel, value) \ 710 do { \ 711 if (sel == 0) \ 712 __asm__ __volatile__( \ 713 "mtc0\t%z0, " #register "\n\t" \ 714 : : "Jr" ((unsigned int)(value))); \ 715 else \ 716 __asm__ __volatile__( \ 717 ".set\tmips32\n\t" \ 718 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 719 ".set\tmips0" \ 720 : : "Jr" ((unsigned int)(value))); \ 721 } while (0) 722 723 #define __write_64bit_c0_register(register, sel, value) \ 724 do { \ 725 if (sizeof(unsigned long) == 4) \ 726 __write_64bit_c0_split(register, sel, value); \ 727 else if (sel == 0) \ 728 __asm__ __volatile__( \ 729 ".set\tmips3\n\t" \ 730 "dmtc0\t%z0, " #register "\n\t" \ 731 ".set\tmips0" \ 732 : : "Jr" (value)); \ 733 else \ 734 __asm__ __volatile__( \ 735 ".set\tmips64\n\t" \ 736 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 737 ".set\tmips0" \ 738 : : "Jr" (value)); \ 739 } while (0) 740 741 #define __read_ulong_c0_register(reg, sel) \ 742 ((sizeof(unsigned long) == 4) ? \ 743 (unsigned long) __read_32bit_c0_register(reg, sel) : \ 744 (unsigned long) __read_64bit_c0_register(reg, sel)) 745 746 #define __write_ulong_c0_register(reg, sel, val) \ 747 do { \ 748 if (sizeof(unsigned long) == 4) \ 749 __write_32bit_c0_register(reg, sel, val); \ 750 else \ 751 __write_64bit_c0_register(reg, sel, val); \ 752 } while (0) 753 754 /* 755 * On RM7000/RM9000 these are uses to access cop0 set 1 registers 756 */ 757 #define __read_32bit_c0_ctrl_register(source) \ 758 ({ int __res; \ 759 __asm__ __volatile__( \ 760 "cfc0\t%0, " #source "\n\t" \ 761 : "=r" (__res)); \ 762 __res; \ 763 }) 764 765 #define __write_32bit_c0_ctrl_register(register, value) \ 766 do { \ 767 __asm__ __volatile__( \ 768 "ctc0\t%z0, " #register "\n\t" \ 769 : : "Jr" ((unsigned int)(value))); \ 770 } while (0) 771 772 /* 773 * These versions are only needed for systems with more than 38 bits of 774 * physical address space running the 32-bit kernel. That's none atm :-) 775 */ 776 #define __read_64bit_c0_split(source, sel) \ 777 ({ \ 778 unsigned long long __val; \ 779 unsigned long __flags; \ 780 \ 781 local_irq_save(__flags); \ 782 if (sel == 0) \ 783 __asm__ __volatile__( \ 784 ".set\tmips64\n\t" \ 785 "dmfc0\t%M0, " #source "\n\t" \ 786 "dsll\t%L0, %M0, 32\n\t" \ 787 "dsra\t%M0, %M0, 32\n\t" \ 788 "dsra\t%L0, %L0, 32\n\t" \ 789 ".set\tmips0" \ 790 : "=r" (__val)); \ 791 else \ 792 __asm__ __volatile__( \ 793 ".set\tmips64\n\t" \ 794 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 795 "dsll\t%L0, %M0, 32\n\t" \ 796 "dsra\t%M0, %M0, 32\n\t" \ 797 "dsra\t%L0, %L0, 32\n\t" \ 798 ".set\tmips0" \ 799 : "=r" (__val)); \ 800 local_irq_restore(__flags); \ 801 \ 802 __val; \ 803 }) 804 805 #define __write_64bit_c0_split(source, sel, val) \ 806 do { \ 807 unsigned long __flags; \ 808 \ 809 local_irq_save(__flags); \ 810 if (sel == 0) \ 811 __asm__ __volatile__( \ 812 ".set\tmips64\n\t" \ 813 "dsll\t%L0, %L0, 32\n\t" \ 814 "dsrl\t%L0, %L0, 32\n\t" \ 815 "dsll\t%M0, %M0, 32\n\t" \ 816 "or\t%L0, %L0, %M0\n\t" \ 817 "dmtc0\t%L0, " #source "\n\t" \ 818 ".set\tmips0" \ 819 : : "r" (val)); \ 820 else \ 821 __asm__ __volatile__( \ 822 ".set\tmips64\n\t" \ 823 "dsll\t%L0, %L0, 32\n\t" \ 824 "dsrl\t%L0, %L0, 32\n\t" \ 825 "dsll\t%M0, %M0, 32\n\t" \ 826 "or\t%L0, %L0, %M0\n\t" \ 827 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 828 ".set\tmips0" \ 829 : : "r" (val)); \ 830 local_irq_restore(__flags); \ 831 } while (0) 832 833 #define read_c0_index() __read_32bit_c0_register($0, 0) 834 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 835 836 #define read_c0_random() __read_32bit_c0_register($1, 0) 837 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 838 839 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 840 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 841 842 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 843 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 844 845 #define read_c0_conf() __read_32bit_c0_register($3, 0) 846 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 847 848 #define read_c0_context() __read_ulong_c0_register($4, 0) 849 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 850 851 #define read_c0_userlocal() __read_ulong_c0_register($4, 2) 852 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 853 854 #define read_c0_pagemask() __read_32bit_c0_register($5, 0) 855 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 856 857 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1) 858 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) 859 860 #define read_c0_wired() __read_32bit_c0_register($6, 0) 861 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 862 863 #define read_c0_info() __read_32bit_c0_register($7, 0) 864 865 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 866 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 867 868 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 869 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) 870 871 #define read_c0_count() __read_32bit_c0_register($9, 0) 872 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 873 874 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ 875 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 876 877 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ 878 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 879 880 #define read_c0_entryhi() __read_ulong_c0_register($10, 0) 881 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 882 883 #define read_c0_compare() __read_32bit_c0_register($11, 0) 884 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 885 886 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ 887 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 888 889 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ 890 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 891 892 #define read_c0_status() __read_32bit_c0_register($12, 0) 893 #ifdef CONFIG_MIPS_MT_SMTC 894 #define write_c0_status(val) \ 895 do { \ 896 __write_32bit_c0_register($12, 0, val); \ 897 __ehb(); \ 898 } while (0) 899 #else 900 /* 901 * Legacy non-SMTC code, which may be hazardous 902 * but which might not support EHB 903 */ 904 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 905 #endif /* CONFIG_MIPS_MT_SMTC */ 906 907 #define read_c0_cause() __read_32bit_c0_register($13, 0) 908 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 909 910 #define read_c0_epc() __read_ulong_c0_register($14, 0) 911 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 912 913 #define read_c0_prid() __read_32bit_c0_register($15, 0) 914 915 #define read_c0_config() __read_32bit_c0_register($16, 0) 916 #define read_c0_config1() __read_32bit_c0_register($16, 1) 917 #define read_c0_config2() __read_32bit_c0_register($16, 2) 918 #define read_c0_config3() __read_32bit_c0_register($16, 3) 919 #define read_c0_config4() __read_32bit_c0_register($16, 4) 920 #define read_c0_config5() __read_32bit_c0_register($16, 5) 921 #define read_c0_config6() __read_32bit_c0_register($16, 6) 922 #define read_c0_config7() __read_32bit_c0_register($16, 7) 923 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 924 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 925 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 926 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 927 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) 928 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) 929 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 930 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 931 932 /* 933 * The WatchLo register. There may be up to 8 of them. 934 */ 935 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 936 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 937 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 938 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 939 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 940 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 941 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 942 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 943 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 944 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 945 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 946 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 947 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 948 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 949 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 950 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 951 952 /* 953 * The WatchHi register. There may be up to 8 of them. 954 */ 955 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 956 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 957 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 958 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 959 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 960 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 961 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 962 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 963 964 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 965 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 966 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 967 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 968 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 969 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 970 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 971 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 972 973 #define read_c0_xcontext() __read_ulong_c0_register($20, 0) 974 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 975 976 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) 977 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 978 979 #define read_c0_framemask() __read_32bit_c0_register($21, 0) 980 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 981 982 #define read_c0_diag() __read_32bit_c0_register($22, 0) 983 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 984 985 #define read_c0_diag1() __read_32bit_c0_register($22, 1) 986 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) 987 988 #define read_c0_diag2() __read_32bit_c0_register($22, 2) 989 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) 990 991 #define read_c0_diag3() __read_32bit_c0_register($22, 3) 992 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) 993 994 #define read_c0_diag4() __read_32bit_c0_register($22, 4) 995 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) 996 997 #define read_c0_diag5() __read_32bit_c0_register($22, 5) 998 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) 999 1000 #define read_c0_debug() __read_32bit_c0_register($23, 0) 1001 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 1002 1003 #define read_c0_depc() __read_ulong_c0_register($24, 0) 1004 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 1005 1006 /* 1007 * MIPS32 / MIPS64 performance counters 1008 */ 1009 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 1010 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 1011 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 1012 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 1013 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) 1014 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) 1015 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 1016 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 1017 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 1018 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 1019 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) 1020 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) 1021 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 1022 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 1023 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 1024 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 1025 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) 1026 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) 1027 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 1028 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 1029 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 1030 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 1031 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) 1032 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) 1033 1034 #define read_c0_ecc() __read_32bit_c0_register($26, 0) 1035 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 1036 1037 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 1038 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 1039 1040 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 1041 1042 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 1043 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 1044 1045 #define read_c0_taglo() __read_32bit_c0_register($28, 0) 1046 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 1047 1048 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) 1049 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) 1050 1051 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3) 1052 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) 1053 1054 #define read_c0_staglo() __read_32bit_c0_register($28, 4) 1055 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) 1056 1057 #define read_c0_taghi() __read_32bit_c0_register($29, 0) 1058 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 1059 1060 #define read_c0_errorepc() __read_ulong_c0_register($30, 0) 1061 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 1062 1063 /* MIPSR2 */ 1064 #define read_c0_hwrena() __read_32bit_c0_register($7, 0) 1065 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 1066 1067 #define read_c0_intctl() __read_32bit_c0_register($12, 1) 1068 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) 1069 1070 #define read_c0_srsctl() __read_32bit_c0_register($12, 2) 1071 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) 1072 1073 #define read_c0_srsmap() __read_32bit_c0_register($12, 3) 1074 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 1075 1076 #define read_c0_ebase() __read_32bit_c0_register($15, 1) 1077 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1078 1079 1080 /* Cavium OCTEON (cnMIPS) */ 1081 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1082 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) 1083 1084 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) 1085 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) 1086 1087 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) 1088 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) 1089 /* 1090 * The cacheerr registers are not standardized. On OCTEON, they are 1091 * 64 bits wide. 1092 */ 1093 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) 1094 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) 1095 1096 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) 1097 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) 1098 1099 /* BMIPS3300 */ 1100 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0) 1101 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) 1102 1103 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4) 1104 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) 1105 1106 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) 1107 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) 1108 1109 /* BMIPS43xx */ 1110 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) 1111 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) 1112 1113 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2) 1114 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) 1115 1116 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3) 1117 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) 1118 1119 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5) 1120 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) 1121 1122 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6) 1123 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) 1124 1125 /* BMIPS5000 */ 1126 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0) 1127 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) 1128 1129 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1) 1130 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) 1131 1132 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2) 1133 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) 1134 1135 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3) 1136 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) 1137 1138 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4) 1139 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) 1140 1141 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7) 1142 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) 1143 1144 /* 1145 * Macros to access the floating point coprocessor control registers 1146 */ 1147 #define read_32bit_cp1_register(source) \ 1148 ({ \ 1149 int __res; \ 1150 \ 1151 __asm__ __volatile__( \ 1152 " .set push \n" \ 1153 " .set reorder \n" \ 1154 " # gas fails to assemble cfc1 for some archs, \n" \ 1155 " # like Octeon. \n" \ 1156 " .set mips1 \n" \ 1157 " cfc1 %0,"STR(source)" \n" \ 1158 " .set pop \n" \ 1159 : "=r" (__res)); \ 1160 __res; \ 1161 }) 1162 1163 #ifdef HAVE_AS_DSP 1164 #define rddsp(mask) \ 1165 ({ \ 1166 unsigned int __dspctl; \ 1167 \ 1168 __asm__ __volatile__( \ 1169 " .set push \n" \ 1170 " .set dsp \n" \ 1171 " rddsp %0, %x1 \n" \ 1172 " .set pop \n" \ 1173 : "=r" (__dspctl) \ 1174 : "i" (mask)); \ 1175 __dspctl; \ 1176 }) 1177 1178 #define wrdsp(val, mask) \ 1179 do { \ 1180 __asm__ __volatile__( \ 1181 " .set push \n" \ 1182 " .set dsp \n" \ 1183 " wrdsp %0, %x1 \n" \ 1184 " .set pop \n" \ 1185 : \ 1186 : "r" (val), "i" (mask)); \ 1187 } while (0) 1188 1189 #define mflo0() \ 1190 ({ \ 1191 long mflo0; \ 1192 __asm__( \ 1193 " .set push \n" \ 1194 " .set dsp \n" \ 1195 " mflo %0, $ac0 \n" \ 1196 " .set pop \n" \ 1197 : "=r" (mflo0)); \ 1198 mflo0; \ 1199 }) 1200 1201 #define mflo1() \ 1202 ({ \ 1203 long mflo1; \ 1204 __asm__( \ 1205 " .set push \n" \ 1206 " .set dsp \n" \ 1207 " mflo %0, $ac1 \n" \ 1208 " .set pop \n" \ 1209 : "=r" (mflo1)); \ 1210 mflo1; \ 1211 }) 1212 1213 #define mflo2() \ 1214 ({ \ 1215 long mflo2; \ 1216 __asm__( \ 1217 " .set push \n" \ 1218 " .set dsp \n" \ 1219 " mflo %0, $ac2 \n" \ 1220 " .set pop \n" \ 1221 : "=r" (mflo2)); \ 1222 mflo2; \ 1223 }) 1224 1225 #define mflo3() \ 1226 ({ \ 1227 long mflo3; \ 1228 __asm__( \ 1229 " .set push \n" \ 1230 " .set dsp \n" \ 1231 " mflo %0, $ac3 \n" \ 1232 " .set pop \n" \ 1233 : "=r" (mflo3)); \ 1234 mflo3; \ 1235 }) 1236 1237 #define mfhi0() \ 1238 ({ \ 1239 long mfhi0; \ 1240 __asm__( \ 1241 " .set push \n" \ 1242 " .set dsp \n" \ 1243 " mfhi %0, $ac0 \n" \ 1244 " .set pop \n" \ 1245 : "=r" (mfhi0)); \ 1246 mfhi0; \ 1247 }) 1248 1249 #define mfhi1() \ 1250 ({ \ 1251 long mfhi1; \ 1252 __asm__( \ 1253 " .set push \n" \ 1254 " .set dsp \n" \ 1255 " mfhi %0, $ac1 \n" \ 1256 " .set pop \n" \ 1257 : "=r" (mfhi1)); \ 1258 mfhi1; \ 1259 }) 1260 1261 #define mfhi2() \ 1262 ({ \ 1263 long mfhi2; \ 1264 __asm__( \ 1265 " .set push \n" \ 1266 " .set dsp \n" \ 1267 " mfhi %0, $ac2 \n" \ 1268 " .set pop \n" \ 1269 : "=r" (mfhi2)); \ 1270 mfhi2; \ 1271 }) 1272 1273 #define mfhi3() \ 1274 ({ \ 1275 long mfhi3; \ 1276 __asm__( \ 1277 " .set push \n" \ 1278 " .set dsp \n" \ 1279 " mfhi %0, $ac3 \n" \ 1280 " .set pop \n" \ 1281 : "=r" (mfhi3)); \ 1282 mfhi3; \ 1283 }) 1284 1285 1286 #define mtlo0(x) \ 1287 ({ \ 1288 __asm__( \ 1289 " .set push \n" \ 1290 " .set dsp \n" \ 1291 " mtlo %0, $ac0 \n" \ 1292 " .set pop \n" \ 1293 : \ 1294 : "r" (x)); \ 1295 }) 1296 1297 #define mtlo1(x) \ 1298 ({ \ 1299 __asm__( \ 1300 " .set push \n" \ 1301 " .set dsp \n" \ 1302 " mtlo %0, $ac1 \n" \ 1303 " .set pop \n" \ 1304 : \ 1305 : "r" (x)); \ 1306 }) 1307 1308 #define mtlo2(x) \ 1309 ({ \ 1310 __asm__( \ 1311 " .set push \n" \ 1312 " .set dsp \n" \ 1313 " mtlo %0, $ac2 \n" \ 1314 " .set pop \n" \ 1315 : \ 1316 : "r" (x)); \ 1317 }) 1318 1319 #define mtlo3(x) \ 1320 ({ \ 1321 __asm__( \ 1322 " .set push \n" \ 1323 " .set dsp \n" \ 1324 " mtlo %0, $ac3 \n" \ 1325 " .set pop \n" \ 1326 : \ 1327 : "r" (x)); \ 1328 }) 1329 1330 #define mthi0(x) \ 1331 ({ \ 1332 __asm__( \ 1333 " .set push \n" \ 1334 " .set dsp \n" \ 1335 " mthi %0, $ac0 \n" \ 1336 " .set pop \n" \ 1337 : \ 1338 : "r" (x)); \ 1339 }) 1340 1341 #define mthi1(x) \ 1342 ({ \ 1343 __asm__( \ 1344 " .set push \n" \ 1345 " .set dsp \n" \ 1346 " mthi %0, $ac1 \n" \ 1347 " .set pop \n" \ 1348 : \ 1349 : "r" (x)); \ 1350 }) 1351 1352 #define mthi2(x) \ 1353 ({ \ 1354 __asm__( \ 1355 " .set push \n" \ 1356 " .set dsp \n" \ 1357 " mthi %0, $ac2 \n" \ 1358 " .set pop \n" \ 1359 : \ 1360 : "r" (x)); \ 1361 }) 1362 1363 #define mthi3(x) \ 1364 ({ \ 1365 __asm__( \ 1366 " .set push \n" \ 1367 " .set dsp \n" \ 1368 " mthi %0, $ac3 \n" \ 1369 " .set pop \n" \ 1370 : \ 1371 : "r" (x)); \ 1372 }) 1373 1374 #else 1375 1376 #ifdef CONFIG_CPU_MICROMIPS 1377 #define rddsp(mask) \ 1378 ({ \ 1379 unsigned int __res; \ 1380 \ 1381 __asm__ __volatile__( \ 1382 " .set push \n" \ 1383 " .set noat \n" \ 1384 " # rddsp $1, %x1 \n" \ 1385 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ 1386 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ 1387 " move %0, $1 \n" \ 1388 " .set pop \n" \ 1389 : "=r" (__res) \ 1390 : "i" (mask)); \ 1391 __res; \ 1392 }) 1393 1394 #define wrdsp(val, mask) \ 1395 do { \ 1396 __asm__ __volatile__( \ 1397 " .set push \n" \ 1398 " .set noat \n" \ 1399 " move $1, %0 \n" \ 1400 " # wrdsp $1, %x1 \n" \ 1401 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ 1402 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ 1403 " .set pop \n" \ 1404 : \ 1405 : "r" (val), "i" (mask)); \ 1406 } while (0) 1407 1408 #define _umips_dsp_mfxxx(ins) \ 1409 ({ \ 1410 unsigned long __treg; \ 1411 \ 1412 __asm__ __volatile__( \ 1413 " .set push \n" \ 1414 " .set noat \n" \ 1415 " .hword 0x0001 \n" \ 1416 " .hword %x1 \n" \ 1417 " move %0, $1 \n" \ 1418 " .set pop \n" \ 1419 : "=r" (__treg) \ 1420 : "i" (ins)); \ 1421 __treg; \ 1422 }) 1423 1424 #define _umips_dsp_mtxxx(val, ins) \ 1425 do { \ 1426 __asm__ __volatile__( \ 1427 " .set push \n" \ 1428 " .set noat \n" \ 1429 " move $1, %0 \n" \ 1430 " .hword 0x0001 \n" \ 1431 " .hword %x1 \n" \ 1432 " .set pop \n" \ 1433 : \ 1434 : "r" (val), "i" (ins)); \ 1435 } while (0) 1436 1437 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) 1438 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) 1439 1440 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) 1441 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) 1442 1443 #define mflo0() _umips_dsp_mflo(0) 1444 #define mflo1() _umips_dsp_mflo(1) 1445 #define mflo2() _umips_dsp_mflo(2) 1446 #define mflo3() _umips_dsp_mflo(3) 1447 1448 #define mfhi0() _umips_dsp_mfhi(0) 1449 #define mfhi1() _umips_dsp_mfhi(1) 1450 #define mfhi2() _umips_dsp_mfhi(2) 1451 #define mfhi3() _umips_dsp_mfhi(3) 1452 1453 #define mtlo0(x) _umips_dsp_mtlo(x, 0) 1454 #define mtlo1(x) _umips_dsp_mtlo(x, 1) 1455 #define mtlo2(x) _umips_dsp_mtlo(x, 2) 1456 #define mtlo3(x) _umips_dsp_mtlo(x, 3) 1457 1458 #define mthi0(x) _umips_dsp_mthi(x, 0) 1459 #define mthi1(x) _umips_dsp_mthi(x, 1) 1460 #define mthi2(x) _umips_dsp_mthi(x, 2) 1461 #define mthi3(x) _umips_dsp_mthi(x, 3) 1462 1463 #else /* !CONFIG_CPU_MICROMIPS */ 1464 #define rddsp(mask) \ 1465 ({ \ 1466 unsigned int __res; \ 1467 \ 1468 __asm__ __volatile__( \ 1469 " .set push \n" \ 1470 " .set noat \n" \ 1471 " # rddsp $1, %x1 \n" \ 1472 " .word 0x7c000cb8 | (%x1 << 16) \n" \ 1473 " move %0, $1 \n" \ 1474 " .set pop \n" \ 1475 : "=r" (__res) \ 1476 : "i" (mask)); \ 1477 __res; \ 1478 }) 1479 1480 #define wrdsp(val, mask) \ 1481 do { \ 1482 __asm__ __volatile__( \ 1483 " .set push \n" \ 1484 " .set noat \n" \ 1485 " move $1, %0 \n" \ 1486 " # wrdsp $1, %x1 \n" \ 1487 " .word 0x7c2004f8 | (%x1 << 11) \n" \ 1488 " .set pop \n" \ 1489 : \ 1490 : "r" (val), "i" (mask)); \ 1491 } while (0) 1492 1493 #define _dsp_mfxxx(ins) \ 1494 ({ \ 1495 unsigned long __treg; \ 1496 \ 1497 __asm__ __volatile__( \ 1498 " .set push \n" \ 1499 " .set noat \n" \ 1500 " .word (0x00000810 | %1) \n" \ 1501 " move %0, $1 \n" \ 1502 " .set pop \n" \ 1503 : "=r" (__treg) \ 1504 : "i" (ins)); \ 1505 __treg; \ 1506 }) 1507 1508 #define _dsp_mtxxx(val, ins) \ 1509 do { \ 1510 __asm__ __volatile__( \ 1511 " .set push \n" \ 1512 " .set noat \n" \ 1513 " move $1, %0 \n" \ 1514 " .word (0x00200011 | %1) \n" \ 1515 " .set pop \n" \ 1516 : \ 1517 : "r" (val), "i" (ins)); \ 1518 } while (0) 1519 1520 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) 1521 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) 1522 1523 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) 1524 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) 1525 1526 #define mflo0() _dsp_mflo(0) 1527 #define mflo1() _dsp_mflo(1) 1528 #define mflo2() _dsp_mflo(2) 1529 #define mflo3() _dsp_mflo(3) 1530 1531 #define mfhi0() _dsp_mfhi(0) 1532 #define mfhi1() _dsp_mfhi(1) 1533 #define mfhi2() _dsp_mfhi(2) 1534 #define mfhi3() _dsp_mfhi(3) 1535 1536 #define mtlo0(x) _dsp_mtlo(x, 0) 1537 #define mtlo1(x) _dsp_mtlo(x, 1) 1538 #define mtlo2(x) _dsp_mtlo(x, 2) 1539 #define mtlo3(x) _dsp_mtlo(x, 3) 1540 1541 #define mthi0(x) _dsp_mthi(x, 0) 1542 #define mthi1(x) _dsp_mthi(x, 1) 1543 #define mthi2(x) _dsp_mthi(x, 2) 1544 #define mthi3(x) _dsp_mthi(x, 3) 1545 1546 #endif /* CONFIG_CPU_MICROMIPS */ 1547 #endif 1548 1549 /* 1550 * TLB operations. 1551 * 1552 * It is responsibility of the caller to take care of any TLB hazards. 1553 */ 1554 static inline void tlb_probe(void) 1555 { 1556 __asm__ __volatile__( 1557 ".set noreorder\n\t" 1558 "tlbp\n\t" 1559 ".set reorder"); 1560 } 1561 1562 static inline void tlb_read(void) 1563 { 1564 #if MIPS34K_MISSED_ITLB_WAR 1565 int res = 0; 1566 1567 __asm__ __volatile__( 1568 " .set push \n" 1569 " .set noreorder \n" 1570 " .set noat \n" 1571 " .set mips32r2 \n" 1572 " .word 0x41610001 # dvpe $1 \n" 1573 " move %0, $1 \n" 1574 " ehb \n" 1575 " .set pop \n" 1576 : "=r" (res)); 1577 1578 instruction_hazard(); 1579 #endif 1580 1581 __asm__ __volatile__( 1582 ".set noreorder\n\t" 1583 "tlbr\n\t" 1584 ".set reorder"); 1585 1586 #if MIPS34K_MISSED_ITLB_WAR 1587 if ((res & _ULCAST_(1))) 1588 __asm__ __volatile__( 1589 " .set push \n" 1590 " .set noreorder \n" 1591 " .set noat \n" 1592 " .set mips32r2 \n" 1593 " .word 0x41600021 # evpe \n" 1594 " ehb \n" 1595 " .set pop \n"); 1596 #endif 1597 } 1598 1599 static inline void tlb_write_indexed(void) 1600 { 1601 __asm__ __volatile__( 1602 ".set noreorder\n\t" 1603 "tlbwi\n\t" 1604 ".set reorder"); 1605 } 1606 1607 static inline void tlb_write_random(void) 1608 { 1609 __asm__ __volatile__( 1610 ".set noreorder\n\t" 1611 "tlbwr\n\t" 1612 ".set reorder"); 1613 } 1614 1615 /* 1616 * Manipulate bits in a c0 register. 1617 */ 1618 #ifndef CONFIG_MIPS_MT_SMTC 1619 /* 1620 * SMTC Linux requires shutting-down microthread scheduling 1621 * during CP0 register read-modify-write sequences. 1622 */ 1623 #define __BUILD_SET_C0(name) \ 1624 static inline unsigned int \ 1625 set_c0_##name(unsigned int set) \ 1626 { \ 1627 unsigned int res, new; \ 1628 \ 1629 res = read_c0_##name(); \ 1630 new = res | set; \ 1631 write_c0_##name(new); \ 1632 \ 1633 return res; \ 1634 } \ 1635 \ 1636 static inline unsigned int \ 1637 clear_c0_##name(unsigned int clear) \ 1638 { \ 1639 unsigned int res, new; \ 1640 \ 1641 res = read_c0_##name(); \ 1642 new = res & ~clear; \ 1643 write_c0_##name(new); \ 1644 \ 1645 return res; \ 1646 } \ 1647 \ 1648 static inline unsigned int \ 1649 change_c0_##name(unsigned int change, unsigned int val) \ 1650 { \ 1651 unsigned int res, new; \ 1652 \ 1653 res = read_c0_##name(); \ 1654 new = res & ~change; \ 1655 new |= (val & change); \ 1656 write_c0_##name(new); \ 1657 \ 1658 return res; \ 1659 } 1660 1661 #else /* SMTC versions that manage MT scheduling */ 1662 1663 #include <linux/irqflags.h> 1664 1665 /* 1666 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with 1667 * header file recursion. 1668 */ 1669 static inline unsigned int __dmt(void) 1670 { 1671 int res; 1672 1673 __asm__ __volatile__( 1674 " .set push \n" 1675 " .set mips32r2 \n" 1676 " .set noat \n" 1677 " .word 0x41610BC1 # dmt $1 \n" 1678 " ehb \n" 1679 " move %0, $1 \n" 1680 " .set pop \n" 1681 : "=r" (res)); 1682 1683 instruction_hazard(); 1684 1685 return res; 1686 } 1687 1688 #define __VPECONTROL_TE_SHIFT 15 1689 #define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT) 1690 1691 #define __EMT_ENABLE __VPECONTROL_TE 1692 1693 static inline void __emt(unsigned int previous) 1694 { 1695 if ((previous & __EMT_ENABLE)) 1696 __asm__ __volatile__( 1697 " .set mips32r2 \n" 1698 " .word 0x41600be1 # emt \n" 1699 " ehb \n" 1700 " .set mips0 \n"); 1701 } 1702 1703 static inline void __ehb(void) 1704 { 1705 __asm__ __volatile__( 1706 " .set mips32r2 \n" 1707 " ehb \n" " .set mips0 \n"); 1708 } 1709 1710 /* 1711 * Note that local_irq_save/restore affect TC-specific IXMT state, 1712 * not Status.IE as in non-SMTC kernel. 1713 */ 1714 1715 #define __BUILD_SET_C0(name) \ 1716 static inline unsigned int \ 1717 set_c0_##name(unsigned int set) \ 1718 { \ 1719 unsigned int res; \ 1720 unsigned int new; \ 1721 unsigned int omt; \ 1722 unsigned long flags; \ 1723 \ 1724 local_irq_save(flags); \ 1725 omt = __dmt(); \ 1726 res = read_c0_##name(); \ 1727 new = res | set; \ 1728 write_c0_##name(new); \ 1729 __emt(omt); \ 1730 local_irq_restore(flags); \ 1731 \ 1732 return res; \ 1733 } \ 1734 \ 1735 static inline unsigned int \ 1736 clear_c0_##name(unsigned int clear) \ 1737 { \ 1738 unsigned int res; \ 1739 unsigned int new; \ 1740 unsigned int omt; \ 1741 unsigned long flags; \ 1742 \ 1743 local_irq_save(flags); \ 1744 omt = __dmt(); \ 1745 res = read_c0_##name(); \ 1746 new = res & ~clear; \ 1747 write_c0_##name(new); \ 1748 __emt(omt); \ 1749 local_irq_restore(flags); \ 1750 \ 1751 return res; \ 1752 } \ 1753 \ 1754 static inline unsigned int \ 1755 change_c0_##name(unsigned int change, unsigned int newbits) \ 1756 { \ 1757 unsigned int res; \ 1758 unsigned int new; \ 1759 unsigned int omt; \ 1760 unsigned long flags; \ 1761 \ 1762 local_irq_save(flags); \ 1763 \ 1764 omt = __dmt(); \ 1765 res = read_c0_##name(); \ 1766 new = res & ~change; \ 1767 new |= (newbits & change); \ 1768 write_c0_##name(new); \ 1769 __emt(omt); \ 1770 local_irq_restore(flags); \ 1771 \ 1772 return res; \ 1773 } 1774 #endif 1775 1776 __BUILD_SET_C0(status) 1777 __BUILD_SET_C0(cause) 1778 __BUILD_SET_C0(config) 1779 __BUILD_SET_C0(intcontrol) 1780 __BUILD_SET_C0(intctl) 1781 __BUILD_SET_C0(srsmap) 1782 __BUILD_SET_C0(brcm_config_0) 1783 __BUILD_SET_C0(brcm_bus_pll) 1784 __BUILD_SET_C0(brcm_reset) 1785 __BUILD_SET_C0(brcm_cmt_intr) 1786 __BUILD_SET_C0(brcm_cmt_ctrl) 1787 __BUILD_SET_C0(brcm_config) 1788 __BUILD_SET_C0(brcm_mode) 1789 1790 #endif /* !__ASSEMBLY__ */ 1791 1792 #endif /* _ASM_MIPSREGS_H */ 1793