1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 7 * Copyright (C) 2000 Silicon Graphics, Inc. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 12 */ 13 #ifndef _ASM_MIPSREGS_H 14 #define _ASM_MIPSREGS_H 15 16 #include <linux/linkage.h> 17 #include <linux/types.h> 18 #include <asm/hazards.h> 19 #include <asm/war.h> 20 21 /* 22 * The following macros are especially useful for __asm__ 23 * inline assembler. 24 */ 25 #ifndef __STR 26 #define __STR(x) #x 27 #endif 28 #ifndef STR 29 #define STR(x) __STR(x) 30 #endif 31 32 /* 33 * Configure language 34 */ 35 #ifdef __ASSEMBLY__ 36 #define _ULCAST_ 37 #else 38 #define _ULCAST_ (unsigned long) 39 #endif 40 41 /* 42 * Coprocessor 0 register names 43 */ 44 #define CP0_INDEX $0 45 #define CP0_RANDOM $1 46 #define CP0_ENTRYLO0 $2 47 #define CP0_ENTRYLO1 $3 48 #define CP0_CONF $3 49 #define CP0_CONTEXT $4 50 #define CP0_PAGEMASK $5 51 #define CP0_WIRED $6 52 #define CP0_INFO $7 53 #define CP0_BADVADDR $8 54 #define CP0_COUNT $9 55 #define CP0_ENTRYHI $10 56 #define CP0_COMPARE $11 57 #define CP0_STATUS $12 58 #define CP0_CAUSE $13 59 #define CP0_EPC $14 60 #define CP0_PRID $15 61 #define CP0_CONFIG $16 62 #define CP0_LLADDR $17 63 #define CP0_WATCHLO $18 64 #define CP0_WATCHHI $19 65 #define CP0_XCONTEXT $20 66 #define CP0_FRAMEMASK $21 67 #define CP0_DIAGNOSTIC $22 68 #define CP0_DEBUG $23 69 #define CP0_DEPC $24 70 #define CP0_PERFORMANCE $25 71 #define CP0_ECC $26 72 #define CP0_CACHEERR $27 73 #define CP0_TAGLO $28 74 #define CP0_TAGHI $29 75 #define CP0_ERROREPC $30 76 #define CP0_DESAVE $31 77 78 /* 79 * R4640/R4650 cp0 register names. These registers are listed 80 * here only for completeness; without MMU these CPUs are not useable 81 * by Linux. A future ELKS port might take make Linux run on them 82 * though ... 83 */ 84 #define CP0_IBASE $0 85 #define CP0_IBOUND $1 86 #define CP0_DBASE $2 87 #define CP0_DBOUND $3 88 #define CP0_CALG $17 89 #define CP0_IWATCH $18 90 #define CP0_DWATCH $19 91 92 /* 93 * Coprocessor 0 Set 1 register names 94 */ 95 #define CP0_S1_DERRADDR0 $26 96 #define CP0_S1_DERRADDR1 $27 97 #define CP0_S1_INTCONTROL $20 98 99 /* 100 * Coprocessor 0 Set 2 register names 101 */ 102 #define CP0_S2_SRSCTL $12 /* MIPSR2 */ 103 104 /* 105 * Coprocessor 0 Set 3 register names 106 */ 107 #define CP0_S3_SRSMAP $12 /* MIPSR2 */ 108 109 /* 110 * TX39 Series 111 */ 112 #define CP0_TX39_CACHE $7 113 114 /* 115 * Coprocessor 1 (FPU) register names 116 */ 117 #define CP1_REVISION $0 118 #define CP1_STATUS $31 119 120 /* 121 * FPU Status Register Values 122 */ 123 /* 124 * Status Register Values 125 */ 126 127 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ 128 #define FPU_CSR_COND 0x00800000 /* $fcc0 */ 129 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ 130 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ 131 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ 132 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ 133 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ 134 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ 135 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ 136 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 137 138 /* 139 * Bits 18 - 20 of the FPU Status Register will be read as 0, 140 * and should be written as zero. 141 */ 142 #define FPU_CSR_RSVD 0x001c0000 143 144 /* 145 * X the exception cause indicator 146 * E the exception enable 147 * S the sticky/flag bit 148 */ 149 #define FPU_CSR_ALL_X 0x0003f000 150 #define FPU_CSR_UNI_X 0x00020000 151 #define FPU_CSR_INV_X 0x00010000 152 #define FPU_CSR_DIV_X 0x00008000 153 #define FPU_CSR_OVF_X 0x00004000 154 #define FPU_CSR_UDF_X 0x00002000 155 #define FPU_CSR_INE_X 0x00001000 156 157 #define FPU_CSR_ALL_E 0x00000f80 158 #define FPU_CSR_INV_E 0x00000800 159 #define FPU_CSR_DIV_E 0x00000400 160 #define FPU_CSR_OVF_E 0x00000200 161 #define FPU_CSR_UDF_E 0x00000100 162 #define FPU_CSR_INE_E 0x00000080 163 164 #define FPU_CSR_ALL_S 0x0000007c 165 #define FPU_CSR_INV_S 0x00000040 166 #define FPU_CSR_DIV_S 0x00000020 167 #define FPU_CSR_OVF_S 0x00000010 168 #define FPU_CSR_UDF_S 0x00000008 169 #define FPU_CSR_INE_S 0x00000004 170 171 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ 172 #define FPU_CSR_RM 0x00000003 173 #define FPU_CSR_RN 0x0 /* nearest */ 174 #define FPU_CSR_RZ 0x1 /* towards zero */ 175 #define FPU_CSR_RU 0x2 /* towards +Infinity */ 176 #define FPU_CSR_RD 0x3 /* towards -Infinity */ 177 178 179 /* 180 * Values for PageMask register 181 */ 182 #ifdef CONFIG_CPU_VR41XX 183 184 /* Why doesn't stupidity hurt ... */ 185 186 #define PM_1K 0x00000000 187 #define PM_4K 0x00001800 188 #define PM_16K 0x00007800 189 #define PM_64K 0x0001f800 190 #define PM_256K 0x0007f800 191 192 #else 193 194 #define PM_4K 0x00000000 195 #define PM_8K 0x00002000 196 #define PM_16K 0x00006000 197 #define PM_32K 0x0000e000 198 #define PM_64K 0x0001e000 199 #define PM_128K 0x0003e000 200 #define PM_256K 0x0007e000 201 #define PM_512K 0x000fe000 202 #define PM_1M 0x001fe000 203 #define PM_2M 0x003fe000 204 #define PM_4M 0x007fe000 205 #define PM_8M 0x00ffe000 206 #define PM_16M 0x01ffe000 207 #define PM_32M 0x03ffe000 208 #define PM_64M 0x07ffe000 209 #define PM_256M 0x1fffe000 210 #define PM_1G 0x7fffe000 211 212 #endif 213 214 /* 215 * Default page size for a given kernel configuration 216 */ 217 #ifdef CONFIG_PAGE_SIZE_4KB 218 #define PM_DEFAULT_MASK PM_4K 219 #elif defined(CONFIG_PAGE_SIZE_8KB) 220 #define PM_DEFAULT_MASK PM_8K 221 #elif defined(CONFIG_PAGE_SIZE_16KB) 222 #define PM_DEFAULT_MASK PM_16K 223 #elif defined(CONFIG_PAGE_SIZE_32KB) 224 #define PM_DEFAULT_MASK PM_32K 225 #elif defined(CONFIG_PAGE_SIZE_64KB) 226 #define PM_DEFAULT_MASK PM_64K 227 #else 228 #error Bad page size configuration! 229 #endif 230 231 /* 232 * Default huge tlb size for a given kernel configuration 233 */ 234 #ifdef CONFIG_PAGE_SIZE_4KB 235 #define PM_HUGE_MASK PM_1M 236 #elif defined(CONFIG_PAGE_SIZE_8KB) 237 #define PM_HUGE_MASK PM_4M 238 #elif defined(CONFIG_PAGE_SIZE_16KB) 239 #define PM_HUGE_MASK PM_16M 240 #elif defined(CONFIG_PAGE_SIZE_32KB) 241 #define PM_HUGE_MASK PM_64M 242 #elif defined(CONFIG_PAGE_SIZE_64KB) 243 #define PM_HUGE_MASK PM_256M 244 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) 245 #error Bad page size configuration for hugetlbfs! 246 #endif 247 248 /* 249 * Values used for computation of new tlb entries 250 */ 251 #define PL_4K 12 252 #define PL_16K 14 253 #define PL_64K 16 254 #define PL_256K 18 255 #define PL_1M 20 256 #define PL_4M 22 257 #define PL_16M 24 258 #define PL_64M 26 259 #define PL_256M 28 260 261 /* 262 * PageGrain bits 263 */ 264 #define PG_RIE (_ULCAST_(1) << 31) 265 #define PG_XIE (_ULCAST_(1) << 30) 266 #define PG_ELPA (_ULCAST_(1) << 29) 267 #define PG_ESP (_ULCAST_(1) << 28) 268 #define PG_IEC (_ULCAST_(1) << 27) 269 270 /* 271 * R4x00 interrupt enable / cause bits 272 */ 273 #define IE_SW0 (_ULCAST_(1) << 8) 274 #define IE_SW1 (_ULCAST_(1) << 9) 275 #define IE_IRQ0 (_ULCAST_(1) << 10) 276 #define IE_IRQ1 (_ULCAST_(1) << 11) 277 #define IE_IRQ2 (_ULCAST_(1) << 12) 278 #define IE_IRQ3 (_ULCAST_(1) << 13) 279 #define IE_IRQ4 (_ULCAST_(1) << 14) 280 #define IE_IRQ5 (_ULCAST_(1) << 15) 281 282 /* 283 * R4x00 interrupt cause bits 284 */ 285 #define C_SW0 (_ULCAST_(1) << 8) 286 #define C_SW1 (_ULCAST_(1) << 9) 287 #define C_IRQ0 (_ULCAST_(1) << 10) 288 #define C_IRQ1 (_ULCAST_(1) << 11) 289 #define C_IRQ2 (_ULCAST_(1) << 12) 290 #define C_IRQ3 (_ULCAST_(1) << 13) 291 #define C_IRQ4 (_ULCAST_(1) << 14) 292 #define C_IRQ5 (_ULCAST_(1) << 15) 293 294 /* 295 * Bitfields in the R4xx0 cp0 status register 296 */ 297 #define ST0_IE 0x00000001 298 #define ST0_EXL 0x00000002 299 #define ST0_ERL 0x00000004 300 #define ST0_KSU 0x00000018 301 # define KSU_USER 0x00000010 302 # define KSU_SUPERVISOR 0x00000008 303 # define KSU_KERNEL 0x00000000 304 #define ST0_UX 0x00000020 305 #define ST0_SX 0x00000040 306 #define ST0_KX 0x00000080 307 #define ST0_DE 0x00010000 308 #define ST0_CE 0x00020000 309 310 /* 311 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate 312 * cacheops in userspace. This bit exists only on RM7000 and RM9000 313 * processors. 314 */ 315 #define ST0_CO 0x08000000 316 317 /* 318 * Bitfields in the R[23]000 cp0 status register. 319 */ 320 #define ST0_IEC 0x00000001 321 #define ST0_KUC 0x00000002 322 #define ST0_IEP 0x00000004 323 #define ST0_KUP 0x00000008 324 #define ST0_IEO 0x00000010 325 #define ST0_KUO 0x00000020 326 /* bits 6 & 7 are reserved on R[23]000 */ 327 #define ST0_ISC 0x00010000 328 #define ST0_SWC 0x00020000 329 #define ST0_CM 0x00080000 330 331 /* 332 * Bits specific to the R4640/R4650 333 */ 334 #define ST0_UM (_ULCAST_(1) << 4) 335 #define ST0_IL (_ULCAST_(1) << 23) 336 #define ST0_DL (_ULCAST_(1) << 24) 337 338 /* 339 * Enable the MIPS MDMX and DSP ASEs 340 */ 341 #define ST0_MX 0x01000000 342 343 /* 344 * Bitfields in the TX39 family CP0 Configuration Register 3 345 */ 346 #define TX39_CONF_ICS_SHIFT 19 347 #define TX39_CONF_ICS_MASK 0x00380000 348 #define TX39_CONF_ICS_1KB 0x00000000 349 #define TX39_CONF_ICS_2KB 0x00080000 350 #define TX39_CONF_ICS_4KB 0x00100000 351 #define TX39_CONF_ICS_8KB 0x00180000 352 #define TX39_CONF_ICS_16KB 0x00200000 353 354 #define TX39_CONF_DCS_SHIFT 16 355 #define TX39_CONF_DCS_MASK 0x00070000 356 #define TX39_CONF_DCS_1KB 0x00000000 357 #define TX39_CONF_DCS_2KB 0x00010000 358 #define TX39_CONF_DCS_4KB 0x00020000 359 #define TX39_CONF_DCS_8KB 0x00030000 360 #define TX39_CONF_DCS_16KB 0x00040000 361 362 #define TX39_CONF_CWFON 0x00004000 363 #define TX39_CONF_WBON 0x00002000 364 #define TX39_CONF_RF_SHIFT 10 365 #define TX39_CONF_RF_MASK 0x00000c00 366 #define TX39_CONF_DOZE 0x00000200 367 #define TX39_CONF_HALT 0x00000100 368 #define TX39_CONF_LOCK 0x00000080 369 #define TX39_CONF_ICE 0x00000020 370 #define TX39_CONF_DCE 0x00000010 371 #define TX39_CONF_IRSIZE_SHIFT 2 372 #define TX39_CONF_IRSIZE_MASK 0x0000000c 373 #define TX39_CONF_DRSIZE_SHIFT 0 374 #define TX39_CONF_DRSIZE_MASK 0x00000003 375 376 /* 377 * Status register bits available in all MIPS CPUs. 378 */ 379 #define ST0_IM 0x0000ff00 380 #define STATUSB_IP0 8 381 #define STATUSF_IP0 (_ULCAST_(1) << 8) 382 #define STATUSB_IP1 9 383 #define STATUSF_IP1 (_ULCAST_(1) << 9) 384 #define STATUSB_IP2 10 385 #define STATUSF_IP2 (_ULCAST_(1) << 10) 386 #define STATUSB_IP3 11 387 #define STATUSF_IP3 (_ULCAST_(1) << 11) 388 #define STATUSB_IP4 12 389 #define STATUSF_IP4 (_ULCAST_(1) << 12) 390 #define STATUSB_IP5 13 391 #define STATUSF_IP5 (_ULCAST_(1) << 13) 392 #define STATUSB_IP6 14 393 #define STATUSF_IP6 (_ULCAST_(1) << 14) 394 #define STATUSB_IP7 15 395 #define STATUSF_IP7 (_ULCAST_(1) << 15) 396 #define STATUSB_IP8 0 397 #define STATUSF_IP8 (_ULCAST_(1) << 0) 398 #define STATUSB_IP9 1 399 #define STATUSF_IP9 (_ULCAST_(1) << 1) 400 #define STATUSB_IP10 2 401 #define STATUSF_IP10 (_ULCAST_(1) << 2) 402 #define STATUSB_IP11 3 403 #define STATUSF_IP11 (_ULCAST_(1) << 3) 404 #define STATUSB_IP12 4 405 #define STATUSF_IP12 (_ULCAST_(1) << 4) 406 #define STATUSB_IP13 5 407 #define STATUSF_IP13 (_ULCAST_(1) << 5) 408 #define STATUSB_IP14 6 409 #define STATUSF_IP14 (_ULCAST_(1) << 6) 410 #define STATUSB_IP15 7 411 #define STATUSF_IP15 (_ULCAST_(1) << 7) 412 #define ST0_CH 0x00040000 413 #define ST0_NMI 0x00080000 414 #define ST0_SR 0x00100000 415 #define ST0_TS 0x00200000 416 #define ST0_BEV 0x00400000 417 #define ST0_RE 0x02000000 418 #define ST0_FR 0x04000000 419 #define ST0_CU 0xf0000000 420 #define ST0_CU0 0x10000000 421 #define ST0_CU1 0x20000000 422 #define ST0_CU2 0x40000000 423 #define ST0_CU3 0x80000000 424 #define ST0_XX 0x80000000 /* MIPS IV naming */ 425 426 /* 427 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) 428 * 429 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 430 */ 431 #define INTCTLB_IPFDC 23 432 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC) 433 #define INTCTLB_IPPCI 26 434 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) 435 #define INTCTLB_IPTI 29 436 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) 437 438 /* 439 * Bitfields and bit numbers in the coprocessor 0 cause register. 440 * 441 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 442 */ 443 #define CAUSEB_EXCCODE 2 444 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 445 #define CAUSEB_IP 8 446 #define CAUSEF_IP (_ULCAST_(255) << 8) 447 #define CAUSEB_IP0 8 448 #define CAUSEF_IP0 (_ULCAST_(1) << 8) 449 #define CAUSEB_IP1 9 450 #define CAUSEF_IP1 (_ULCAST_(1) << 9) 451 #define CAUSEB_IP2 10 452 #define CAUSEF_IP2 (_ULCAST_(1) << 10) 453 #define CAUSEB_IP3 11 454 #define CAUSEF_IP3 (_ULCAST_(1) << 11) 455 #define CAUSEB_IP4 12 456 #define CAUSEF_IP4 (_ULCAST_(1) << 12) 457 #define CAUSEB_IP5 13 458 #define CAUSEF_IP5 (_ULCAST_(1) << 13) 459 #define CAUSEB_IP6 14 460 #define CAUSEF_IP6 (_ULCAST_(1) << 14) 461 #define CAUSEB_IP7 15 462 #define CAUSEF_IP7 (_ULCAST_(1) << 15) 463 #define CAUSEB_FDCI 21 464 #define CAUSEF_FDCI (_ULCAST_(1) << 21) 465 #define CAUSEB_IV 23 466 #define CAUSEF_IV (_ULCAST_(1) << 23) 467 #define CAUSEB_PCI 26 468 #define CAUSEF_PCI (_ULCAST_(1) << 26) 469 #define CAUSEB_CE 28 470 #define CAUSEF_CE (_ULCAST_(3) << 28) 471 #define CAUSEB_TI 30 472 #define CAUSEF_TI (_ULCAST_(1) << 30) 473 #define CAUSEB_BD 31 474 #define CAUSEF_BD (_ULCAST_(1) << 31) 475 476 /* 477 * Bits in the coprocessor 0 config register. 478 */ 479 /* Generic bits. */ 480 #define CONF_CM_CACHABLE_NO_WA 0 481 #define CONF_CM_CACHABLE_WA 1 482 #define CONF_CM_UNCACHED 2 483 #define CONF_CM_CACHABLE_NONCOHERENT 3 484 #define CONF_CM_CACHABLE_CE 4 485 #define CONF_CM_CACHABLE_COW 5 486 #define CONF_CM_CACHABLE_CUW 6 487 #define CONF_CM_CACHABLE_ACCELERATED 7 488 #define CONF_CM_CMASK 7 489 #define CONF_BE (_ULCAST_(1) << 15) 490 491 /* Bits common to various processors. */ 492 #define CONF_CU (_ULCAST_(1) << 3) 493 #define CONF_DB (_ULCAST_(1) << 4) 494 #define CONF_IB (_ULCAST_(1) << 5) 495 #define CONF_DC (_ULCAST_(7) << 6) 496 #define CONF_IC (_ULCAST_(7) << 9) 497 #define CONF_EB (_ULCAST_(1) << 13) 498 #define CONF_EM (_ULCAST_(1) << 14) 499 #define CONF_SM (_ULCAST_(1) << 16) 500 #define CONF_SC (_ULCAST_(1) << 17) 501 #define CONF_EW (_ULCAST_(3) << 18) 502 #define CONF_EP (_ULCAST_(15)<< 24) 503 #define CONF_EC (_ULCAST_(7) << 28) 504 #define CONF_CM (_ULCAST_(1) << 31) 505 506 /* Bits specific to the R4xx0. */ 507 #define R4K_CONF_SW (_ULCAST_(1) << 20) 508 #define R4K_CONF_SS (_ULCAST_(1) << 21) 509 #define R4K_CONF_SB (_ULCAST_(3) << 22) 510 511 /* Bits specific to the R5000. */ 512 #define R5K_CONF_SE (_ULCAST_(1) << 12) 513 #define R5K_CONF_SS (_ULCAST_(3) << 20) 514 515 /* Bits specific to the RM7000. */ 516 #define RM7K_CONF_SE (_ULCAST_(1) << 3) 517 #define RM7K_CONF_TE (_ULCAST_(1) << 12) 518 #define RM7K_CONF_CLK (_ULCAST_(1) << 16) 519 #define RM7K_CONF_TC (_ULCAST_(1) << 17) 520 #define RM7K_CONF_SI (_ULCAST_(3) << 20) 521 #define RM7K_CONF_SC (_ULCAST_(1) << 31) 522 523 /* Bits specific to the R10000. */ 524 #define R10K_CONF_DN (_ULCAST_(3) << 3) 525 #define R10K_CONF_CT (_ULCAST_(1) << 5) 526 #define R10K_CONF_PE (_ULCAST_(1) << 6) 527 #define R10K_CONF_PM (_ULCAST_(3) << 7) 528 #define R10K_CONF_EC (_ULCAST_(15)<< 9) 529 #define R10K_CONF_SB (_ULCAST_(1) << 13) 530 #define R10K_CONF_SK (_ULCAST_(1) << 14) 531 #define R10K_CONF_SS (_ULCAST_(7) << 16) 532 #define R10K_CONF_SC (_ULCAST_(7) << 19) 533 #define R10K_CONF_DC (_ULCAST_(7) << 26) 534 #define R10K_CONF_IC (_ULCAST_(7) << 29) 535 536 /* Bits specific to the VR41xx. */ 537 #define VR41_CONF_CS (_ULCAST_(1) << 12) 538 #define VR41_CONF_P4K (_ULCAST_(1) << 13) 539 #define VR41_CONF_BP (_ULCAST_(1) << 16) 540 #define VR41_CONF_M16 (_ULCAST_(1) << 20) 541 #define VR41_CONF_AD (_ULCAST_(1) << 23) 542 543 /* Bits specific to the R30xx. */ 544 #define R30XX_CONF_FDM (_ULCAST_(1) << 19) 545 #define R30XX_CONF_REV (_ULCAST_(1) << 22) 546 #define R30XX_CONF_AC (_ULCAST_(1) << 23) 547 #define R30XX_CONF_RF (_ULCAST_(1) << 24) 548 #define R30XX_CONF_HALT (_ULCAST_(1) << 25) 549 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 550 #define R30XX_CONF_DBR (_ULCAST_(1) << 29) 551 #define R30XX_CONF_SB (_ULCAST_(1) << 30) 552 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 553 554 /* Bits specific to the TX49. */ 555 #define TX49_CONF_DC (_ULCAST_(1) << 16) 556 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 557 #define TX49_CONF_HALT (_ULCAST_(1) << 18) 558 #define TX49_CONF_CWFON (_ULCAST_(1) << 27) 559 560 /* Bits specific to the MIPS32/64 PRA. */ 561 #define MIPS_CONF_MT (_ULCAST_(7) << 7) 562 #define MIPS_CONF_AR (_ULCAST_(7) << 10) 563 #define MIPS_CONF_AT (_ULCAST_(3) << 13) 564 #define MIPS_CONF_M (_ULCAST_(1) << 31) 565 566 /* 567 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 568 */ 569 #define MIPS_CONF1_FP (_ULCAST_(1) << 0) 570 #define MIPS_CONF1_EP (_ULCAST_(1) << 1) 571 #define MIPS_CONF1_CA (_ULCAST_(1) << 2) 572 #define MIPS_CONF1_WR (_ULCAST_(1) << 3) 573 #define MIPS_CONF1_PC (_ULCAST_(1) << 4) 574 #define MIPS_CONF1_MD (_ULCAST_(1) << 5) 575 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 576 #define MIPS_CONF1_DA_SHF 7 577 #define MIPS_CONF1_DA_SZ 3 578 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) 579 #define MIPS_CONF1_DL_SHF 10 580 #define MIPS_CONF1_DL_SZ 3 581 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) 582 #define MIPS_CONF1_DS_SHF 13 583 #define MIPS_CONF1_DS_SZ 3 584 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) 585 #define MIPS_CONF1_IA_SHF 16 586 #define MIPS_CONF1_IA_SZ 3 587 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) 588 #define MIPS_CONF1_IL_SHF 19 589 #define MIPS_CONF1_IL_SZ 3 590 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) 591 #define MIPS_CONF1_IS_SHF 22 592 #define MIPS_CONF1_IS_SZ 3 593 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) 594 #define MIPS_CONF1_TLBS_SHIFT (25) 595 #define MIPS_CONF1_TLBS_SIZE (6) 596 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT) 597 598 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 599 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 600 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 601 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 602 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 603 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 604 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 605 #define MIPS_CONF2_TU (_ULCAST_(7) << 28) 606 607 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 608 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 609 #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 610 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3) 611 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 612 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 613 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 614 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 615 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8) 616 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9) 617 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 618 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 619 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 620 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 621 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 622 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) 623 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17) 624 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18) 625 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21) 626 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 627 #define MIPS_CONF3_PW (_ULCAST_(1) << 24) 628 #define MIPS_CONF3_SC (_ULCAST_(1) << 25) 629 #define MIPS_CONF3_BI (_ULCAST_(1) << 26) 630 #define MIPS_CONF3_BP (_ULCAST_(1) << 27) 631 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28) 632 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29) 633 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30) 634 635 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0) 636 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 637 #define MIPS_CONF4_FTLBSETS_SHIFT (0) 638 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT) 639 #define MIPS_CONF4_FTLBWAYS_SHIFT (4) 640 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT) 641 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8) 642 /* bits 10:8 in FTLB-only configurations */ 643 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) 644 /* bits 12:8 in VTLB-FTLB only configurations */ 645 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) 646 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 647 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 648 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14) 649 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14) 650 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16) 651 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24) 652 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT) 653 #define MIPS_CONF4_AE (_ULCAST_(1) << 28) 654 #define MIPS_CONF4_IE (_ULCAST_(3) << 29) 655 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29) 656 657 #define MIPS_CONF5_NF (_ULCAST_(1) << 0) 658 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2) 659 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3) 660 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4) 661 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5) 662 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8) 663 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9) 664 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) 665 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28) 666 #define MIPS_CONF5_CV (_ULCAST_(1) << 29) 667 #define MIPS_CONF5_K (_ULCAST_(1) << 30) 668 669 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 670 /* proAptiv FTLB on/off bit */ 671 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) 672 /* FTLB probability bits */ 673 #define MIPS_CONF6_FTLBP_SHIFT (16) 674 675 #define MIPS_CONF7_WII (_ULCAST_(1) << 31) 676 677 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 678 679 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10) 680 #define MIPS_CONF7_AR (_ULCAST_(1) << 16) 681 682 /* MAAR bit definitions */ 683 #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12) 684 #define MIPS_MAAR_ADDR_SHIFT 12 685 #define MIPS_MAAR_S (_ULCAST_(1) << 1) 686 #define MIPS_MAAR_V (_ULCAST_(1) << 0) 687 688 /* EntryHI bit definition */ 689 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) 690 691 /* CMGCRBase bit definitions */ 692 #define MIPS_CMGCRB_BASE 11 693 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) 694 695 /* 696 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 697 */ 698 #define MIPS_FPIR_S (_ULCAST_(1) << 16) 699 #define MIPS_FPIR_D (_ULCAST_(1) << 17) 700 #define MIPS_FPIR_PS (_ULCAST_(1) << 18) 701 #define MIPS_FPIR_3D (_ULCAST_(1) << 19) 702 #define MIPS_FPIR_W (_ULCAST_(1) << 20) 703 #define MIPS_FPIR_L (_ULCAST_(1) << 21) 704 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 705 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29) 706 707 /* 708 * Bits in the MIPS32 Memory Segmentation registers. 709 */ 710 #define MIPS_SEGCFG_PA_SHIFT 9 711 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT) 712 #define MIPS_SEGCFG_AM_SHIFT 4 713 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT) 714 #define MIPS_SEGCFG_EU_SHIFT 3 715 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT) 716 #define MIPS_SEGCFG_C_SHIFT 0 717 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT) 718 719 #define MIPS_SEGCFG_UUSK _ULCAST_(7) 720 #define MIPS_SEGCFG_USK _ULCAST_(5) 721 #define MIPS_SEGCFG_MUSUK _ULCAST_(4) 722 #define MIPS_SEGCFG_MUSK _ULCAST_(3) 723 #define MIPS_SEGCFG_MSK _ULCAST_(2) 724 #define MIPS_SEGCFG_MK _ULCAST_(1) 725 #define MIPS_SEGCFG_UK _ULCAST_(0) 726 727 #define MIPS_PWFIELD_GDI_SHIFT 24 728 #define MIPS_PWFIELD_GDI_MASK 0x3f000000 729 #define MIPS_PWFIELD_UDI_SHIFT 18 730 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000 731 #define MIPS_PWFIELD_MDI_SHIFT 12 732 #define MIPS_PWFIELD_MDI_MASK 0x0003f000 733 #define MIPS_PWFIELD_PTI_SHIFT 6 734 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0 735 #define MIPS_PWFIELD_PTEI_SHIFT 0 736 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f 737 738 #define MIPS_PWSIZE_GDW_SHIFT 24 739 #define MIPS_PWSIZE_GDW_MASK 0x3f000000 740 #define MIPS_PWSIZE_UDW_SHIFT 18 741 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000 742 #define MIPS_PWSIZE_MDW_SHIFT 12 743 #define MIPS_PWSIZE_MDW_MASK 0x0003f000 744 #define MIPS_PWSIZE_PTW_SHIFT 6 745 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0 746 #define MIPS_PWSIZE_PTEW_SHIFT 0 747 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f 748 749 #define MIPS_PWCTL_PWEN_SHIFT 31 750 #define MIPS_PWCTL_PWEN_MASK 0x80000000 751 #define MIPS_PWCTL_DPH_SHIFT 7 752 #define MIPS_PWCTL_DPH_MASK 0x00000080 753 #define MIPS_PWCTL_HUGEPG_SHIFT 6 754 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060 755 #define MIPS_PWCTL_PSN_SHIFT 0 756 #define MIPS_PWCTL_PSN_MASK 0x0000003f 757 758 /* CDMMBase register bit definitions */ 759 #define MIPS_CDMMBASE_SIZE_SHIFT 0 760 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT) 761 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9) 762 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10) 763 #define MIPS_CDMMBASE_ADDR_SHIFT 11 764 #define MIPS_CDMMBASE_ADDR_START 15 765 766 #ifndef __ASSEMBLY__ 767 768 /* 769 * Macros for handling the ISA mode bit for MIPS16 and microMIPS. 770 */ 771 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \ 772 defined(CONFIG_SYS_SUPPORTS_MICROMIPS) 773 #define get_isa16_mode(x) ((x) & 0x1) 774 #define msk_isa16_mode(x) ((x) & ~0x1) 775 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0) 776 #else 777 #define get_isa16_mode(x) 0 778 #define msk_isa16_mode(x) (x) 779 #define set_isa16_mode(x) do { } while(0) 780 #endif 781 782 /* 783 * microMIPS instructions can be 16-bit or 32-bit in length. This 784 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. 785 */ 786 static inline int mm_insn_16bit(u16 insn) 787 { 788 u16 opcode = (insn >> 10) & 0x7; 789 790 return (opcode >= 1 && opcode <= 3) ? 1 : 0; 791 } 792 793 /* 794 * TLB Invalidate Flush 795 */ 796 static inline void tlbinvf(void) 797 { 798 __asm__ __volatile__( 799 ".set push\n\t" 800 ".set noreorder\n\t" 801 ".word 0x42000004\n\t" /* tlbinvf */ 802 ".set pop"); 803 } 804 805 806 /* 807 * Functions to access the R10000 performance counters. These are basically 808 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 809 * performance counter number encoded into bits 1 ... 5 of the instruction. 810 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware 811 * disassembler these will look like an access to sel 0 or 1. 812 */ 813 #define read_r10k_perf_cntr(counter) \ 814 ({ \ 815 unsigned int __res; \ 816 __asm__ __volatile__( \ 817 "mfpc\t%0, %1" \ 818 : "=r" (__res) \ 819 : "i" (counter)); \ 820 \ 821 __res; \ 822 }) 823 824 #define write_r10k_perf_cntr(counter,val) \ 825 do { \ 826 __asm__ __volatile__( \ 827 "mtpc\t%0, %1" \ 828 : \ 829 : "r" (val), "i" (counter)); \ 830 } while (0) 831 832 #define read_r10k_perf_event(counter) \ 833 ({ \ 834 unsigned int __res; \ 835 __asm__ __volatile__( \ 836 "mfps\t%0, %1" \ 837 : "=r" (__res) \ 838 : "i" (counter)); \ 839 \ 840 __res; \ 841 }) 842 843 #define write_r10k_perf_cntl(counter,val) \ 844 do { \ 845 __asm__ __volatile__( \ 846 "mtps\t%0, %1" \ 847 : \ 848 : "r" (val), "i" (counter)); \ 849 } while (0) 850 851 852 /* 853 * Macros to access the system control coprocessor 854 */ 855 856 #define __read_32bit_c0_register(source, sel) \ 857 ({ int __res; \ 858 if (sel == 0) \ 859 __asm__ __volatile__( \ 860 "mfc0\t%0, " #source "\n\t" \ 861 : "=r" (__res)); \ 862 else \ 863 __asm__ __volatile__( \ 864 ".set\tmips32\n\t" \ 865 "mfc0\t%0, " #source ", " #sel "\n\t" \ 866 ".set\tmips0\n\t" \ 867 : "=r" (__res)); \ 868 __res; \ 869 }) 870 871 #define __read_64bit_c0_register(source, sel) \ 872 ({ unsigned long long __res; \ 873 if (sizeof(unsigned long) == 4) \ 874 __res = __read_64bit_c0_split(source, sel); \ 875 else if (sel == 0) \ 876 __asm__ __volatile__( \ 877 ".set\tmips3\n\t" \ 878 "dmfc0\t%0, " #source "\n\t" \ 879 ".set\tmips0" \ 880 : "=r" (__res)); \ 881 else \ 882 __asm__ __volatile__( \ 883 ".set\tmips64\n\t" \ 884 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 885 ".set\tmips0" \ 886 : "=r" (__res)); \ 887 __res; \ 888 }) 889 890 #define __write_32bit_c0_register(register, sel, value) \ 891 do { \ 892 if (sel == 0) \ 893 __asm__ __volatile__( \ 894 "mtc0\t%z0, " #register "\n\t" \ 895 : : "Jr" ((unsigned int)(value))); \ 896 else \ 897 __asm__ __volatile__( \ 898 ".set\tmips32\n\t" \ 899 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 900 ".set\tmips0" \ 901 : : "Jr" ((unsigned int)(value))); \ 902 } while (0) 903 904 #define __write_64bit_c0_register(register, sel, value) \ 905 do { \ 906 if (sizeof(unsigned long) == 4) \ 907 __write_64bit_c0_split(register, sel, value); \ 908 else if (sel == 0) \ 909 __asm__ __volatile__( \ 910 ".set\tmips3\n\t" \ 911 "dmtc0\t%z0, " #register "\n\t" \ 912 ".set\tmips0" \ 913 : : "Jr" (value)); \ 914 else \ 915 __asm__ __volatile__( \ 916 ".set\tmips64\n\t" \ 917 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 918 ".set\tmips0" \ 919 : : "Jr" (value)); \ 920 } while (0) 921 922 #define __read_ulong_c0_register(reg, sel) \ 923 ((sizeof(unsigned long) == 4) ? \ 924 (unsigned long) __read_32bit_c0_register(reg, sel) : \ 925 (unsigned long) __read_64bit_c0_register(reg, sel)) 926 927 #define __write_ulong_c0_register(reg, sel, val) \ 928 do { \ 929 if (sizeof(unsigned long) == 4) \ 930 __write_32bit_c0_register(reg, sel, val); \ 931 else \ 932 __write_64bit_c0_register(reg, sel, val); \ 933 } while (0) 934 935 /* 936 * On RM7000/RM9000 these are uses to access cop0 set 1 registers 937 */ 938 #define __read_32bit_c0_ctrl_register(source) \ 939 ({ int __res; \ 940 __asm__ __volatile__( \ 941 "cfc0\t%0, " #source "\n\t" \ 942 : "=r" (__res)); \ 943 __res; \ 944 }) 945 946 #define __write_32bit_c0_ctrl_register(register, value) \ 947 do { \ 948 __asm__ __volatile__( \ 949 "ctc0\t%z0, " #register "\n\t" \ 950 : : "Jr" ((unsigned int)(value))); \ 951 } while (0) 952 953 /* 954 * These versions are only needed for systems with more than 38 bits of 955 * physical address space running the 32-bit kernel. That's none atm :-) 956 */ 957 #define __read_64bit_c0_split(source, sel) \ 958 ({ \ 959 unsigned long long __val; \ 960 unsigned long __flags; \ 961 \ 962 local_irq_save(__flags); \ 963 if (sel == 0) \ 964 __asm__ __volatile__( \ 965 ".set\tmips64\n\t" \ 966 "dmfc0\t%M0, " #source "\n\t" \ 967 "dsll\t%L0, %M0, 32\n\t" \ 968 "dsra\t%M0, %M0, 32\n\t" \ 969 "dsra\t%L0, %L0, 32\n\t" \ 970 ".set\tmips0" \ 971 : "=r" (__val)); \ 972 else \ 973 __asm__ __volatile__( \ 974 ".set\tmips64\n\t" \ 975 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 976 "dsll\t%L0, %M0, 32\n\t" \ 977 "dsra\t%M0, %M0, 32\n\t" \ 978 "dsra\t%L0, %L0, 32\n\t" \ 979 ".set\tmips0" \ 980 : "=r" (__val)); \ 981 local_irq_restore(__flags); \ 982 \ 983 __val; \ 984 }) 985 986 #define __write_64bit_c0_split(source, sel, val) \ 987 do { \ 988 unsigned long __flags; \ 989 \ 990 local_irq_save(__flags); \ 991 if (sel == 0) \ 992 __asm__ __volatile__( \ 993 ".set\tmips64\n\t" \ 994 "dsll\t%L0, %L0, 32\n\t" \ 995 "dsrl\t%L0, %L0, 32\n\t" \ 996 "dsll\t%M0, %M0, 32\n\t" \ 997 "or\t%L0, %L0, %M0\n\t" \ 998 "dmtc0\t%L0, " #source "\n\t" \ 999 ".set\tmips0" \ 1000 : : "r" (val)); \ 1001 else \ 1002 __asm__ __volatile__( \ 1003 ".set\tmips64\n\t" \ 1004 "dsll\t%L0, %L0, 32\n\t" \ 1005 "dsrl\t%L0, %L0, 32\n\t" \ 1006 "dsll\t%M0, %M0, 32\n\t" \ 1007 "or\t%L0, %L0, %M0\n\t" \ 1008 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 1009 ".set\tmips0" \ 1010 : : "r" (val)); \ 1011 local_irq_restore(__flags); \ 1012 } while (0) 1013 1014 #define __readx_32bit_c0_register(source) \ 1015 ({ \ 1016 unsigned int __res; \ 1017 \ 1018 __asm__ __volatile__( \ 1019 " .set push \n" \ 1020 " .set noat \n" \ 1021 " .set mips32r2 \n" \ 1022 " .insn \n" \ 1023 " # mfhc0 $1, %1 \n" \ 1024 " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \ 1025 " move %0, $1 \n" \ 1026 " .set pop \n" \ 1027 : "=r" (__res) \ 1028 : "i" (source)); \ 1029 __res; \ 1030 }) 1031 1032 #define __writex_32bit_c0_register(register, value) \ 1033 do { \ 1034 __asm__ __volatile__( \ 1035 " .set push \n" \ 1036 " .set noat \n" \ 1037 " .set mips32r2 \n" \ 1038 " move $1, %0 \n" \ 1039 " # mthc0 $1, %1 \n" \ 1040 " .insn \n" \ 1041 " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \ 1042 " .set pop \n" \ 1043 : \ 1044 : "r" (value), "i" (register)); \ 1045 } while (0) 1046 1047 #define read_c0_index() __read_32bit_c0_register($0, 0) 1048 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 1049 1050 #define read_c0_random() __read_32bit_c0_register($1, 0) 1051 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 1052 1053 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 1054 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 1055 1056 #define readx_c0_entrylo0() __readx_32bit_c0_register(2) 1057 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val) 1058 1059 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 1060 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 1061 1062 #define readx_c0_entrylo1() __readx_32bit_c0_register(3) 1063 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val) 1064 1065 #define read_c0_conf() __read_32bit_c0_register($3, 0) 1066 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 1067 1068 #define read_c0_context() __read_ulong_c0_register($4, 0) 1069 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 1070 1071 #define read_c0_userlocal() __read_ulong_c0_register($4, 2) 1072 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 1073 1074 #define read_c0_pagemask() __read_32bit_c0_register($5, 0) 1075 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 1076 1077 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1) 1078 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) 1079 1080 #define read_c0_wired() __read_32bit_c0_register($6, 0) 1081 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 1082 1083 #define read_c0_info() __read_32bit_c0_register($7, 0) 1084 1085 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 1086 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 1087 1088 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 1089 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) 1090 1091 #define read_c0_count() __read_32bit_c0_register($9, 0) 1092 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 1093 1094 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ 1095 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 1096 1097 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ 1098 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 1099 1100 #define read_c0_entryhi() __read_ulong_c0_register($10, 0) 1101 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 1102 1103 #define read_c0_compare() __read_32bit_c0_register($11, 0) 1104 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 1105 1106 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ 1107 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 1108 1109 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ 1110 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 1111 1112 #define read_c0_status() __read_32bit_c0_register($12, 0) 1113 1114 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 1115 1116 #define read_c0_cause() __read_32bit_c0_register($13, 0) 1117 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 1118 1119 #define read_c0_epc() __read_ulong_c0_register($14, 0) 1120 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 1121 1122 #define read_c0_prid() __read_32bit_c0_register($15, 0) 1123 1124 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3) 1125 1126 #define read_c0_config() __read_32bit_c0_register($16, 0) 1127 #define read_c0_config1() __read_32bit_c0_register($16, 1) 1128 #define read_c0_config2() __read_32bit_c0_register($16, 2) 1129 #define read_c0_config3() __read_32bit_c0_register($16, 3) 1130 #define read_c0_config4() __read_32bit_c0_register($16, 4) 1131 #define read_c0_config5() __read_32bit_c0_register($16, 5) 1132 #define read_c0_config6() __read_32bit_c0_register($16, 6) 1133 #define read_c0_config7() __read_32bit_c0_register($16, 7) 1134 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 1135 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 1136 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 1137 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 1138 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) 1139 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) 1140 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 1141 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 1142 1143 #define read_c0_lladdr() __read_ulong_c0_register($17, 0) 1144 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val) 1145 #define read_c0_maar() __read_ulong_c0_register($17, 1) 1146 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val) 1147 #define read_c0_maari() __read_32bit_c0_register($17, 2) 1148 #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val) 1149 1150 /* 1151 * The WatchLo register. There may be up to 8 of them. 1152 */ 1153 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 1154 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 1155 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 1156 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 1157 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 1158 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 1159 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 1160 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 1161 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 1162 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 1163 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 1164 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 1165 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 1166 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 1167 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 1168 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 1169 1170 /* 1171 * The WatchHi register. There may be up to 8 of them. 1172 */ 1173 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 1174 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 1175 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 1176 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 1177 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 1178 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 1179 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 1180 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 1181 1182 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 1183 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 1184 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 1185 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 1186 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 1187 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 1188 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 1189 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 1190 1191 #define read_c0_xcontext() __read_ulong_c0_register($20, 0) 1192 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 1193 1194 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) 1195 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 1196 1197 #define read_c0_framemask() __read_32bit_c0_register($21, 0) 1198 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 1199 1200 #define read_c0_diag() __read_32bit_c0_register($22, 0) 1201 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 1202 1203 #define read_c0_diag1() __read_32bit_c0_register($22, 1) 1204 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) 1205 1206 #define read_c0_diag2() __read_32bit_c0_register($22, 2) 1207 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) 1208 1209 #define read_c0_diag3() __read_32bit_c0_register($22, 3) 1210 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) 1211 1212 #define read_c0_diag4() __read_32bit_c0_register($22, 4) 1213 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) 1214 1215 #define read_c0_diag5() __read_32bit_c0_register($22, 5) 1216 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) 1217 1218 #define read_c0_debug() __read_32bit_c0_register($23, 0) 1219 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 1220 1221 #define read_c0_depc() __read_ulong_c0_register($24, 0) 1222 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 1223 1224 /* 1225 * MIPS32 / MIPS64 performance counters 1226 */ 1227 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 1228 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 1229 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 1230 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 1231 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) 1232 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) 1233 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 1234 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 1235 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 1236 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 1237 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) 1238 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) 1239 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 1240 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 1241 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 1242 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 1243 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) 1244 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) 1245 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 1246 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 1247 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 1248 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 1249 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) 1250 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) 1251 1252 #define read_c0_ecc() __read_32bit_c0_register($26, 0) 1253 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 1254 1255 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 1256 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 1257 1258 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 1259 1260 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 1261 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 1262 1263 #define read_c0_taglo() __read_32bit_c0_register($28, 0) 1264 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 1265 1266 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) 1267 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) 1268 1269 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3) 1270 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) 1271 1272 #define read_c0_staglo() __read_32bit_c0_register($28, 4) 1273 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) 1274 1275 #define read_c0_taghi() __read_32bit_c0_register($29, 0) 1276 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 1277 1278 #define read_c0_errorepc() __read_ulong_c0_register($30, 0) 1279 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 1280 1281 /* MIPSR2 */ 1282 #define read_c0_hwrena() __read_32bit_c0_register($7, 0) 1283 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 1284 1285 #define read_c0_intctl() __read_32bit_c0_register($12, 1) 1286 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) 1287 1288 #define read_c0_srsctl() __read_32bit_c0_register($12, 2) 1289 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) 1290 1291 #define read_c0_srsmap() __read_32bit_c0_register($12, 3) 1292 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 1293 1294 #define read_c0_ebase() __read_32bit_c0_register($15, 1) 1295 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1296 1297 #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2) 1298 #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val) 1299 1300 /* MIPSR3 */ 1301 #define read_c0_segctl0() __read_32bit_c0_register($5, 2) 1302 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val) 1303 1304 #define read_c0_segctl1() __read_32bit_c0_register($5, 3) 1305 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val) 1306 1307 #define read_c0_segctl2() __read_32bit_c0_register($5, 4) 1308 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val) 1309 1310 /* Hardware Page Table Walker */ 1311 #define read_c0_pwbase() __read_ulong_c0_register($5, 5) 1312 #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val) 1313 1314 #define read_c0_pwfield() __read_ulong_c0_register($5, 6) 1315 #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val) 1316 1317 #define read_c0_pwsize() __read_ulong_c0_register($5, 7) 1318 #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val) 1319 1320 #define read_c0_pwctl() __read_32bit_c0_register($6, 6) 1321 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val) 1322 1323 /* Cavium OCTEON (cnMIPS) */ 1324 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1325 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) 1326 1327 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) 1328 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) 1329 1330 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) 1331 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) 1332 /* 1333 * The cacheerr registers are not standardized. On OCTEON, they are 1334 * 64 bits wide. 1335 */ 1336 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) 1337 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) 1338 1339 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) 1340 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) 1341 1342 /* BMIPS3300 */ 1343 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0) 1344 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) 1345 1346 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4) 1347 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) 1348 1349 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) 1350 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) 1351 1352 /* BMIPS43xx */ 1353 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) 1354 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) 1355 1356 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2) 1357 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) 1358 1359 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3) 1360 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) 1361 1362 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5) 1363 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) 1364 1365 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6) 1366 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) 1367 1368 /* BMIPS5000 */ 1369 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0) 1370 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) 1371 1372 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1) 1373 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) 1374 1375 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2) 1376 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) 1377 1378 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3) 1379 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) 1380 1381 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4) 1382 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) 1383 1384 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7) 1385 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) 1386 1387 /* 1388 * Macros to access the floating point coprocessor control registers 1389 */ 1390 #define _read_32bit_cp1_register(source, gas_hardfloat) \ 1391 ({ \ 1392 int __res; \ 1393 \ 1394 __asm__ __volatile__( \ 1395 " .set push \n" \ 1396 " .set reorder \n" \ 1397 " # gas fails to assemble cfc1 for some archs, \n" \ 1398 " # like Octeon. \n" \ 1399 " .set mips1 \n" \ 1400 " "STR(gas_hardfloat)" \n" \ 1401 " cfc1 %0,"STR(source)" \n" \ 1402 " .set pop \n" \ 1403 : "=r" (__res)); \ 1404 __res; \ 1405 }) 1406 1407 #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \ 1408 do { \ 1409 __asm__ __volatile__( \ 1410 " .set push \n" \ 1411 " .set reorder \n" \ 1412 " "STR(gas_hardfloat)" \n" \ 1413 " ctc1 %0,"STR(dest)" \n" \ 1414 " .set pop \n" \ 1415 : : "r" (val)); \ 1416 } while (0) 1417 1418 #ifdef GAS_HAS_SET_HARDFLOAT 1419 #define read_32bit_cp1_register(source) \ 1420 _read_32bit_cp1_register(source, .set hardfloat) 1421 #define write_32bit_cp1_register(dest, val) \ 1422 _write_32bit_cp1_register(dest, val, .set hardfloat) 1423 #else 1424 #define read_32bit_cp1_register(source) \ 1425 _read_32bit_cp1_register(source, ) 1426 #define write_32bit_cp1_register(dest, val) \ 1427 _write_32bit_cp1_register(dest, val, ) 1428 #endif 1429 1430 #ifdef HAVE_AS_DSP 1431 #define rddsp(mask) \ 1432 ({ \ 1433 unsigned int __dspctl; \ 1434 \ 1435 __asm__ __volatile__( \ 1436 " .set push \n" \ 1437 " .set dsp \n" \ 1438 " rddsp %0, %x1 \n" \ 1439 " .set pop \n" \ 1440 : "=r" (__dspctl) \ 1441 : "i" (mask)); \ 1442 __dspctl; \ 1443 }) 1444 1445 #define wrdsp(val, mask) \ 1446 do { \ 1447 __asm__ __volatile__( \ 1448 " .set push \n" \ 1449 " .set dsp \n" \ 1450 " wrdsp %0, %x1 \n" \ 1451 " .set pop \n" \ 1452 : \ 1453 : "r" (val), "i" (mask)); \ 1454 } while (0) 1455 1456 #define mflo0() \ 1457 ({ \ 1458 long mflo0; \ 1459 __asm__( \ 1460 " .set push \n" \ 1461 " .set dsp \n" \ 1462 " mflo %0, $ac0 \n" \ 1463 " .set pop \n" \ 1464 : "=r" (mflo0)); \ 1465 mflo0; \ 1466 }) 1467 1468 #define mflo1() \ 1469 ({ \ 1470 long mflo1; \ 1471 __asm__( \ 1472 " .set push \n" \ 1473 " .set dsp \n" \ 1474 " mflo %0, $ac1 \n" \ 1475 " .set pop \n" \ 1476 : "=r" (mflo1)); \ 1477 mflo1; \ 1478 }) 1479 1480 #define mflo2() \ 1481 ({ \ 1482 long mflo2; \ 1483 __asm__( \ 1484 " .set push \n" \ 1485 " .set dsp \n" \ 1486 " mflo %0, $ac2 \n" \ 1487 " .set pop \n" \ 1488 : "=r" (mflo2)); \ 1489 mflo2; \ 1490 }) 1491 1492 #define mflo3() \ 1493 ({ \ 1494 long mflo3; \ 1495 __asm__( \ 1496 " .set push \n" \ 1497 " .set dsp \n" \ 1498 " mflo %0, $ac3 \n" \ 1499 " .set pop \n" \ 1500 : "=r" (mflo3)); \ 1501 mflo3; \ 1502 }) 1503 1504 #define mfhi0() \ 1505 ({ \ 1506 long mfhi0; \ 1507 __asm__( \ 1508 " .set push \n" \ 1509 " .set dsp \n" \ 1510 " mfhi %0, $ac0 \n" \ 1511 " .set pop \n" \ 1512 : "=r" (mfhi0)); \ 1513 mfhi0; \ 1514 }) 1515 1516 #define mfhi1() \ 1517 ({ \ 1518 long mfhi1; \ 1519 __asm__( \ 1520 " .set push \n" \ 1521 " .set dsp \n" \ 1522 " mfhi %0, $ac1 \n" \ 1523 " .set pop \n" \ 1524 : "=r" (mfhi1)); \ 1525 mfhi1; \ 1526 }) 1527 1528 #define mfhi2() \ 1529 ({ \ 1530 long mfhi2; \ 1531 __asm__( \ 1532 " .set push \n" \ 1533 " .set dsp \n" \ 1534 " mfhi %0, $ac2 \n" \ 1535 " .set pop \n" \ 1536 : "=r" (mfhi2)); \ 1537 mfhi2; \ 1538 }) 1539 1540 #define mfhi3() \ 1541 ({ \ 1542 long mfhi3; \ 1543 __asm__( \ 1544 " .set push \n" \ 1545 " .set dsp \n" \ 1546 " mfhi %0, $ac3 \n" \ 1547 " .set pop \n" \ 1548 : "=r" (mfhi3)); \ 1549 mfhi3; \ 1550 }) 1551 1552 1553 #define mtlo0(x) \ 1554 ({ \ 1555 __asm__( \ 1556 " .set push \n" \ 1557 " .set dsp \n" \ 1558 " mtlo %0, $ac0 \n" \ 1559 " .set pop \n" \ 1560 : \ 1561 : "r" (x)); \ 1562 }) 1563 1564 #define mtlo1(x) \ 1565 ({ \ 1566 __asm__( \ 1567 " .set push \n" \ 1568 " .set dsp \n" \ 1569 " mtlo %0, $ac1 \n" \ 1570 " .set pop \n" \ 1571 : \ 1572 : "r" (x)); \ 1573 }) 1574 1575 #define mtlo2(x) \ 1576 ({ \ 1577 __asm__( \ 1578 " .set push \n" \ 1579 " .set dsp \n" \ 1580 " mtlo %0, $ac2 \n" \ 1581 " .set pop \n" \ 1582 : \ 1583 : "r" (x)); \ 1584 }) 1585 1586 #define mtlo3(x) \ 1587 ({ \ 1588 __asm__( \ 1589 " .set push \n" \ 1590 " .set dsp \n" \ 1591 " mtlo %0, $ac3 \n" \ 1592 " .set pop \n" \ 1593 : \ 1594 : "r" (x)); \ 1595 }) 1596 1597 #define mthi0(x) \ 1598 ({ \ 1599 __asm__( \ 1600 " .set push \n" \ 1601 " .set dsp \n" \ 1602 " mthi %0, $ac0 \n" \ 1603 " .set pop \n" \ 1604 : \ 1605 : "r" (x)); \ 1606 }) 1607 1608 #define mthi1(x) \ 1609 ({ \ 1610 __asm__( \ 1611 " .set push \n" \ 1612 " .set dsp \n" \ 1613 " mthi %0, $ac1 \n" \ 1614 " .set pop \n" \ 1615 : \ 1616 : "r" (x)); \ 1617 }) 1618 1619 #define mthi2(x) \ 1620 ({ \ 1621 __asm__( \ 1622 " .set push \n" \ 1623 " .set dsp \n" \ 1624 " mthi %0, $ac2 \n" \ 1625 " .set pop \n" \ 1626 : \ 1627 : "r" (x)); \ 1628 }) 1629 1630 #define mthi3(x) \ 1631 ({ \ 1632 __asm__( \ 1633 " .set push \n" \ 1634 " .set dsp \n" \ 1635 " mthi %0, $ac3 \n" \ 1636 " .set pop \n" \ 1637 : \ 1638 : "r" (x)); \ 1639 }) 1640 1641 #else 1642 1643 #ifdef CONFIG_CPU_MICROMIPS 1644 #define rddsp(mask) \ 1645 ({ \ 1646 unsigned int __res; \ 1647 \ 1648 __asm__ __volatile__( \ 1649 " .set push \n" \ 1650 " .set noat \n" \ 1651 " # rddsp $1, %x1 \n" \ 1652 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ 1653 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ 1654 " move %0, $1 \n" \ 1655 " .set pop \n" \ 1656 : "=r" (__res) \ 1657 : "i" (mask)); \ 1658 __res; \ 1659 }) 1660 1661 #define wrdsp(val, mask) \ 1662 do { \ 1663 __asm__ __volatile__( \ 1664 " .set push \n" \ 1665 " .set noat \n" \ 1666 " move $1, %0 \n" \ 1667 " # wrdsp $1, %x1 \n" \ 1668 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ 1669 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ 1670 " .set pop \n" \ 1671 : \ 1672 : "r" (val), "i" (mask)); \ 1673 } while (0) 1674 1675 #define _umips_dsp_mfxxx(ins) \ 1676 ({ \ 1677 unsigned long __treg; \ 1678 \ 1679 __asm__ __volatile__( \ 1680 " .set push \n" \ 1681 " .set noat \n" \ 1682 " .hword 0x0001 \n" \ 1683 " .hword %x1 \n" \ 1684 " move %0, $1 \n" \ 1685 " .set pop \n" \ 1686 : "=r" (__treg) \ 1687 : "i" (ins)); \ 1688 __treg; \ 1689 }) 1690 1691 #define _umips_dsp_mtxxx(val, ins) \ 1692 do { \ 1693 __asm__ __volatile__( \ 1694 " .set push \n" \ 1695 " .set noat \n" \ 1696 " move $1, %0 \n" \ 1697 " .hword 0x0001 \n" \ 1698 " .hword %x1 \n" \ 1699 " .set pop \n" \ 1700 : \ 1701 : "r" (val), "i" (ins)); \ 1702 } while (0) 1703 1704 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) 1705 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) 1706 1707 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) 1708 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) 1709 1710 #define mflo0() _umips_dsp_mflo(0) 1711 #define mflo1() _umips_dsp_mflo(1) 1712 #define mflo2() _umips_dsp_mflo(2) 1713 #define mflo3() _umips_dsp_mflo(3) 1714 1715 #define mfhi0() _umips_dsp_mfhi(0) 1716 #define mfhi1() _umips_dsp_mfhi(1) 1717 #define mfhi2() _umips_dsp_mfhi(2) 1718 #define mfhi3() _umips_dsp_mfhi(3) 1719 1720 #define mtlo0(x) _umips_dsp_mtlo(x, 0) 1721 #define mtlo1(x) _umips_dsp_mtlo(x, 1) 1722 #define mtlo2(x) _umips_dsp_mtlo(x, 2) 1723 #define mtlo3(x) _umips_dsp_mtlo(x, 3) 1724 1725 #define mthi0(x) _umips_dsp_mthi(x, 0) 1726 #define mthi1(x) _umips_dsp_mthi(x, 1) 1727 #define mthi2(x) _umips_dsp_mthi(x, 2) 1728 #define mthi3(x) _umips_dsp_mthi(x, 3) 1729 1730 #else /* !CONFIG_CPU_MICROMIPS */ 1731 #define rddsp(mask) \ 1732 ({ \ 1733 unsigned int __res; \ 1734 \ 1735 __asm__ __volatile__( \ 1736 " .set push \n" \ 1737 " .set noat \n" \ 1738 " # rddsp $1, %x1 \n" \ 1739 " .word 0x7c000cb8 | (%x1 << 16) \n" \ 1740 " move %0, $1 \n" \ 1741 " .set pop \n" \ 1742 : "=r" (__res) \ 1743 : "i" (mask)); \ 1744 __res; \ 1745 }) 1746 1747 #define wrdsp(val, mask) \ 1748 do { \ 1749 __asm__ __volatile__( \ 1750 " .set push \n" \ 1751 " .set noat \n" \ 1752 " move $1, %0 \n" \ 1753 " # wrdsp $1, %x1 \n" \ 1754 " .word 0x7c2004f8 | (%x1 << 11) \n" \ 1755 " .set pop \n" \ 1756 : \ 1757 : "r" (val), "i" (mask)); \ 1758 } while (0) 1759 1760 #define _dsp_mfxxx(ins) \ 1761 ({ \ 1762 unsigned long __treg; \ 1763 \ 1764 __asm__ __volatile__( \ 1765 " .set push \n" \ 1766 " .set noat \n" \ 1767 " .word (0x00000810 | %1) \n" \ 1768 " move %0, $1 \n" \ 1769 " .set pop \n" \ 1770 : "=r" (__treg) \ 1771 : "i" (ins)); \ 1772 __treg; \ 1773 }) 1774 1775 #define _dsp_mtxxx(val, ins) \ 1776 do { \ 1777 __asm__ __volatile__( \ 1778 " .set push \n" \ 1779 " .set noat \n" \ 1780 " move $1, %0 \n" \ 1781 " .word (0x00200011 | %1) \n" \ 1782 " .set pop \n" \ 1783 : \ 1784 : "r" (val), "i" (ins)); \ 1785 } while (0) 1786 1787 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) 1788 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) 1789 1790 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) 1791 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) 1792 1793 #define mflo0() _dsp_mflo(0) 1794 #define mflo1() _dsp_mflo(1) 1795 #define mflo2() _dsp_mflo(2) 1796 #define mflo3() _dsp_mflo(3) 1797 1798 #define mfhi0() _dsp_mfhi(0) 1799 #define mfhi1() _dsp_mfhi(1) 1800 #define mfhi2() _dsp_mfhi(2) 1801 #define mfhi3() _dsp_mfhi(3) 1802 1803 #define mtlo0(x) _dsp_mtlo(x, 0) 1804 #define mtlo1(x) _dsp_mtlo(x, 1) 1805 #define mtlo2(x) _dsp_mtlo(x, 2) 1806 #define mtlo3(x) _dsp_mtlo(x, 3) 1807 1808 #define mthi0(x) _dsp_mthi(x, 0) 1809 #define mthi1(x) _dsp_mthi(x, 1) 1810 #define mthi2(x) _dsp_mthi(x, 2) 1811 #define mthi3(x) _dsp_mthi(x, 3) 1812 1813 #endif /* CONFIG_CPU_MICROMIPS */ 1814 #endif 1815 1816 /* 1817 * TLB operations. 1818 * 1819 * It is responsibility of the caller to take care of any TLB hazards. 1820 */ 1821 static inline void tlb_probe(void) 1822 { 1823 __asm__ __volatile__( 1824 ".set noreorder\n\t" 1825 "tlbp\n\t" 1826 ".set reorder"); 1827 } 1828 1829 static inline void tlb_read(void) 1830 { 1831 #if MIPS34K_MISSED_ITLB_WAR 1832 int res = 0; 1833 1834 __asm__ __volatile__( 1835 " .set push \n" 1836 " .set noreorder \n" 1837 " .set noat \n" 1838 " .set mips32r2 \n" 1839 " .word 0x41610001 # dvpe $1 \n" 1840 " move %0, $1 \n" 1841 " ehb \n" 1842 " .set pop \n" 1843 : "=r" (res)); 1844 1845 instruction_hazard(); 1846 #endif 1847 1848 __asm__ __volatile__( 1849 ".set noreorder\n\t" 1850 "tlbr\n\t" 1851 ".set reorder"); 1852 1853 #if MIPS34K_MISSED_ITLB_WAR 1854 if ((res & _ULCAST_(1))) 1855 __asm__ __volatile__( 1856 " .set push \n" 1857 " .set noreorder \n" 1858 " .set noat \n" 1859 " .set mips32r2 \n" 1860 " .word 0x41600021 # evpe \n" 1861 " ehb \n" 1862 " .set pop \n"); 1863 #endif 1864 } 1865 1866 static inline void tlb_write_indexed(void) 1867 { 1868 __asm__ __volatile__( 1869 ".set noreorder\n\t" 1870 "tlbwi\n\t" 1871 ".set reorder"); 1872 } 1873 1874 static inline void tlb_write_random(void) 1875 { 1876 __asm__ __volatile__( 1877 ".set noreorder\n\t" 1878 "tlbwr\n\t" 1879 ".set reorder"); 1880 } 1881 1882 /* 1883 * Manipulate bits in a c0 register. 1884 */ 1885 #define __BUILD_SET_C0(name) \ 1886 static inline unsigned int \ 1887 set_c0_##name(unsigned int set) \ 1888 { \ 1889 unsigned int res, new; \ 1890 \ 1891 res = read_c0_##name(); \ 1892 new = res | set; \ 1893 write_c0_##name(new); \ 1894 \ 1895 return res; \ 1896 } \ 1897 \ 1898 static inline unsigned int \ 1899 clear_c0_##name(unsigned int clear) \ 1900 { \ 1901 unsigned int res, new; \ 1902 \ 1903 res = read_c0_##name(); \ 1904 new = res & ~clear; \ 1905 write_c0_##name(new); \ 1906 \ 1907 return res; \ 1908 } \ 1909 \ 1910 static inline unsigned int \ 1911 change_c0_##name(unsigned int change, unsigned int val) \ 1912 { \ 1913 unsigned int res, new; \ 1914 \ 1915 res = read_c0_##name(); \ 1916 new = res & ~change; \ 1917 new |= (val & change); \ 1918 write_c0_##name(new); \ 1919 \ 1920 return res; \ 1921 } 1922 1923 __BUILD_SET_C0(status) 1924 __BUILD_SET_C0(cause) 1925 __BUILD_SET_C0(config) 1926 __BUILD_SET_C0(config5) 1927 __BUILD_SET_C0(intcontrol) 1928 __BUILD_SET_C0(intctl) 1929 __BUILD_SET_C0(srsmap) 1930 __BUILD_SET_C0(pagegrain) 1931 __BUILD_SET_C0(brcm_config_0) 1932 __BUILD_SET_C0(brcm_bus_pll) 1933 __BUILD_SET_C0(brcm_reset) 1934 __BUILD_SET_C0(brcm_cmt_intr) 1935 __BUILD_SET_C0(brcm_cmt_ctrl) 1936 __BUILD_SET_C0(brcm_config) 1937 __BUILD_SET_C0(brcm_mode) 1938 1939 /* 1940 * Return low 10 bits of ebase. 1941 * Note that under KVM (MIPSVZ) this returns vcpu id. 1942 */ 1943 static inline unsigned int get_ebase_cpunum(void) 1944 { 1945 return read_c0_ebase() & 0x3ff; 1946 } 1947 1948 #endif /* !__ASSEMBLY__ */ 1949 1950 #endif /* _ASM_MIPSREGS_H */ 1951