1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 7 * Copyright (C) 2000 Silicon Graphics, Inc. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 12 */ 13 #ifndef _ASM_MIPSREGS_H 14 #define _ASM_MIPSREGS_H 15 16 #include <linux/linkage.h> 17 #include <asm/hazards.h> 18 #include <asm/war.h> 19 20 /* 21 * The following macros are especially useful for __asm__ 22 * inline assembler. 23 */ 24 #ifndef __STR 25 #define __STR(x) #x 26 #endif 27 #ifndef STR 28 #define STR(x) __STR(x) 29 #endif 30 31 /* 32 * Configure language 33 */ 34 #ifdef __ASSEMBLY__ 35 #define _ULCAST_ 36 #else 37 #define _ULCAST_ (unsigned long) 38 #endif 39 40 /* 41 * Coprocessor 0 register names 42 */ 43 #define CP0_INDEX $0 44 #define CP0_RANDOM $1 45 #define CP0_ENTRYLO0 $2 46 #define CP0_ENTRYLO1 $3 47 #define CP0_CONF $3 48 #define CP0_CONTEXT $4 49 #define CP0_PAGEMASK $5 50 #define CP0_WIRED $6 51 #define CP0_INFO $7 52 #define CP0_BADVADDR $8 53 #define CP0_COUNT $9 54 #define CP0_ENTRYHI $10 55 #define CP0_COMPARE $11 56 #define CP0_STATUS $12 57 #define CP0_CAUSE $13 58 #define CP0_EPC $14 59 #define CP0_PRID $15 60 #define CP0_CONFIG $16 61 #define CP0_LLADDR $17 62 #define CP0_WATCHLO $18 63 #define CP0_WATCHHI $19 64 #define CP0_XCONTEXT $20 65 #define CP0_FRAMEMASK $21 66 #define CP0_DIAGNOSTIC $22 67 #define CP0_DEBUG $23 68 #define CP0_DEPC $24 69 #define CP0_PERFORMANCE $25 70 #define CP0_ECC $26 71 #define CP0_CACHEERR $27 72 #define CP0_TAGLO $28 73 #define CP0_TAGHI $29 74 #define CP0_ERROREPC $30 75 #define CP0_DESAVE $31 76 77 /* 78 * R4640/R4650 cp0 register names. These registers are listed 79 * here only for completeness; without MMU these CPUs are not useable 80 * by Linux. A future ELKS port might take make Linux run on them 81 * though ... 82 */ 83 #define CP0_IBASE $0 84 #define CP0_IBOUND $1 85 #define CP0_DBASE $2 86 #define CP0_DBOUND $3 87 #define CP0_CALG $17 88 #define CP0_IWATCH $18 89 #define CP0_DWATCH $19 90 91 /* 92 * Coprocessor 0 Set 1 register names 93 */ 94 #define CP0_S1_DERRADDR0 $26 95 #define CP0_S1_DERRADDR1 $27 96 #define CP0_S1_INTCONTROL $20 97 98 /* 99 * Coprocessor 0 Set 2 register names 100 */ 101 #define CP0_S2_SRSCTL $12 /* MIPSR2 */ 102 103 /* 104 * Coprocessor 0 Set 3 register names 105 */ 106 #define CP0_S3_SRSMAP $12 /* MIPSR2 */ 107 108 /* 109 * TX39 Series 110 */ 111 #define CP0_TX39_CACHE $7 112 113 /* 114 * Coprocessor 1 (FPU) register names 115 */ 116 #define CP1_REVISION $0 117 #define CP1_STATUS $31 118 119 /* 120 * FPU Status Register Values 121 */ 122 /* 123 * Status Register Values 124 */ 125 126 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ 127 #define FPU_CSR_COND 0x00800000 /* $fcc0 */ 128 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ 129 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ 130 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ 131 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ 132 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ 133 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ 134 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ 135 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 136 137 /* 138 * X the exception cause indicator 139 * E the exception enable 140 * S the sticky/flag bit 141 */ 142 #define FPU_CSR_ALL_X 0x0003f000 143 #define FPU_CSR_UNI_X 0x00020000 144 #define FPU_CSR_INV_X 0x00010000 145 #define FPU_CSR_DIV_X 0x00008000 146 #define FPU_CSR_OVF_X 0x00004000 147 #define FPU_CSR_UDF_X 0x00002000 148 #define FPU_CSR_INE_X 0x00001000 149 150 #define FPU_CSR_ALL_E 0x00000f80 151 #define FPU_CSR_INV_E 0x00000800 152 #define FPU_CSR_DIV_E 0x00000400 153 #define FPU_CSR_OVF_E 0x00000200 154 #define FPU_CSR_UDF_E 0x00000100 155 #define FPU_CSR_INE_E 0x00000080 156 157 #define FPU_CSR_ALL_S 0x0000007c 158 #define FPU_CSR_INV_S 0x00000040 159 #define FPU_CSR_DIV_S 0x00000020 160 #define FPU_CSR_OVF_S 0x00000010 161 #define FPU_CSR_UDF_S 0x00000008 162 #define FPU_CSR_INE_S 0x00000004 163 164 /* rounding mode */ 165 #define FPU_CSR_RN 0x0 /* nearest */ 166 #define FPU_CSR_RZ 0x1 /* towards zero */ 167 #define FPU_CSR_RU 0x2 /* towards +Infinity */ 168 #define FPU_CSR_RD 0x3 /* towards -Infinity */ 169 170 171 /* 172 * Values for PageMask register 173 */ 174 #ifdef CONFIG_CPU_VR41XX 175 176 /* Why doesn't stupidity hurt ... */ 177 178 #define PM_1K 0x00000000 179 #define PM_4K 0x00001800 180 #define PM_16K 0x00007800 181 #define PM_64K 0x0001f800 182 #define PM_256K 0x0007f800 183 184 #else 185 186 #define PM_4K 0x00000000 187 #define PM_8K 0x00002000 188 #define PM_16K 0x00006000 189 #define PM_32K 0x0000e000 190 #define PM_64K 0x0001e000 191 #define PM_128K 0x0003e000 192 #define PM_256K 0x0007e000 193 #define PM_512K 0x000fe000 194 #define PM_1M 0x001fe000 195 #define PM_2M 0x003fe000 196 #define PM_4M 0x007fe000 197 #define PM_8M 0x00ffe000 198 #define PM_16M 0x01ffe000 199 #define PM_32M 0x03ffe000 200 #define PM_64M 0x07ffe000 201 #define PM_256M 0x1fffe000 202 #define PM_1G 0x7fffe000 203 204 #endif 205 206 /* 207 * Default page size for a given kernel configuration 208 */ 209 #ifdef CONFIG_PAGE_SIZE_4KB 210 #define PM_DEFAULT_MASK PM_4K 211 #elif defined(CONFIG_PAGE_SIZE_8KB) 212 #define PM_DEFAULT_MASK PM_8K 213 #elif defined(CONFIG_PAGE_SIZE_16KB) 214 #define PM_DEFAULT_MASK PM_16K 215 #elif defined(CONFIG_PAGE_SIZE_32KB) 216 #define PM_DEFAULT_MASK PM_32K 217 #elif defined(CONFIG_PAGE_SIZE_64KB) 218 #define PM_DEFAULT_MASK PM_64K 219 #else 220 #error Bad page size configuration! 221 #endif 222 223 /* 224 * Default huge tlb size for a given kernel configuration 225 */ 226 #ifdef CONFIG_PAGE_SIZE_4KB 227 #define PM_HUGE_MASK PM_1M 228 #elif defined(CONFIG_PAGE_SIZE_8KB) 229 #define PM_HUGE_MASK PM_4M 230 #elif defined(CONFIG_PAGE_SIZE_16KB) 231 #define PM_HUGE_MASK PM_16M 232 #elif defined(CONFIG_PAGE_SIZE_32KB) 233 #define PM_HUGE_MASK PM_64M 234 #elif defined(CONFIG_PAGE_SIZE_64KB) 235 #define PM_HUGE_MASK PM_256M 236 #elif defined(CONFIG_HUGETLB_PAGE) 237 #error Bad page size configuration for hugetlbfs! 238 #endif 239 240 /* 241 * Values used for computation of new tlb entries 242 */ 243 #define PL_4K 12 244 #define PL_16K 14 245 #define PL_64K 16 246 #define PL_256K 18 247 #define PL_1M 20 248 #define PL_4M 22 249 #define PL_16M 24 250 #define PL_64M 26 251 #define PL_256M 28 252 253 /* 254 * PageGrain bits 255 */ 256 #define PG_RIE (_ULCAST_(1) << 31) 257 #define PG_XIE (_ULCAST_(1) << 30) 258 #define PG_ELPA (_ULCAST_(1) << 29) 259 #define PG_ESP (_ULCAST_(1) << 28) 260 261 /* 262 * R4x00 interrupt enable / cause bits 263 */ 264 #define IE_SW0 (_ULCAST_(1) << 8) 265 #define IE_SW1 (_ULCAST_(1) << 9) 266 #define IE_IRQ0 (_ULCAST_(1) << 10) 267 #define IE_IRQ1 (_ULCAST_(1) << 11) 268 #define IE_IRQ2 (_ULCAST_(1) << 12) 269 #define IE_IRQ3 (_ULCAST_(1) << 13) 270 #define IE_IRQ4 (_ULCAST_(1) << 14) 271 #define IE_IRQ5 (_ULCAST_(1) << 15) 272 273 /* 274 * R4x00 interrupt cause bits 275 */ 276 #define C_SW0 (_ULCAST_(1) << 8) 277 #define C_SW1 (_ULCAST_(1) << 9) 278 #define C_IRQ0 (_ULCAST_(1) << 10) 279 #define C_IRQ1 (_ULCAST_(1) << 11) 280 #define C_IRQ2 (_ULCAST_(1) << 12) 281 #define C_IRQ3 (_ULCAST_(1) << 13) 282 #define C_IRQ4 (_ULCAST_(1) << 14) 283 #define C_IRQ5 (_ULCAST_(1) << 15) 284 285 /* 286 * Bitfields in the R4xx0 cp0 status register 287 */ 288 #define ST0_IE 0x00000001 289 #define ST0_EXL 0x00000002 290 #define ST0_ERL 0x00000004 291 #define ST0_KSU 0x00000018 292 # define KSU_USER 0x00000010 293 # define KSU_SUPERVISOR 0x00000008 294 # define KSU_KERNEL 0x00000000 295 #define ST0_UX 0x00000020 296 #define ST0_SX 0x00000040 297 #define ST0_KX 0x00000080 298 #define ST0_DE 0x00010000 299 #define ST0_CE 0x00020000 300 301 /* 302 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate 303 * cacheops in userspace. This bit exists only on RM7000 and RM9000 304 * processors. 305 */ 306 #define ST0_CO 0x08000000 307 308 /* 309 * Bitfields in the R[23]000 cp0 status register. 310 */ 311 #define ST0_IEC 0x00000001 312 #define ST0_KUC 0x00000002 313 #define ST0_IEP 0x00000004 314 #define ST0_KUP 0x00000008 315 #define ST0_IEO 0x00000010 316 #define ST0_KUO 0x00000020 317 /* bits 6 & 7 are reserved on R[23]000 */ 318 #define ST0_ISC 0x00010000 319 #define ST0_SWC 0x00020000 320 #define ST0_CM 0x00080000 321 322 /* 323 * Bits specific to the R4640/R4650 324 */ 325 #define ST0_UM (_ULCAST_(1) << 4) 326 #define ST0_IL (_ULCAST_(1) << 23) 327 #define ST0_DL (_ULCAST_(1) << 24) 328 329 /* 330 * Enable the MIPS MDMX and DSP ASEs 331 */ 332 #define ST0_MX 0x01000000 333 334 /* 335 * Bitfields in the TX39 family CP0 Configuration Register 3 336 */ 337 #define TX39_CONF_ICS_SHIFT 19 338 #define TX39_CONF_ICS_MASK 0x00380000 339 #define TX39_CONF_ICS_1KB 0x00000000 340 #define TX39_CONF_ICS_2KB 0x00080000 341 #define TX39_CONF_ICS_4KB 0x00100000 342 #define TX39_CONF_ICS_8KB 0x00180000 343 #define TX39_CONF_ICS_16KB 0x00200000 344 345 #define TX39_CONF_DCS_SHIFT 16 346 #define TX39_CONF_DCS_MASK 0x00070000 347 #define TX39_CONF_DCS_1KB 0x00000000 348 #define TX39_CONF_DCS_2KB 0x00010000 349 #define TX39_CONF_DCS_4KB 0x00020000 350 #define TX39_CONF_DCS_8KB 0x00030000 351 #define TX39_CONF_DCS_16KB 0x00040000 352 353 #define TX39_CONF_CWFON 0x00004000 354 #define TX39_CONF_WBON 0x00002000 355 #define TX39_CONF_RF_SHIFT 10 356 #define TX39_CONF_RF_MASK 0x00000c00 357 #define TX39_CONF_DOZE 0x00000200 358 #define TX39_CONF_HALT 0x00000100 359 #define TX39_CONF_LOCK 0x00000080 360 #define TX39_CONF_ICE 0x00000020 361 #define TX39_CONF_DCE 0x00000010 362 #define TX39_CONF_IRSIZE_SHIFT 2 363 #define TX39_CONF_IRSIZE_MASK 0x0000000c 364 #define TX39_CONF_DRSIZE_SHIFT 0 365 #define TX39_CONF_DRSIZE_MASK 0x00000003 366 367 /* 368 * Status register bits available in all MIPS CPUs. 369 */ 370 #define ST0_IM 0x0000ff00 371 #define STATUSB_IP0 8 372 #define STATUSF_IP0 (_ULCAST_(1) << 8) 373 #define STATUSB_IP1 9 374 #define STATUSF_IP1 (_ULCAST_(1) << 9) 375 #define STATUSB_IP2 10 376 #define STATUSF_IP2 (_ULCAST_(1) << 10) 377 #define STATUSB_IP3 11 378 #define STATUSF_IP3 (_ULCAST_(1) << 11) 379 #define STATUSB_IP4 12 380 #define STATUSF_IP4 (_ULCAST_(1) << 12) 381 #define STATUSB_IP5 13 382 #define STATUSF_IP5 (_ULCAST_(1) << 13) 383 #define STATUSB_IP6 14 384 #define STATUSF_IP6 (_ULCAST_(1) << 14) 385 #define STATUSB_IP7 15 386 #define STATUSF_IP7 (_ULCAST_(1) << 15) 387 #define STATUSB_IP8 0 388 #define STATUSF_IP8 (_ULCAST_(1) << 0) 389 #define STATUSB_IP9 1 390 #define STATUSF_IP9 (_ULCAST_(1) << 1) 391 #define STATUSB_IP10 2 392 #define STATUSF_IP10 (_ULCAST_(1) << 2) 393 #define STATUSB_IP11 3 394 #define STATUSF_IP11 (_ULCAST_(1) << 3) 395 #define STATUSB_IP12 4 396 #define STATUSF_IP12 (_ULCAST_(1) << 4) 397 #define STATUSB_IP13 5 398 #define STATUSF_IP13 (_ULCAST_(1) << 5) 399 #define STATUSB_IP14 6 400 #define STATUSF_IP14 (_ULCAST_(1) << 6) 401 #define STATUSB_IP15 7 402 #define STATUSF_IP15 (_ULCAST_(1) << 7) 403 #define ST0_CH 0x00040000 404 #define ST0_SR 0x00100000 405 #define ST0_TS 0x00200000 406 #define ST0_BEV 0x00400000 407 #define ST0_RE 0x02000000 408 #define ST0_FR 0x04000000 409 #define ST0_CU 0xf0000000 410 #define ST0_CU0 0x10000000 411 #define ST0_CU1 0x20000000 412 #define ST0_CU2 0x40000000 413 #define ST0_CU3 0x80000000 414 #define ST0_XX 0x80000000 /* MIPS IV naming */ 415 416 /* 417 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) 418 * 419 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 420 */ 421 #define INTCTLB_IPPCI 26 422 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) 423 #define INTCTLB_IPTI 29 424 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) 425 426 /* 427 * Bitfields and bit numbers in the coprocessor 0 cause register. 428 * 429 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 430 */ 431 #define CAUSEB_EXCCODE 2 432 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 433 #define CAUSEB_IP 8 434 #define CAUSEF_IP (_ULCAST_(255) << 8) 435 #define CAUSEB_IP0 8 436 #define CAUSEF_IP0 (_ULCAST_(1) << 8) 437 #define CAUSEB_IP1 9 438 #define CAUSEF_IP1 (_ULCAST_(1) << 9) 439 #define CAUSEB_IP2 10 440 #define CAUSEF_IP2 (_ULCAST_(1) << 10) 441 #define CAUSEB_IP3 11 442 #define CAUSEF_IP3 (_ULCAST_(1) << 11) 443 #define CAUSEB_IP4 12 444 #define CAUSEF_IP4 (_ULCAST_(1) << 12) 445 #define CAUSEB_IP5 13 446 #define CAUSEF_IP5 (_ULCAST_(1) << 13) 447 #define CAUSEB_IP6 14 448 #define CAUSEF_IP6 (_ULCAST_(1) << 14) 449 #define CAUSEB_IP7 15 450 #define CAUSEF_IP7 (_ULCAST_(1) << 15) 451 #define CAUSEB_IV 23 452 #define CAUSEF_IV (_ULCAST_(1) << 23) 453 #define CAUSEB_CE 28 454 #define CAUSEF_CE (_ULCAST_(3) << 28) 455 #define CAUSEB_TI 30 456 #define CAUSEF_TI (_ULCAST_(1) << 30) 457 #define CAUSEB_BD 31 458 #define CAUSEF_BD (_ULCAST_(1) << 31) 459 460 /* 461 * Bits in the coprocessor 0 config register. 462 */ 463 /* Generic bits. */ 464 #define CONF_CM_CACHABLE_NO_WA 0 465 #define CONF_CM_CACHABLE_WA 1 466 #define CONF_CM_UNCACHED 2 467 #define CONF_CM_CACHABLE_NONCOHERENT 3 468 #define CONF_CM_CACHABLE_CE 4 469 #define CONF_CM_CACHABLE_COW 5 470 #define CONF_CM_CACHABLE_CUW 6 471 #define CONF_CM_CACHABLE_ACCELERATED 7 472 #define CONF_CM_CMASK 7 473 #define CONF_BE (_ULCAST_(1) << 15) 474 475 /* Bits common to various processors. */ 476 #define CONF_CU (_ULCAST_(1) << 3) 477 #define CONF_DB (_ULCAST_(1) << 4) 478 #define CONF_IB (_ULCAST_(1) << 5) 479 #define CONF_DC (_ULCAST_(7) << 6) 480 #define CONF_IC (_ULCAST_(7) << 9) 481 #define CONF_EB (_ULCAST_(1) << 13) 482 #define CONF_EM (_ULCAST_(1) << 14) 483 #define CONF_SM (_ULCAST_(1) << 16) 484 #define CONF_SC (_ULCAST_(1) << 17) 485 #define CONF_EW (_ULCAST_(3) << 18) 486 #define CONF_EP (_ULCAST_(15)<< 24) 487 #define CONF_EC (_ULCAST_(7) << 28) 488 #define CONF_CM (_ULCAST_(1) << 31) 489 490 /* Bits specific to the R4xx0. */ 491 #define R4K_CONF_SW (_ULCAST_(1) << 20) 492 #define R4K_CONF_SS (_ULCAST_(1) << 21) 493 #define R4K_CONF_SB (_ULCAST_(3) << 22) 494 495 /* Bits specific to the R5000. */ 496 #define R5K_CONF_SE (_ULCAST_(1) << 12) 497 #define R5K_CONF_SS (_ULCAST_(3) << 20) 498 499 /* Bits specific to the RM7000. */ 500 #define RM7K_CONF_SE (_ULCAST_(1) << 3) 501 #define RM7K_CONF_TE (_ULCAST_(1) << 12) 502 #define RM7K_CONF_CLK (_ULCAST_(1) << 16) 503 #define RM7K_CONF_TC (_ULCAST_(1) << 17) 504 #define RM7K_CONF_SI (_ULCAST_(3) << 20) 505 #define RM7K_CONF_SC (_ULCAST_(1) << 31) 506 507 /* Bits specific to the R10000. */ 508 #define R10K_CONF_DN (_ULCAST_(3) << 3) 509 #define R10K_CONF_CT (_ULCAST_(1) << 5) 510 #define R10K_CONF_PE (_ULCAST_(1) << 6) 511 #define R10K_CONF_PM (_ULCAST_(3) << 7) 512 #define R10K_CONF_EC (_ULCAST_(15)<< 9) 513 #define R10K_CONF_SB (_ULCAST_(1) << 13) 514 #define R10K_CONF_SK (_ULCAST_(1) << 14) 515 #define R10K_CONF_SS (_ULCAST_(7) << 16) 516 #define R10K_CONF_SC (_ULCAST_(7) << 19) 517 #define R10K_CONF_DC (_ULCAST_(7) << 26) 518 #define R10K_CONF_IC (_ULCAST_(7) << 29) 519 520 /* Bits specific to the VR41xx. */ 521 #define VR41_CONF_CS (_ULCAST_(1) << 12) 522 #define VR41_CONF_P4K (_ULCAST_(1) << 13) 523 #define VR41_CONF_BP (_ULCAST_(1) << 16) 524 #define VR41_CONF_M16 (_ULCAST_(1) << 20) 525 #define VR41_CONF_AD (_ULCAST_(1) << 23) 526 527 /* Bits specific to the R30xx. */ 528 #define R30XX_CONF_FDM (_ULCAST_(1) << 19) 529 #define R30XX_CONF_REV (_ULCAST_(1) << 22) 530 #define R30XX_CONF_AC (_ULCAST_(1) << 23) 531 #define R30XX_CONF_RF (_ULCAST_(1) << 24) 532 #define R30XX_CONF_HALT (_ULCAST_(1) << 25) 533 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 534 #define R30XX_CONF_DBR (_ULCAST_(1) << 29) 535 #define R30XX_CONF_SB (_ULCAST_(1) << 30) 536 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 537 538 /* Bits specific to the TX49. */ 539 #define TX49_CONF_DC (_ULCAST_(1) << 16) 540 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 541 #define TX49_CONF_HALT (_ULCAST_(1) << 18) 542 #define TX49_CONF_CWFON (_ULCAST_(1) << 27) 543 544 /* Bits specific to the MIPS32/64 PRA. */ 545 #define MIPS_CONF_MT (_ULCAST_(7) << 7) 546 #define MIPS_CONF_AR (_ULCAST_(7) << 10) 547 #define MIPS_CONF_AT (_ULCAST_(3) << 13) 548 #define MIPS_CONF_M (_ULCAST_(1) << 31) 549 550 /* 551 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 552 */ 553 #define MIPS_CONF1_FP (_ULCAST_(1) << 0) 554 #define MIPS_CONF1_EP (_ULCAST_(1) << 1) 555 #define MIPS_CONF1_CA (_ULCAST_(1) << 2) 556 #define MIPS_CONF1_WR (_ULCAST_(1) << 3) 557 #define MIPS_CONF1_PC (_ULCAST_(1) << 4) 558 #define MIPS_CONF1_MD (_ULCAST_(1) << 5) 559 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 560 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) 561 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) 562 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) 563 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) 564 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) 565 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) 566 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) 567 568 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 569 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 570 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 571 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 572 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 573 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 574 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 575 #define MIPS_CONF2_TU (_ULCAST_(7) << 28) 576 577 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 578 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 579 #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 580 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 581 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 582 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 583 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 584 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 585 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 586 587 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 588 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 589 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 590 591 #define MIPS_CONF7_WII (_ULCAST_(1) << 31) 592 593 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 594 595 596 /* 597 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 598 */ 599 #define MIPS_FPIR_S (_ULCAST_(1) << 16) 600 #define MIPS_FPIR_D (_ULCAST_(1) << 17) 601 #define MIPS_FPIR_PS (_ULCAST_(1) << 18) 602 #define MIPS_FPIR_3D (_ULCAST_(1) << 19) 603 #define MIPS_FPIR_W (_ULCAST_(1) << 20) 604 #define MIPS_FPIR_L (_ULCAST_(1) << 21) 605 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 606 607 #ifndef __ASSEMBLY__ 608 609 /* 610 * Functions to access the R10000 performance counters. These are basically 611 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 612 * performance counter number encoded into bits 1 ... 5 of the instruction. 613 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware 614 * disassembler these will look like an access to sel 0 or 1. 615 */ 616 #define read_r10k_perf_cntr(counter) \ 617 ({ \ 618 unsigned int __res; \ 619 __asm__ __volatile__( \ 620 "mfpc\t%0, %1" \ 621 : "=r" (__res) \ 622 : "i" (counter)); \ 623 \ 624 __res; \ 625 }) 626 627 #define write_r10k_perf_cntr(counter,val) \ 628 do { \ 629 __asm__ __volatile__( \ 630 "mtpc\t%0, %1" \ 631 : \ 632 : "r" (val), "i" (counter)); \ 633 } while (0) 634 635 #define read_r10k_perf_event(counter) \ 636 ({ \ 637 unsigned int __res; \ 638 __asm__ __volatile__( \ 639 "mfps\t%0, %1" \ 640 : "=r" (__res) \ 641 : "i" (counter)); \ 642 \ 643 __res; \ 644 }) 645 646 #define write_r10k_perf_cntl(counter,val) \ 647 do { \ 648 __asm__ __volatile__( \ 649 "mtps\t%0, %1" \ 650 : \ 651 : "r" (val), "i" (counter)); \ 652 } while (0) 653 654 655 /* 656 * Macros to access the system control coprocessor 657 */ 658 659 #define __read_32bit_c0_register(source, sel) \ 660 ({ int __res; \ 661 if (sel == 0) \ 662 __asm__ __volatile__( \ 663 "mfc0\t%0, " #source "\n\t" \ 664 : "=r" (__res)); \ 665 else \ 666 __asm__ __volatile__( \ 667 ".set\tmips32\n\t" \ 668 "mfc0\t%0, " #source ", " #sel "\n\t" \ 669 ".set\tmips0\n\t" \ 670 : "=r" (__res)); \ 671 __res; \ 672 }) 673 674 #define __read_64bit_c0_register(source, sel) \ 675 ({ unsigned long long __res; \ 676 if (sizeof(unsigned long) == 4) \ 677 __res = __read_64bit_c0_split(source, sel); \ 678 else if (sel == 0) \ 679 __asm__ __volatile__( \ 680 ".set\tmips3\n\t" \ 681 "dmfc0\t%0, " #source "\n\t" \ 682 ".set\tmips0" \ 683 : "=r" (__res)); \ 684 else \ 685 __asm__ __volatile__( \ 686 ".set\tmips64\n\t" \ 687 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 688 ".set\tmips0" \ 689 : "=r" (__res)); \ 690 __res; \ 691 }) 692 693 #define __write_32bit_c0_register(register, sel, value) \ 694 do { \ 695 if (sel == 0) \ 696 __asm__ __volatile__( \ 697 "mtc0\t%z0, " #register "\n\t" \ 698 : : "Jr" ((unsigned int)(value))); \ 699 else \ 700 __asm__ __volatile__( \ 701 ".set\tmips32\n\t" \ 702 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 703 ".set\tmips0" \ 704 : : "Jr" ((unsigned int)(value))); \ 705 } while (0) 706 707 #define __write_64bit_c0_register(register, sel, value) \ 708 do { \ 709 if (sizeof(unsigned long) == 4) \ 710 __write_64bit_c0_split(register, sel, value); \ 711 else if (sel == 0) \ 712 __asm__ __volatile__( \ 713 ".set\tmips3\n\t" \ 714 "dmtc0\t%z0, " #register "\n\t" \ 715 ".set\tmips0" \ 716 : : "Jr" (value)); \ 717 else \ 718 __asm__ __volatile__( \ 719 ".set\tmips64\n\t" \ 720 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 721 ".set\tmips0" \ 722 : : "Jr" (value)); \ 723 } while (0) 724 725 #define __read_ulong_c0_register(reg, sel) \ 726 ((sizeof(unsigned long) == 4) ? \ 727 (unsigned long) __read_32bit_c0_register(reg, sel) : \ 728 (unsigned long) __read_64bit_c0_register(reg, sel)) 729 730 #define __write_ulong_c0_register(reg, sel, val) \ 731 do { \ 732 if (sizeof(unsigned long) == 4) \ 733 __write_32bit_c0_register(reg, sel, val); \ 734 else \ 735 __write_64bit_c0_register(reg, sel, val); \ 736 } while (0) 737 738 /* 739 * On RM7000/RM9000 these are uses to access cop0 set 1 registers 740 */ 741 #define __read_32bit_c0_ctrl_register(source) \ 742 ({ int __res; \ 743 __asm__ __volatile__( \ 744 "cfc0\t%0, " #source "\n\t" \ 745 : "=r" (__res)); \ 746 __res; \ 747 }) 748 749 #define __write_32bit_c0_ctrl_register(register, value) \ 750 do { \ 751 __asm__ __volatile__( \ 752 "ctc0\t%z0, " #register "\n\t" \ 753 : : "Jr" ((unsigned int)(value))); \ 754 } while (0) 755 756 /* 757 * These versions are only needed for systems with more than 38 bits of 758 * physical address space running the 32-bit kernel. That's none atm :-) 759 */ 760 #define __read_64bit_c0_split(source, sel) \ 761 ({ \ 762 unsigned long long __val; \ 763 unsigned long __flags; \ 764 \ 765 local_irq_save(__flags); \ 766 if (sel == 0) \ 767 __asm__ __volatile__( \ 768 ".set\tmips64\n\t" \ 769 "dmfc0\t%M0, " #source "\n\t" \ 770 "dsll\t%L0, %M0, 32\n\t" \ 771 "dsra\t%M0, %M0, 32\n\t" \ 772 "dsra\t%L0, %L0, 32\n\t" \ 773 ".set\tmips0" \ 774 : "=r" (__val)); \ 775 else \ 776 __asm__ __volatile__( \ 777 ".set\tmips64\n\t" \ 778 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 779 "dsll\t%L0, %M0, 32\n\t" \ 780 "dsra\t%M0, %M0, 32\n\t" \ 781 "dsra\t%L0, %L0, 32\n\t" \ 782 ".set\tmips0" \ 783 : "=r" (__val)); \ 784 local_irq_restore(__flags); \ 785 \ 786 __val; \ 787 }) 788 789 #define __write_64bit_c0_split(source, sel, val) \ 790 do { \ 791 unsigned long __flags; \ 792 \ 793 local_irq_save(__flags); \ 794 if (sel == 0) \ 795 __asm__ __volatile__( \ 796 ".set\tmips64\n\t" \ 797 "dsll\t%L0, %L0, 32\n\t" \ 798 "dsrl\t%L0, %L0, 32\n\t" \ 799 "dsll\t%M0, %M0, 32\n\t" \ 800 "or\t%L0, %L0, %M0\n\t" \ 801 "dmtc0\t%L0, " #source "\n\t" \ 802 ".set\tmips0" \ 803 : : "r" (val)); \ 804 else \ 805 __asm__ __volatile__( \ 806 ".set\tmips64\n\t" \ 807 "dsll\t%L0, %L0, 32\n\t" \ 808 "dsrl\t%L0, %L0, 32\n\t" \ 809 "dsll\t%M0, %M0, 32\n\t" \ 810 "or\t%L0, %L0, %M0\n\t" \ 811 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 812 ".set\tmips0" \ 813 : : "r" (val)); \ 814 local_irq_restore(__flags); \ 815 } while (0) 816 817 #define read_c0_index() __read_32bit_c0_register($0, 0) 818 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 819 820 #define read_c0_random() __read_32bit_c0_register($1, 0) 821 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 822 823 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 824 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 825 826 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 827 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 828 829 #define read_c0_conf() __read_32bit_c0_register($3, 0) 830 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 831 832 #define read_c0_context() __read_ulong_c0_register($4, 0) 833 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 834 835 #define read_c0_userlocal() __read_ulong_c0_register($4, 2) 836 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 837 838 #define read_c0_pagemask() __read_32bit_c0_register($5, 0) 839 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 840 841 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1) 842 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) 843 844 #define read_c0_wired() __read_32bit_c0_register($6, 0) 845 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 846 847 #define read_c0_info() __read_32bit_c0_register($7, 0) 848 849 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 850 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 851 852 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 853 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) 854 855 #define read_c0_count() __read_32bit_c0_register($9, 0) 856 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 857 858 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ 859 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 860 861 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ 862 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 863 864 #define read_c0_entryhi() __read_ulong_c0_register($10, 0) 865 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 866 867 #define read_c0_compare() __read_32bit_c0_register($11, 0) 868 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 869 870 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ 871 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 872 873 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ 874 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 875 876 #define read_c0_status() __read_32bit_c0_register($12, 0) 877 #ifdef CONFIG_MIPS_MT_SMTC 878 #define write_c0_status(val) \ 879 do { \ 880 __write_32bit_c0_register($12, 0, val); \ 881 __ehb(); \ 882 } while (0) 883 #else 884 /* 885 * Legacy non-SMTC code, which may be hazardous 886 * but which might not support EHB 887 */ 888 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 889 #endif /* CONFIG_MIPS_MT_SMTC */ 890 891 #define read_c0_cause() __read_32bit_c0_register($13, 0) 892 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 893 894 #define read_c0_epc() __read_ulong_c0_register($14, 0) 895 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 896 897 #define read_c0_prid() __read_32bit_c0_register($15, 0) 898 899 #define read_c0_config() __read_32bit_c0_register($16, 0) 900 #define read_c0_config1() __read_32bit_c0_register($16, 1) 901 #define read_c0_config2() __read_32bit_c0_register($16, 2) 902 #define read_c0_config3() __read_32bit_c0_register($16, 3) 903 #define read_c0_config4() __read_32bit_c0_register($16, 4) 904 #define read_c0_config5() __read_32bit_c0_register($16, 5) 905 #define read_c0_config6() __read_32bit_c0_register($16, 6) 906 #define read_c0_config7() __read_32bit_c0_register($16, 7) 907 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 908 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 909 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 910 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 911 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) 912 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) 913 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 914 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 915 916 /* 917 * The WatchLo register. There may be upto 8 of them. 918 */ 919 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 920 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 921 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 922 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 923 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 924 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 925 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 926 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 927 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 928 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 929 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 930 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 931 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 932 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 933 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 934 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 935 936 /* 937 * The WatchHi register. There may be upto 8 of them. 938 */ 939 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 940 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 941 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 942 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 943 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 944 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 945 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 946 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 947 948 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 949 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 950 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 951 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 952 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 953 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 954 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 955 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 956 957 #define read_c0_xcontext() __read_ulong_c0_register($20, 0) 958 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 959 960 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) 961 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 962 963 #define read_c0_framemask() __read_32bit_c0_register($21, 0) 964 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 965 966 /* RM9000 PerfControl performance counter control register */ 967 #define read_c0_perfcontrol() __read_32bit_c0_register($22, 0) 968 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val) 969 970 #define read_c0_diag() __read_32bit_c0_register($22, 0) 971 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 972 973 #define read_c0_diag1() __read_32bit_c0_register($22, 1) 974 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) 975 976 #define read_c0_diag2() __read_32bit_c0_register($22, 2) 977 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) 978 979 #define read_c0_diag3() __read_32bit_c0_register($22, 3) 980 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) 981 982 #define read_c0_diag4() __read_32bit_c0_register($22, 4) 983 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) 984 985 #define read_c0_diag5() __read_32bit_c0_register($22, 5) 986 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) 987 988 #define read_c0_debug() __read_32bit_c0_register($23, 0) 989 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 990 991 #define read_c0_depc() __read_ulong_c0_register($24, 0) 992 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 993 994 /* 995 * MIPS32 / MIPS64 performance counters 996 */ 997 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 998 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 999 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 1000 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 1001 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 1002 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 1003 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 1004 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 1005 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 1006 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 1007 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 1008 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 1009 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 1010 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 1011 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 1012 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 1013 1014 /* RM9000 PerfCount performance counter register */ 1015 #define read_c0_perfcount() __read_64bit_c0_register($25, 0) 1016 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val) 1017 1018 #define read_c0_ecc() __read_32bit_c0_register($26, 0) 1019 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 1020 1021 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 1022 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 1023 1024 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 1025 1026 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 1027 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 1028 1029 #define read_c0_taglo() __read_32bit_c0_register($28, 0) 1030 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 1031 1032 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) 1033 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) 1034 1035 #define read_c0_taghi() __read_32bit_c0_register($29, 0) 1036 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 1037 1038 #define read_c0_errorepc() __read_ulong_c0_register($30, 0) 1039 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 1040 1041 /* MIPSR2 */ 1042 #define read_c0_hwrena() __read_32bit_c0_register($7, 0) 1043 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 1044 1045 #define read_c0_intctl() __read_32bit_c0_register($12, 1) 1046 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) 1047 1048 #define read_c0_srsctl() __read_32bit_c0_register($12, 2) 1049 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) 1050 1051 #define read_c0_srsmap() __read_32bit_c0_register($12, 3) 1052 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 1053 1054 #define read_c0_ebase() __read_32bit_c0_register($15, 1) 1055 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1056 1057 1058 /* Cavium OCTEON (cnMIPS) */ 1059 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1060 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) 1061 1062 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) 1063 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) 1064 1065 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) 1066 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) 1067 /* 1068 * The cacheerr registers are not standardized. On OCTEON, they are 1069 * 64 bits wide. 1070 */ 1071 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) 1072 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) 1073 1074 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) 1075 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) 1076 1077 /* 1078 * Macros to access the floating point coprocessor control registers 1079 */ 1080 #define read_32bit_cp1_register(source) \ 1081 ({ int __res; \ 1082 __asm__ __volatile__( \ 1083 ".set\tpush\n\t" \ 1084 ".set\treorder\n\t" \ 1085 /* gas fails to assemble cfc1 for some archs (octeon).*/ \ 1086 ".set\tmips1\n\t" \ 1087 "cfc1\t%0,"STR(source)"\n\t" \ 1088 ".set\tpop" \ 1089 : "=r" (__res)); \ 1090 __res;}) 1091 1092 #define rddsp(mask) \ 1093 ({ \ 1094 unsigned int __res; \ 1095 \ 1096 __asm__ __volatile__( \ 1097 " .set push \n" \ 1098 " .set noat \n" \ 1099 " # rddsp $1, %x1 \n" \ 1100 " .word 0x7c000cb8 | (%x1 << 16) \n" \ 1101 " move %0, $1 \n" \ 1102 " .set pop \n" \ 1103 : "=r" (__res) \ 1104 : "i" (mask)); \ 1105 __res; \ 1106 }) 1107 1108 #define wrdsp(val, mask) \ 1109 do { \ 1110 __asm__ __volatile__( \ 1111 " .set push \n" \ 1112 " .set noat \n" \ 1113 " move $1, %0 \n" \ 1114 " # wrdsp $1, %x1 \n" \ 1115 " .word 0x7c2004f8 | (%x1 << 11) \n" \ 1116 " .set pop \n" \ 1117 : \ 1118 : "r" (val), "i" (mask)); \ 1119 } while (0) 1120 1121 #if 0 /* Need DSP ASE capable assembler ... */ 1122 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) 1123 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) 1124 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) 1125 #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;}) 1126 1127 #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;}) 1128 #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;}) 1129 #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;}) 1130 #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;}) 1131 1132 #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x)) 1133 #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x)) 1134 #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x)) 1135 #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x)) 1136 1137 #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x)) 1138 #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x)) 1139 #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x)) 1140 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x)) 1141 1142 #else 1143 1144 #define mfhi0() \ 1145 ({ \ 1146 unsigned long __treg; \ 1147 \ 1148 __asm__ __volatile__( \ 1149 " .set push \n" \ 1150 " .set noat \n" \ 1151 " # mfhi %0, $ac0 \n" \ 1152 " .word 0x00000810 \n" \ 1153 " move %0, $1 \n" \ 1154 " .set pop \n" \ 1155 : "=r" (__treg)); \ 1156 __treg; \ 1157 }) 1158 1159 #define mfhi1() \ 1160 ({ \ 1161 unsigned long __treg; \ 1162 \ 1163 __asm__ __volatile__( \ 1164 " .set push \n" \ 1165 " .set noat \n" \ 1166 " # mfhi %0, $ac1 \n" \ 1167 " .word 0x00200810 \n" \ 1168 " move %0, $1 \n" \ 1169 " .set pop \n" \ 1170 : "=r" (__treg)); \ 1171 __treg; \ 1172 }) 1173 1174 #define mfhi2() \ 1175 ({ \ 1176 unsigned long __treg; \ 1177 \ 1178 __asm__ __volatile__( \ 1179 " .set push \n" \ 1180 " .set noat \n" \ 1181 " # mfhi %0, $ac2 \n" \ 1182 " .word 0x00400810 \n" \ 1183 " move %0, $1 \n" \ 1184 " .set pop \n" \ 1185 : "=r" (__treg)); \ 1186 __treg; \ 1187 }) 1188 1189 #define mfhi3() \ 1190 ({ \ 1191 unsigned long __treg; \ 1192 \ 1193 __asm__ __volatile__( \ 1194 " .set push \n" \ 1195 " .set noat \n" \ 1196 " # mfhi %0, $ac3 \n" \ 1197 " .word 0x00600810 \n" \ 1198 " move %0, $1 \n" \ 1199 " .set pop \n" \ 1200 : "=r" (__treg)); \ 1201 __treg; \ 1202 }) 1203 1204 #define mflo0() \ 1205 ({ \ 1206 unsigned long __treg; \ 1207 \ 1208 __asm__ __volatile__( \ 1209 " .set push \n" \ 1210 " .set noat \n" \ 1211 " # mflo %0, $ac0 \n" \ 1212 " .word 0x00000812 \n" \ 1213 " move %0, $1 \n" \ 1214 " .set pop \n" \ 1215 : "=r" (__treg)); \ 1216 __treg; \ 1217 }) 1218 1219 #define mflo1() \ 1220 ({ \ 1221 unsigned long __treg; \ 1222 \ 1223 __asm__ __volatile__( \ 1224 " .set push \n" \ 1225 " .set noat \n" \ 1226 " # mflo %0, $ac1 \n" \ 1227 " .word 0x00200812 \n" \ 1228 " move %0, $1 \n" \ 1229 " .set pop \n" \ 1230 : "=r" (__treg)); \ 1231 __treg; \ 1232 }) 1233 1234 #define mflo2() \ 1235 ({ \ 1236 unsigned long __treg; \ 1237 \ 1238 __asm__ __volatile__( \ 1239 " .set push \n" \ 1240 " .set noat \n" \ 1241 " # mflo %0, $ac2 \n" \ 1242 " .word 0x00400812 \n" \ 1243 " move %0, $1 \n" \ 1244 " .set pop \n" \ 1245 : "=r" (__treg)); \ 1246 __treg; \ 1247 }) 1248 1249 #define mflo3() \ 1250 ({ \ 1251 unsigned long __treg; \ 1252 \ 1253 __asm__ __volatile__( \ 1254 " .set push \n" \ 1255 " .set noat \n" \ 1256 " # mflo %0, $ac3 \n" \ 1257 " .word 0x00600812 \n" \ 1258 " move %0, $1 \n" \ 1259 " .set pop \n" \ 1260 : "=r" (__treg)); \ 1261 __treg; \ 1262 }) 1263 1264 #define mthi0(x) \ 1265 do { \ 1266 __asm__ __volatile__( \ 1267 " .set push \n" \ 1268 " .set noat \n" \ 1269 " move $1, %0 \n" \ 1270 " # mthi $1, $ac0 \n" \ 1271 " .word 0x00200011 \n" \ 1272 " .set pop \n" \ 1273 : \ 1274 : "r" (x)); \ 1275 } while (0) 1276 1277 #define mthi1(x) \ 1278 do { \ 1279 __asm__ __volatile__( \ 1280 " .set push \n" \ 1281 " .set noat \n" \ 1282 " move $1, %0 \n" \ 1283 " # mthi $1, $ac1 \n" \ 1284 " .word 0x00200811 \n" \ 1285 " .set pop \n" \ 1286 : \ 1287 : "r" (x)); \ 1288 } while (0) 1289 1290 #define mthi2(x) \ 1291 do { \ 1292 __asm__ __volatile__( \ 1293 " .set push \n" \ 1294 " .set noat \n" \ 1295 " move $1, %0 \n" \ 1296 " # mthi $1, $ac2 \n" \ 1297 " .word 0x00201011 \n" \ 1298 " .set pop \n" \ 1299 : \ 1300 : "r" (x)); \ 1301 } while (0) 1302 1303 #define mthi3(x) \ 1304 do { \ 1305 __asm__ __volatile__( \ 1306 " .set push \n" \ 1307 " .set noat \n" \ 1308 " move $1, %0 \n" \ 1309 " # mthi $1, $ac3 \n" \ 1310 " .word 0x00201811 \n" \ 1311 " .set pop \n" \ 1312 : \ 1313 : "r" (x)); \ 1314 } while (0) 1315 1316 #define mtlo0(x) \ 1317 do { \ 1318 __asm__ __volatile__( \ 1319 " .set push \n" \ 1320 " .set noat \n" \ 1321 " move $1, %0 \n" \ 1322 " # mtlo $1, $ac0 \n" \ 1323 " .word 0x00200013 \n" \ 1324 " .set pop \n" \ 1325 : \ 1326 : "r" (x)); \ 1327 } while (0) 1328 1329 #define mtlo1(x) \ 1330 do { \ 1331 __asm__ __volatile__( \ 1332 " .set push \n" \ 1333 " .set noat \n" \ 1334 " move $1, %0 \n" \ 1335 " # mtlo $1, $ac1 \n" \ 1336 " .word 0x00200813 \n" \ 1337 " .set pop \n" \ 1338 : \ 1339 : "r" (x)); \ 1340 } while (0) 1341 1342 #define mtlo2(x) \ 1343 do { \ 1344 __asm__ __volatile__( \ 1345 " .set push \n" \ 1346 " .set noat \n" \ 1347 " move $1, %0 \n" \ 1348 " # mtlo $1, $ac2 \n" \ 1349 " .word 0x00201013 \n" \ 1350 " .set pop \n" \ 1351 : \ 1352 : "r" (x)); \ 1353 } while (0) 1354 1355 #define mtlo3(x) \ 1356 do { \ 1357 __asm__ __volatile__( \ 1358 " .set push \n" \ 1359 " .set noat \n" \ 1360 " move $1, %0 \n" \ 1361 " # mtlo $1, $ac3 \n" \ 1362 " .word 0x00201813 \n" \ 1363 " .set pop \n" \ 1364 : \ 1365 : "r" (x)); \ 1366 } while (0) 1367 1368 #endif 1369 1370 /* 1371 * TLB operations. 1372 * 1373 * It is responsibility of the caller to take care of any TLB hazards. 1374 */ 1375 static inline void tlb_probe(void) 1376 { 1377 __asm__ __volatile__( 1378 ".set noreorder\n\t" 1379 "tlbp\n\t" 1380 ".set reorder"); 1381 } 1382 1383 static inline void tlb_read(void) 1384 { 1385 #if MIPS34K_MISSED_ITLB_WAR 1386 int res = 0; 1387 1388 __asm__ __volatile__( 1389 " .set push \n" 1390 " .set noreorder \n" 1391 " .set noat \n" 1392 " .set mips32r2 \n" 1393 " .word 0x41610001 # dvpe $1 \n" 1394 " move %0, $1 \n" 1395 " ehb \n" 1396 " .set pop \n" 1397 : "=r" (res)); 1398 1399 instruction_hazard(); 1400 #endif 1401 1402 __asm__ __volatile__( 1403 ".set noreorder\n\t" 1404 "tlbr\n\t" 1405 ".set reorder"); 1406 1407 #if MIPS34K_MISSED_ITLB_WAR 1408 if ((res & _ULCAST_(1))) 1409 __asm__ __volatile__( 1410 " .set push \n" 1411 " .set noreorder \n" 1412 " .set noat \n" 1413 " .set mips32r2 \n" 1414 " .word 0x41600021 # evpe \n" 1415 " ehb \n" 1416 " .set pop \n"); 1417 #endif 1418 } 1419 1420 static inline void tlb_write_indexed(void) 1421 { 1422 __asm__ __volatile__( 1423 ".set noreorder\n\t" 1424 "tlbwi\n\t" 1425 ".set reorder"); 1426 } 1427 1428 static inline void tlb_write_random(void) 1429 { 1430 __asm__ __volatile__( 1431 ".set noreorder\n\t" 1432 "tlbwr\n\t" 1433 ".set reorder"); 1434 } 1435 1436 /* 1437 * Manipulate bits in a c0 register. 1438 */ 1439 #ifndef CONFIG_MIPS_MT_SMTC 1440 /* 1441 * SMTC Linux requires shutting-down microthread scheduling 1442 * during CP0 register read-modify-write sequences. 1443 */ 1444 #define __BUILD_SET_C0(name) \ 1445 static inline unsigned int \ 1446 set_c0_##name(unsigned int set) \ 1447 { \ 1448 unsigned int res, new; \ 1449 \ 1450 res = read_c0_##name(); \ 1451 new = res | set; \ 1452 write_c0_##name(new); \ 1453 \ 1454 return res; \ 1455 } \ 1456 \ 1457 static inline unsigned int \ 1458 clear_c0_##name(unsigned int clear) \ 1459 { \ 1460 unsigned int res, new; \ 1461 \ 1462 res = read_c0_##name(); \ 1463 new = res & ~clear; \ 1464 write_c0_##name(new); \ 1465 \ 1466 return res; \ 1467 } \ 1468 \ 1469 static inline unsigned int \ 1470 change_c0_##name(unsigned int change, unsigned int val) \ 1471 { \ 1472 unsigned int res, new; \ 1473 \ 1474 res = read_c0_##name(); \ 1475 new = res & ~change; \ 1476 new |= (val & change); \ 1477 write_c0_##name(new); \ 1478 \ 1479 return res; \ 1480 } 1481 1482 #else /* SMTC versions that manage MT scheduling */ 1483 1484 #include <linux/irqflags.h> 1485 1486 /* 1487 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with 1488 * header file recursion. 1489 */ 1490 static inline unsigned int __dmt(void) 1491 { 1492 int res; 1493 1494 __asm__ __volatile__( 1495 " .set push \n" 1496 " .set mips32r2 \n" 1497 " .set noat \n" 1498 " .word 0x41610BC1 # dmt $1 \n" 1499 " ehb \n" 1500 " move %0, $1 \n" 1501 " .set pop \n" 1502 : "=r" (res)); 1503 1504 instruction_hazard(); 1505 1506 return res; 1507 } 1508 1509 #define __VPECONTROL_TE_SHIFT 15 1510 #define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT) 1511 1512 #define __EMT_ENABLE __VPECONTROL_TE 1513 1514 static inline void __emt(unsigned int previous) 1515 { 1516 if ((previous & __EMT_ENABLE)) 1517 __asm__ __volatile__( 1518 " .set mips32r2 \n" 1519 " .word 0x41600be1 # emt \n" 1520 " ehb \n" 1521 " .set mips0 \n"); 1522 } 1523 1524 static inline void __ehb(void) 1525 { 1526 __asm__ __volatile__( 1527 " .set mips32r2 \n" 1528 " ehb \n" " .set mips0 \n"); 1529 } 1530 1531 /* 1532 * Note that local_irq_save/restore affect TC-specific IXMT state, 1533 * not Status.IE as in non-SMTC kernel. 1534 */ 1535 1536 #define __BUILD_SET_C0(name) \ 1537 static inline unsigned int \ 1538 set_c0_##name(unsigned int set) \ 1539 { \ 1540 unsigned int res; \ 1541 unsigned int new; \ 1542 unsigned int omt; \ 1543 unsigned long flags; \ 1544 \ 1545 local_irq_save(flags); \ 1546 omt = __dmt(); \ 1547 res = read_c0_##name(); \ 1548 new = res | set; \ 1549 write_c0_##name(new); \ 1550 __emt(omt); \ 1551 local_irq_restore(flags); \ 1552 \ 1553 return res; \ 1554 } \ 1555 \ 1556 static inline unsigned int \ 1557 clear_c0_##name(unsigned int clear) \ 1558 { \ 1559 unsigned int res; \ 1560 unsigned int new; \ 1561 unsigned int omt; \ 1562 unsigned long flags; \ 1563 \ 1564 local_irq_save(flags); \ 1565 omt = __dmt(); \ 1566 res = read_c0_##name(); \ 1567 new = res & ~clear; \ 1568 write_c0_##name(new); \ 1569 __emt(omt); \ 1570 local_irq_restore(flags); \ 1571 \ 1572 return res; \ 1573 } \ 1574 \ 1575 static inline unsigned int \ 1576 change_c0_##name(unsigned int change, unsigned int newbits) \ 1577 { \ 1578 unsigned int res; \ 1579 unsigned int new; \ 1580 unsigned int omt; \ 1581 unsigned long flags; \ 1582 \ 1583 local_irq_save(flags); \ 1584 \ 1585 omt = __dmt(); \ 1586 res = read_c0_##name(); \ 1587 new = res & ~change; \ 1588 new |= (newbits & change); \ 1589 write_c0_##name(new); \ 1590 __emt(omt); \ 1591 local_irq_restore(flags); \ 1592 \ 1593 return res; \ 1594 } 1595 #endif 1596 1597 __BUILD_SET_C0(status) 1598 __BUILD_SET_C0(cause) 1599 __BUILD_SET_C0(config) 1600 __BUILD_SET_C0(intcontrol) 1601 __BUILD_SET_C0(intctl) 1602 __BUILD_SET_C0(srsmap) 1603 1604 #endif /* !__ASSEMBLY__ */ 1605 1606 #endif /* _ASM_MIPSREGS_H */ 1607