1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 7 * Copyright (C) 2000 Silicon Graphics, Inc. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 12 */ 13 #ifndef _ASM_MIPSREGS_H 14 #define _ASM_MIPSREGS_H 15 16 #include <linux/linkage.h> 17 #include <linux/types.h> 18 #include <asm/hazards.h> 19 #include <asm/war.h> 20 21 /* 22 * The following macros are especially useful for __asm__ 23 * inline assembler. 24 */ 25 #ifndef __STR 26 #define __STR(x) #x 27 #endif 28 #ifndef STR 29 #define STR(x) __STR(x) 30 #endif 31 32 /* 33 * Configure language 34 */ 35 #ifdef __ASSEMBLY__ 36 #define _ULCAST_ 37 #else 38 #define _ULCAST_ (unsigned long) 39 #endif 40 41 /* 42 * Coprocessor 0 register names 43 */ 44 #define CP0_INDEX $0 45 #define CP0_RANDOM $1 46 #define CP0_ENTRYLO0 $2 47 #define CP0_ENTRYLO1 $3 48 #define CP0_CONF $3 49 #define CP0_CONTEXT $4 50 #define CP0_PAGEMASK $5 51 #define CP0_WIRED $6 52 #define CP0_INFO $7 53 #define CP0_BADVADDR $8 54 #define CP0_COUNT $9 55 #define CP0_ENTRYHI $10 56 #define CP0_COMPARE $11 57 #define CP0_STATUS $12 58 #define CP0_CAUSE $13 59 #define CP0_EPC $14 60 #define CP0_PRID $15 61 #define CP0_CONFIG $16 62 #define CP0_LLADDR $17 63 #define CP0_WATCHLO $18 64 #define CP0_WATCHHI $19 65 #define CP0_XCONTEXT $20 66 #define CP0_FRAMEMASK $21 67 #define CP0_DIAGNOSTIC $22 68 #define CP0_DEBUG $23 69 #define CP0_DEPC $24 70 #define CP0_PERFORMANCE $25 71 #define CP0_ECC $26 72 #define CP0_CACHEERR $27 73 #define CP0_TAGLO $28 74 #define CP0_TAGHI $29 75 #define CP0_ERROREPC $30 76 #define CP0_DESAVE $31 77 78 /* 79 * R4640/R4650 cp0 register names. These registers are listed 80 * here only for completeness; without MMU these CPUs are not useable 81 * by Linux. A future ELKS port might take make Linux run on them 82 * though ... 83 */ 84 #define CP0_IBASE $0 85 #define CP0_IBOUND $1 86 #define CP0_DBASE $2 87 #define CP0_DBOUND $3 88 #define CP0_CALG $17 89 #define CP0_IWATCH $18 90 #define CP0_DWATCH $19 91 92 /* 93 * Coprocessor 0 Set 1 register names 94 */ 95 #define CP0_S1_DERRADDR0 $26 96 #define CP0_S1_DERRADDR1 $27 97 #define CP0_S1_INTCONTROL $20 98 99 /* 100 * Coprocessor 0 Set 2 register names 101 */ 102 #define CP0_S2_SRSCTL $12 /* MIPSR2 */ 103 104 /* 105 * Coprocessor 0 Set 3 register names 106 */ 107 #define CP0_S3_SRSMAP $12 /* MIPSR2 */ 108 109 /* 110 * TX39 Series 111 */ 112 #define CP0_TX39_CACHE $7 113 114 115 /* 116 * Values for PageMask register 117 */ 118 #ifdef CONFIG_CPU_VR41XX 119 120 /* Why doesn't stupidity hurt ... */ 121 122 #define PM_1K 0x00000000 123 #define PM_4K 0x00001800 124 #define PM_16K 0x00007800 125 #define PM_64K 0x0001f800 126 #define PM_256K 0x0007f800 127 128 #else 129 130 #define PM_4K 0x00000000 131 #define PM_8K 0x00002000 132 #define PM_16K 0x00006000 133 #define PM_32K 0x0000e000 134 #define PM_64K 0x0001e000 135 #define PM_128K 0x0003e000 136 #define PM_256K 0x0007e000 137 #define PM_512K 0x000fe000 138 #define PM_1M 0x001fe000 139 #define PM_2M 0x003fe000 140 #define PM_4M 0x007fe000 141 #define PM_8M 0x00ffe000 142 #define PM_16M 0x01ffe000 143 #define PM_32M 0x03ffe000 144 #define PM_64M 0x07ffe000 145 #define PM_256M 0x1fffe000 146 #define PM_1G 0x7fffe000 147 148 #endif 149 150 /* 151 * Default page size for a given kernel configuration 152 */ 153 #ifdef CONFIG_PAGE_SIZE_4KB 154 #define PM_DEFAULT_MASK PM_4K 155 #elif defined(CONFIG_PAGE_SIZE_8KB) 156 #define PM_DEFAULT_MASK PM_8K 157 #elif defined(CONFIG_PAGE_SIZE_16KB) 158 #define PM_DEFAULT_MASK PM_16K 159 #elif defined(CONFIG_PAGE_SIZE_32KB) 160 #define PM_DEFAULT_MASK PM_32K 161 #elif defined(CONFIG_PAGE_SIZE_64KB) 162 #define PM_DEFAULT_MASK PM_64K 163 #else 164 #error Bad page size configuration! 165 #endif 166 167 /* 168 * Default huge tlb size for a given kernel configuration 169 */ 170 #ifdef CONFIG_PAGE_SIZE_4KB 171 #define PM_HUGE_MASK PM_1M 172 #elif defined(CONFIG_PAGE_SIZE_8KB) 173 #define PM_HUGE_MASK PM_4M 174 #elif defined(CONFIG_PAGE_SIZE_16KB) 175 #define PM_HUGE_MASK PM_16M 176 #elif defined(CONFIG_PAGE_SIZE_32KB) 177 #define PM_HUGE_MASK PM_64M 178 #elif defined(CONFIG_PAGE_SIZE_64KB) 179 #define PM_HUGE_MASK PM_256M 180 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) 181 #error Bad page size configuration for hugetlbfs! 182 #endif 183 184 /* 185 * Values used for computation of new tlb entries 186 */ 187 #define PL_4K 12 188 #define PL_16K 14 189 #define PL_64K 16 190 #define PL_256K 18 191 #define PL_1M 20 192 #define PL_4M 22 193 #define PL_16M 24 194 #define PL_64M 26 195 #define PL_256M 28 196 197 /* 198 * PageGrain bits 199 */ 200 #define PG_RIE (_ULCAST_(1) << 31) 201 #define PG_XIE (_ULCAST_(1) << 30) 202 #define PG_ELPA (_ULCAST_(1) << 29) 203 #define PG_ESP (_ULCAST_(1) << 28) 204 #define PG_IEC (_ULCAST_(1) << 27) 205 206 /* 207 * R4x00 interrupt enable / cause bits 208 */ 209 #define IE_SW0 (_ULCAST_(1) << 8) 210 #define IE_SW1 (_ULCAST_(1) << 9) 211 #define IE_IRQ0 (_ULCAST_(1) << 10) 212 #define IE_IRQ1 (_ULCAST_(1) << 11) 213 #define IE_IRQ2 (_ULCAST_(1) << 12) 214 #define IE_IRQ3 (_ULCAST_(1) << 13) 215 #define IE_IRQ4 (_ULCAST_(1) << 14) 216 #define IE_IRQ5 (_ULCAST_(1) << 15) 217 218 /* 219 * R4x00 interrupt cause bits 220 */ 221 #define C_SW0 (_ULCAST_(1) << 8) 222 #define C_SW1 (_ULCAST_(1) << 9) 223 #define C_IRQ0 (_ULCAST_(1) << 10) 224 #define C_IRQ1 (_ULCAST_(1) << 11) 225 #define C_IRQ2 (_ULCAST_(1) << 12) 226 #define C_IRQ3 (_ULCAST_(1) << 13) 227 #define C_IRQ4 (_ULCAST_(1) << 14) 228 #define C_IRQ5 (_ULCAST_(1) << 15) 229 230 /* 231 * Bitfields in the R4xx0 cp0 status register 232 */ 233 #define ST0_IE 0x00000001 234 #define ST0_EXL 0x00000002 235 #define ST0_ERL 0x00000004 236 #define ST0_KSU 0x00000018 237 # define KSU_USER 0x00000010 238 # define KSU_SUPERVISOR 0x00000008 239 # define KSU_KERNEL 0x00000000 240 #define ST0_UX 0x00000020 241 #define ST0_SX 0x00000040 242 #define ST0_KX 0x00000080 243 #define ST0_DE 0x00010000 244 #define ST0_CE 0x00020000 245 246 /* 247 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate 248 * cacheops in userspace. This bit exists only on RM7000 and RM9000 249 * processors. 250 */ 251 #define ST0_CO 0x08000000 252 253 /* 254 * Bitfields in the R[23]000 cp0 status register. 255 */ 256 #define ST0_IEC 0x00000001 257 #define ST0_KUC 0x00000002 258 #define ST0_IEP 0x00000004 259 #define ST0_KUP 0x00000008 260 #define ST0_IEO 0x00000010 261 #define ST0_KUO 0x00000020 262 /* bits 6 & 7 are reserved on R[23]000 */ 263 #define ST0_ISC 0x00010000 264 #define ST0_SWC 0x00020000 265 #define ST0_CM 0x00080000 266 267 /* 268 * Bits specific to the R4640/R4650 269 */ 270 #define ST0_UM (_ULCAST_(1) << 4) 271 #define ST0_IL (_ULCAST_(1) << 23) 272 #define ST0_DL (_ULCAST_(1) << 24) 273 274 /* 275 * Enable the MIPS MDMX and DSP ASEs 276 */ 277 #define ST0_MX 0x01000000 278 279 /* 280 * Status register bits available in all MIPS CPUs. 281 */ 282 #define ST0_IM 0x0000ff00 283 #define STATUSB_IP0 8 284 #define STATUSF_IP0 (_ULCAST_(1) << 8) 285 #define STATUSB_IP1 9 286 #define STATUSF_IP1 (_ULCAST_(1) << 9) 287 #define STATUSB_IP2 10 288 #define STATUSF_IP2 (_ULCAST_(1) << 10) 289 #define STATUSB_IP3 11 290 #define STATUSF_IP3 (_ULCAST_(1) << 11) 291 #define STATUSB_IP4 12 292 #define STATUSF_IP4 (_ULCAST_(1) << 12) 293 #define STATUSB_IP5 13 294 #define STATUSF_IP5 (_ULCAST_(1) << 13) 295 #define STATUSB_IP6 14 296 #define STATUSF_IP6 (_ULCAST_(1) << 14) 297 #define STATUSB_IP7 15 298 #define STATUSF_IP7 (_ULCAST_(1) << 15) 299 #define STATUSB_IP8 0 300 #define STATUSF_IP8 (_ULCAST_(1) << 0) 301 #define STATUSB_IP9 1 302 #define STATUSF_IP9 (_ULCAST_(1) << 1) 303 #define STATUSB_IP10 2 304 #define STATUSF_IP10 (_ULCAST_(1) << 2) 305 #define STATUSB_IP11 3 306 #define STATUSF_IP11 (_ULCAST_(1) << 3) 307 #define STATUSB_IP12 4 308 #define STATUSF_IP12 (_ULCAST_(1) << 4) 309 #define STATUSB_IP13 5 310 #define STATUSF_IP13 (_ULCAST_(1) << 5) 311 #define STATUSB_IP14 6 312 #define STATUSF_IP14 (_ULCAST_(1) << 6) 313 #define STATUSB_IP15 7 314 #define STATUSF_IP15 (_ULCAST_(1) << 7) 315 #define ST0_CH 0x00040000 316 #define ST0_NMI 0x00080000 317 #define ST0_SR 0x00100000 318 #define ST0_TS 0x00200000 319 #define ST0_BEV 0x00400000 320 #define ST0_RE 0x02000000 321 #define ST0_FR 0x04000000 322 #define ST0_CU 0xf0000000 323 #define ST0_CU0 0x10000000 324 #define ST0_CU1 0x20000000 325 #define ST0_CU2 0x40000000 326 #define ST0_CU3 0x80000000 327 #define ST0_XX 0x80000000 /* MIPS IV naming */ 328 329 /* 330 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) 331 */ 332 #define INTCTLB_IPFDC 23 333 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC) 334 #define INTCTLB_IPPCI 26 335 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) 336 #define INTCTLB_IPTI 29 337 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) 338 339 /* 340 * Bitfields and bit numbers in the coprocessor 0 cause register. 341 * 342 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 343 */ 344 #define CAUSEB_EXCCODE 2 345 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 346 #define CAUSEB_IP 8 347 #define CAUSEF_IP (_ULCAST_(255) << 8) 348 #define CAUSEB_IP0 8 349 #define CAUSEF_IP0 (_ULCAST_(1) << 8) 350 #define CAUSEB_IP1 9 351 #define CAUSEF_IP1 (_ULCAST_(1) << 9) 352 #define CAUSEB_IP2 10 353 #define CAUSEF_IP2 (_ULCAST_(1) << 10) 354 #define CAUSEB_IP3 11 355 #define CAUSEF_IP3 (_ULCAST_(1) << 11) 356 #define CAUSEB_IP4 12 357 #define CAUSEF_IP4 (_ULCAST_(1) << 12) 358 #define CAUSEB_IP5 13 359 #define CAUSEF_IP5 (_ULCAST_(1) << 13) 360 #define CAUSEB_IP6 14 361 #define CAUSEF_IP6 (_ULCAST_(1) << 14) 362 #define CAUSEB_IP7 15 363 #define CAUSEF_IP7 (_ULCAST_(1) << 15) 364 #define CAUSEB_FDCI 21 365 #define CAUSEF_FDCI (_ULCAST_(1) << 21) 366 #define CAUSEB_IV 23 367 #define CAUSEF_IV (_ULCAST_(1) << 23) 368 #define CAUSEB_PCI 26 369 #define CAUSEF_PCI (_ULCAST_(1) << 26) 370 #define CAUSEB_CE 28 371 #define CAUSEF_CE (_ULCAST_(3) << 28) 372 #define CAUSEB_TI 30 373 #define CAUSEF_TI (_ULCAST_(1) << 30) 374 #define CAUSEB_BD 31 375 #define CAUSEF_BD (_ULCAST_(1) << 31) 376 377 /* 378 * Bits in the coprocessor 0 config register. 379 */ 380 /* Generic bits. */ 381 #define CONF_CM_CACHABLE_NO_WA 0 382 #define CONF_CM_CACHABLE_WA 1 383 #define CONF_CM_UNCACHED 2 384 #define CONF_CM_CACHABLE_NONCOHERENT 3 385 #define CONF_CM_CACHABLE_CE 4 386 #define CONF_CM_CACHABLE_COW 5 387 #define CONF_CM_CACHABLE_CUW 6 388 #define CONF_CM_CACHABLE_ACCELERATED 7 389 #define CONF_CM_CMASK 7 390 #define CONF_BE (_ULCAST_(1) << 15) 391 392 /* Bits common to various processors. */ 393 #define CONF_CU (_ULCAST_(1) << 3) 394 #define CONF_DB (_ULCAST_(1) << 4) 395 #define CONF_IB (_ULCAST_(1) << 5) 396 #define CONF_DC (_ULCAST_(7) << 6) 397 #define CONF_IC (_ULCAST_(7) << 9) 398 #define CONF_EB (_ULCAST_(1) << 13) 399 #define CONF_EM (_ULCAST_(1) << 14) 400 #define CONF_SM (_ULCAST_(1) << 16) 401 #define CONF_SC (_ULCAST_(1) << 17) 402 #define CONF_EW (_ULCAST_(3) << 18) 403 #define CONF_EP (_ULCAST_(15)<< 24) 404 #define CONF_EC (_ULCAST_(7) << 28) 405 #define CONF_CM (_ULCAST_(1) << 31) 406 407 /* Bits specific to the R4xx0. */ 408 #define R4K_CONF_SW (_ULCAST_(1) << 20) 409 #define R4K_CONF_SS (_ULCAST_(1) << 21) 410 #define R4K_CONF_SB (_ULCAST_(3) << 22) 411 412 /* Bits specific to the R5000. */ 413 #define R5K_CONF_SE (_ULCAST_(1) << 12) 414 #define R5K_CONF_SS (_ULCAST_(3) << 20) 415 416 /* Bits specific to the RM7000. */ 417 #define RM7K_CONF_SE (_ULCAST_(1) << 3) 418 #define RM7K_CONF_TE (_ULCAST_(1) << 12) 419 #define RM7K_CONF_CLK (_ULCAST_(1) << 16) 420 #define RM7K_CONF_TC (_ULCAST_(1) << 17) 421 #define RM7K_CONF_SI (_ULCAST_(3) << 20) 422 #define RM7K_CONF_SC (_ULCAST_(1) << 31) 423 424 /* Bits specific to the R10000. */ 425 #define R10K_CONF_DN (_ULCAST_(3) << 3) 426 #define R10K_CONF_CT (_ULCAST_(1) << 5) 427 #define R10K_CONF_PE (_ULCAST_(1) << 6) 428 #define R10K_CONF_PM (_ULCAST_(3) << 7) 429 #define R10K_CONF_EC (_ULCAST_(15)<< 9) 430 #define R10K_CONF_SB (_ULCAST_(1) << 13) 431 #define R10K_CONF_SK (_ULCAST_(1) << 14) 432 #define R10K_CONF_SS (_ULCAST_(7) << 16) 433 #define R10K_CONF_SC (_ULCAST_(7) << 19) 434 #define R10K_CONF_DC (_ULCAST_(7) << 26) 435 #define R10K_CONF_IC (_ULCAST_(7) << 29) 436 437 /* Bits specific to the VR41xx. */ 438 #define VR41_CONF_CS (_ULCAST_(1) << 12) 439 #define VR41_CONF_P4K (_ULCAST_(1) << 13) 440 #define VR41_CONF_BP (_ULCAST_(1) << 16) 441 #define VR41_CONF_M16 (_ULCAST_(1) << 20) 442 #define VR41_CONF_AD (_ULCAST_(1) << 23) 443 444 /* Bits specific to the R30xx. */ 445 #define R30XX_CONF_FDM (_ULCAST_(1) << 19) 446 #define R30XX_CONF_REV (_ULCAST_(1) << 22) 447 #define R30XX_CONF_AC (_ULCAST_(1) << 23) 448 #define R30XX_CONF_RF (_ULCAST_(1) << 24) 449 #define R30XX_CONF_HALT (_ULCAST_(1) << 25) 450 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 451 #define R30XX_CONF_DBR (_ULCAST_(1) << 29) 452 #define R30XX_CONF_SB (_ULCAST_(1) << 30) 453 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 454 455 /* Bits specific to the TX49. */ 456 #define TX49_CONF_DC (_ULCAST_(1) << 16) 457 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 458 #define TX49_CONF_HALT (_ULCAST_(1) << 18) 459 #define TX49_CONF_CWFON (_ULCAST_(1) << 27) 460 461 /* Bits specific to the MIPS32/64 PRA. */ 462 #define MIPS_CONF_MT (_ULCAST_(7) << 7) 463 #define MIPS_CONF_AR (_ULCAST_(7) << 10) 464 #define MIPS_CONF_AT (_ULCAST_(3) << 13) 465 #define MIPS_CONF_M (_ULCAST_(1) << 31) 466 467 /* 468 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 469 */ 470 #define MIPS_CONF1_FP (_ULCAST_(1) << 0) 471 #define MIPS_CONF1_EP (_ULCAST_(1) << 1) 472 #define MIPS_CONF1_CA (_ULCAST_(1) << 2) 473 #define MIPS_CONF1_WR (_ULCAST_(1) << 3) 474 #define MIPS_CONF1_PC (_ULCAST_(1) << 4) 475 #define MIPS_CONF1_MD (_ULCAST_(1) << 5) 476 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 477 #define MIPS_CONF1_DA_SHF 7 478 #define MIPS_CONF1_DA_SZ 3 479 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) 480 #define MIPS_CONF1_DL_SHF 10 481 #define MIPS_CONF1_DL_SZ 3 482 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) 483 #define MIPS_CONF1_DS_SHF 13 484 #define MIPS_CONF1_DS_SZ 3 485 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) 486 #define MIPS_CONF1_IA_SHF 16 487 #define MIPS_CONF1_IA_SZ 3 488 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) 489 #define MIPS_CONF1_IL_SHF 19 490 #define MIPS_CONF1_IL_SZ 3 491 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) 492 #define MIPS_CONF1_IS_SHF 22 493 #define MIPS_CONF1_IS_SZ 3 494 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) 495 #define MIPS_CONF1_TLBS_SHIFT (25) 496 #define MIPS_CONF1_TLBS_SIZE (6) 497 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT) 498 499 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 500 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 501 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 502 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 503 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 504 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 505 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 506 #define MIPS_CONF2_TU (_ULCAST_(7) << 28) 507 508 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 509 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 510 #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 511 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3) 512 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 513 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 514 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 515 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 516 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8) 517 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9) 518 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 519 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 520 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 521 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 522 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 523 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) 524 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17) 525 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18) 526 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21) 527 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 528 #define MIPS_CONF3_PW (_ULCAST_(1) << 24) 529 #define MIPS_CONF3_SC (_ULCAST_(1) << 25) 530 #define MIPS_CONF3_BI (_ULCAST_(1) << 26) 531 #define MIPS_CONF3_BP (_ULCAST_(1) << 27) 532 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28) 533 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29) 534 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30) 535 536 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0) 537 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 538 #define MIPS_CONF4_FTLBSETS_SHIFT (0) 539 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT) 540 #define MIPS_CONF4_FTLBWAYS_SHIFT (4) 541 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT) 542 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8) 543 /* bits 10:8 in FTLB-only configurations */ 544 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) 545 /* bits 12:8 in VTLB-FTLB only configurations */ 546 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) 547 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 548 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 549 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14) 550 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14) 551 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16) 552 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24) 553 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT) 554 #define MIPS_CONF4_AE (_ULCAST_(1) << 28) 555 #define MIPS_CONF4_IE (_ULCAST_(3) << 29) 556 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29) 557 558 #define MIPS_CONF5_NF (_ULCAST_(1) << 0) 559 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2) 560 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3) 561 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4) 562 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5) 563 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8) 564 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9) 565 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) 566 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28) 567 #define MIPS_CONF5_CV (_ULCAST_(1) << 29) 568 #define MIPS_CONF5_K (_ULCAST_(1) << 30) 569 570 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 571 /* proAptiv FTLB on/off bit */ 572 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) 573 /* FTLB probability bits */ 574 #define MIPS_CONF6_FTLBP_SHIFT (16) 575 576 #define MIPS_CONF7_WII (_ULCAST_(1) << 31) 577 578 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 579 580 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10) 581 #define MIPS_CONF7_AR (_ULCAST_(1) << 16) 582 583 /* MAAR bit definitions */ 584 #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12) 585 #define MIPS_MAAR_ADDR_SHIFT 12 586 #define MIPS_MAAR_S (_ULCAST_(1) << 1) 587 #define MIPS_MAAR_V (_ULCAST_(1) << 0) 588 589 /* EntryHI bit definition */ 590 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) 591 592 /* CMGCRBase bit definitions */ 593 #define MIPS_CMGCRB_BASE 11 594 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) 595 596 /* 597 * Bits in the MIPS32 Memory Segmentation registers. 598 */ 599 #define MIPS_SEGCFG_PA_SHIFT 9 600 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT) 601 #define MIPS_SEGCFG_AM_SHIFT 4 602 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT) 603 #define MIPS_SEGCFG_EU_SHIFT 3 604 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT) 605 #define MIPS_SEGCFG_C_SHIFT 0 606 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT) 607 608 #define MIPS_SEGCFG_UUSK _ULCAST_(7) 609 #define MIPS_SEGCFG_USK _ULCAST_(5) 610 #define MIPS_SEGCFG_MUSUK _ULCAST_(4) 611 #define MIPS_SEGCFG_MUSK _ULCAST_(3) 612 #define MIPS_SEGCFG_MSK _ULCAST_(2) 613 #define MIPS_SEGCFG_MK _ULCAST_(1) 614 #define MIPS_SEGCFG_UK _ULCAST_(0) 615 616 #define MIPS_PWFIELD_GDI_SHIFT 24 617 #define MIPS_PWFIELD_GDI_MASK 0x3f000000 618 #define MIPS_PWFIELD_UDI_SHIFT 18 619 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000 620 #define MIPS_PWFIELD_MDI_SHIFT 12 621 #define MIPS_PWFIELD_MDI_MASK 0x0003f000 622 #define MIPS_PWFIELD_PTI_SHIFT 6 623 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0 624 #define MIPS_PWFIELD_PTEI_SHIFT 0 625 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f 626 627 #define MIPS_PWSIZE_GDW_SHIFT 24 628 #define MIPS_PWSIZE_GDW_MASK 0x3f000000 629 #define MIPS_PWSIZE_UDW_SHIFT 18 630 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000 631 #define MIPS_PWSIZE_MDW_SHIFT 12 632 #define MIPS_PWSIZE_MDW_MASK 0x0003f000 633 #define MIPS_PWSIZE_PTW_SHIFT 6 634 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0 635 #define MIPS_PWSIZE_PTEW_SHIFT 0 636 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f 637 638 #define MIPS_PWCTL_PWEN_SHIFT 31 639 #define MIPS_PWCTL_PWEN_MASK 0x80000000 640 #define MIPS_PWCTL_DPH_SHIFT 7 641 #define MIPS_PWCTL_DPH_MASK 0x00000080 642 #define MIPS_PWCTL_HUGEPG_SHIFT 6 643 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060 644 #define MIPS_PWCTL_PSN_SHIFT 0 645 #define MIPS_PWCTL_PSN_MASK 0x0000003f 646 647 /* CDMMBase register bit definitions */ 648 #define MIPS_CDMMBASE_SIZE_SHIFT 0 649 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT) 650 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9) 651 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10) 652 #define MIPS_CDMMBASE_ADDR_SHIFT 11 653 #define MIPS_CDMMBASE_ADDR_START 15 654 655 /* 656 * Bitfields in the TX39 family CP0 Configuration Register 3 657 */ 658 #define TX39_CONF_ICS_SHIFT 19 659 #define TX39_CONF_ICS_MASK 0x00380000 660 #define TX39_CONF_ICS_1KB 0x00000000 661 #define TX39_CONF_ICS_2KB 0x00080000 662 #define TX39_CONF_ICS_4KB 0x00100000 663 #define TX39_CONF_ICS_8KB 0x00180000 664 #define TX39_CONF_ICS_16KB 0x00200000 665 666 #define TX39_CONF_DCS_SHIFT 16 667 #define TX39_CONF_DCS_MASK 0x00070000 668 #define TX39_CONF_DCS_1KB 0x00000000 669 #define TX39_CONF_DCS_2KB 0x00010000 670 #define TX39_CONF_DCS_4KB 0x00020000 671 #define TX39_CONF_DCS_8KB 0x00030000 672 #define TX39_CONF_DCS_16KB 0x00040000 673 674 #define TX39_CONF_CWFON 0x00004000 675 #define TX39_CONF_WBON 0x00002000 676 #define TX39_CONF_RF_SHIFT 10 677 #define TX39_CONF_RF_MASK 0x00000c00 678 #define TX39_CONF_DOZE 0x00000200 679 #define TX39_CONF_HALT 0x00000100 680 #define TX39_CONF_LOCK 0x00000080 681 #define TX39_CONF_ICE 0x00000020 682 #define TX39_CONF_DCE 0x00000010 683 #define TX39_CONF_IRSIZE_SHIFT 2 684 #define TX39_CONF_IRSIZE_MASK 0x0000000c 685 #define TX39_CONF_DRSIZE_SHIFT 0 686 #define TX39_CONF_DRSIZE_MASK 0x00000003 687 688 689 /* 690 * Coprocessor 1 (FPU) register names 691 */ 692 #define CP1_REVISION $0 693 #define CP1_STATUS $31 694 695 696 /* 697 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 698 */ 699 #define MIPS_FPIR_S (_ULCAST_(1) << 16) 700 #define MIPS_FPIR_D (_ULCAST_(1) << 17) 701 #define MIPS_FPIR_PS (_ULCAST_(1) << 18) 702 #define MIPS_FPIR_3D (_ULCAST_(1) << 19) 703 #define MIPS_FPIR_W (_ULCAST_(1) << 20) 704 #define MIPS_FPIR_L (_ULCAST_(1) << 21) 705 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 706 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29) 707 708 /* 709 * FPU Status Register Values 710 */ 711 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ 712 #define FPU_CSR_COND 0x00800000 /* $fcc0 */ 713 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ 714 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ 715 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ 716 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ 717 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ 718 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ 719 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ 720 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 721 722 /* 723 * Bits 18 - 20 of the FPU Status Register will be read as 0, 724 * and should be written as zero. 725 */ 726 #define FPU_CSR_RSVD 0x001c0000 727 728 /* 729 * X the exception cause indicator 730 * E the exception enable 731 * S the sticky/flag bit 732 */ 733 #define FPU_CSR_ALL_X 0x0003f000 734 #define FPU_CSR_UNI_X 0x00020000 735 #define FPU_CSR_INV_X 0x00010000 736 #define FPU_CSR_DIV_X 0x00008000 737 #define FPU_CSR_OVF_X 0x00004000 738 #define FPU_CSR_UDF_X 0x00002000 739 #define FPU_CSR_INE_X 0x00001000 740 741 #define FPU_CSR_ALL_E 0x00000f80 742 #define FPU_CSR_INV_E 0x00000800 743 #define FPU_CSR_DIV_E 0x00000400 744 #define FPU_CSR_OVF_E 0x00000200 745 #define FPU_CSR_UDF_E 0x00000100 746 #define FPU_CSR_INE_E 0x00000080 747 748 #define FPU_CSR_ALL_S 0x0000007c 749 #define FPU_CSR_INV_S 0x00000040 750 #define FPU_CSR_DIV_S 0x00000020 751 #define FPU_CSR_OVF_S 0x00000010 752 #define FPU_CSR_UDF_S 0x00000008 753 #define FPU_CSR_INE_S 0x00000004 754 755 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ 756 #define FPU_CSR_RM 0x00000003 757 #define FPU_CSR_RN 0x0 /* nearest */ 758 #define FPU_CSR_RZ 0x1 /* towards zero */ 759 #define FPU_CSR_RU 0x2 /* towards +Infinity */ 760 #define FPU_CSR_RD 0x3 /* towards -Infinity */ 761 762 763 #ifndef __ASSEMBLY__ 764 765 /* 766 * Macros for handling the ISA mode bit for MIPS16 and microMIPS. 767 */ 768 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \ 769 defined(CONFIG_SYS_SUPPORTS_MICROMIPS) 770 #define get_isa16_mode(x) ((x) & 0x1) 771 #define msk_isa16_mode(x) ((x) & ~0x1) 772 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0) 773 #else 774 #define get_isa16_mode(x) 0 775 #define msk_isa16_mode(x) (x) 776 #define set_isa16_mode(x) do { } while(0) 777 #endif 778 779 /* 780 * microMIPS instructions can be 16-bit or 32-bit in length. This 781 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. 782 */ 783 static inline int mm_insn_16bit(u16 insn) 784 { 785 u16 opcode = (insn >> 10) & 0x7; 786 787 return (opcode >= 1 && opcode <= 3) ? 1 : 0; 788 } 789 790 /* 791 * TLB Invalidate Flush 792 */ 793 static inline void tlbinvf(void) 794 { 795 __asm__ __volatile__( 796 ".set push\n\t" 797 ".set noreorder\n\t" 798 ".word 0x42000004\n\t" /* tlbinvf */ 799 ".set pop"); 800 } 801 802 803 /* 804 * Functions to access the R10000 performance counters. These are basically 805 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 806 * performance counter number encoded into bits 1 ... 5 of the instruction. 807 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware 808 * disassembler these will look like an access to sel 0 or 1. 809 */ 810 #define read_r10k_perf_cntr(counter) \ 811 ({ \ 812 unsigned int __res; \ 813 __asm__ __volatile__( \ 814 "mfpc\t%0, %1" \ 815 : "=r" (__res) \ 816 : "i" (counter)); \ 817 \ 818 __res; \ 819 }) 820 821 #define write_r10k_perf_cntr(counter,val) \ 822 do { \ 823 __asm__ __volatile__( \ 824 "mtpc\t%0, %1" \ 825 : \ 826 : "r" (val), "i" (counter)); \ 827 } while (0) 828 829 #define read_r10k_perf_event(counter) \ 830 ({ \ 831 unsigned int __res; \ 832 __asm__ __volatile__( \ 833 "mfps\t%0, %1" \ 834 : "=r" (__res) \ 835 : "i" (counter)); \ 836 \ 837 __res; \ 838 }) 839 840 #define write_r10k_perf_cntl(counter,val) \ 841 do { \ 842 __asm__ __volatile__( \ 843 "mtps\t%0, %1" \ 844 : \ 845 : "r" (val), "i" (counter)); \ 846 } while (0) 847 848 849 /* 850 * Macros to access the system control coprocessor 851 */ 852 853 #define __read_32bit_c0_register(source, sel) \ 854 ({ int __res; \ 855 if (sel == 0) \ 856 __asm__ __volatile__( \ 857 "mfc0\t%0, " #source "\n\t" \ 858 : "=r" (__res)); \ 859 else \ 860 __asm__ __volatile__( \ 861 ".set\tmips32\n\t" \ 862 "mfc0\t%0, " #source ", " #sel "\n\t" \ 863 ".set\tmips0\n\t" \ 864 : "=r" (__res)); \ 865 __res; \ 866 }) 867 868 #define __read_64bit_c0_register(source, sel) \ 869 ({ unsigned long long __res; \ 870 if (sizeof(unsigned long) == 4) \ 871 __res = __read_64bit_c0_split(source, sel); \ 872 else if (sel == 0) \ 873 __asm__ __volatile__( \ 874 ".set\tmips3\n\t" \ 875 "dmfc0\t%0, " #source "\n\t" \ 876 ".set\tmips0" \ 877 : "=r" (__res)); \ 878 else \ 879 __asm__ __volatile__( \ 880 ".set\tmips64\n\t" \ 881 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 882 ".set\tmips0" \ 883 : "=r" (__res)); \ 884 __res; \ 885 }) 886 887 #define __write_32bit_c0_register(register, sel, value) \ 888 do { \ 889 if (sel == 0) \ 890 __asm__ __volatile__( \ 891 "mtc0\t%z0, " #register "\n\t" \ 892 : : "Jr" ((unsigned int)(value))); \ 893 else \ 894 __asm__ __volatile__( \ 895 ".set\tmips32\n\t" \ 896 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 897 ".set\tmips0" \ 898 : : "Jr" ((unsigned int)(value))); \ 899 } while (0) 900 901 #define __write_64bit_c0_register(register, sel, value) \ 902 do { \ 903 if (sizeof(unsigned long) == 4) \ 904 __write_64bit_c0_split(register, sel, value); \ 905 else if (sel == 0) \ 906 __asm__ __volatile__( \ 907 ".set\tmips3\n\t" \ 908 "dmtc0\t%z0, " #register "\n\t" \ 909 ".set\tmips0" \ 910 : : "Jr" (value)); \ 911 else \ 912 __asm__ __volatile__( \ 913 ".set\tmips64\n\t" \ 914 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 915 ".set\tmips0" \ 916 : : "Jr" (value)); \ 917 } while (0) 918 919 #define __read_ulong_c0_register(reg, sel) \ 920 ((sizeof(unsigned long) == 4) ? \ 921 (unsigned long) __read_32bit_c0_register(reg, sel) : \ 922 (unsigned long) __read_64bit_c0_register(reg, sel)) 923 924 #define __write_ulong_c0_register(reg, sel, val) \ 925 do { \ 926 if (sizeof(unsigned long) == 4) \ 927 __write_32bit_c0_register(reg, sel, val); \ 928 else \ 929 __write_64bit_c0_register(reg, sel, val); \ 930 } while (0) 931 932 /* 933 * On RM7000/RM9000 these are uses to access cop0 set 1 registers 934 */ 935 #define __read_32bit_c0_ctrl_register(source) \ 936 ({ int __res; \ 937 __asm__ __volatile__( \ 938 "cfc0\t%0, " #source "\n\t" \ 939 : "=r" (__res)); \ 940 __res; \ 941 }) 942 943 #define __write_32bit_c0_ctrl_register(register, value) \ 944 do { \ 945 __asm__ __volatile__( \ 946 "ctc0\t%z0, " #register "\n\t" \ 947 : : "Jr" ((unsigned int)(value))); \ 948 } while (0) 949 950 /* 951 * These versions are only needed for systems with more than 38 bits of 952 * physical address space running the 32-bit kernel. That's none atm :-) 953 */ 954 #define __read_64bit_c0_split(source, sel) \ 955 ({ \ 956 unsigned long long __val; \ 957 unsigned long __flags; \ 958 \ 959 local_irq_save(__flags); \ 960 if (sel == 0) \ 961 __asm__ __volatile__( \ 962 ".set\tmips64\n\t" \ 963 "dmfc0\t%M0, " #source "\n\t" \ 964 "dsll\t%L0, %M0, 32\n\t" \ 965 "dsra\t%M0, %M0, 32\n\t" \ 966 "dsra\t%L0, %L0, 32\n\t" \ 967 ".set\tmips0" \ 968 : "=r" (__val)); \ 969 else \ 970 __asm__ __volatile__( \ 971 ".set\tmips64\n\t" \ 972 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 973 "dsll\t%L0, %M0, 32\n\t" \ 974 "dsra\t%M0, %M0, 32\n\t" \ 975 "dsra\t%L0, %L0, 32\n\t" \ 976 ".set\tmips0" \ 977 : "=r" (__val)); \ 978 local_irq_restore(__flags); \ 979 \ 980 __val; \ 981 }) 982 983 #define __write_64bit_c0_split(source, sel, val) \ 984 do { \ 985 unsigned long __flags; \ 986 \ 987 local_irq_save(__flags); \ 988 if (sel == 0) \ 989 __asm__ __volatile__( \ 990 ".set\tmips64\n\t" \ 991 "dsll\t%L0, %L0, 32\n\t" \ 992 "dsrl\t%L0, %L0, 32\n\t" \ 993 "dsll\t%M0, %M0, 32\n\t" \ 994 "or\t%L0, %L0, %M0\n\t" \ 995 "dmtc0\t%L0, " #source "\n\t" \ 996 ".set\tmips0" \ 997 : : "r" (val)); \ 998 else \ 999 __asm__ __volatile__( \ 1000 ".set\tmips64\n\t" \ 1001 "dsll\t%L0, %L0, 32\n\t" \ 1002 "dsrl\t%L0, %L0, 32\n\t" \ 1003 "dsll\t%M0, %M0, 32\n\t" \ 1004 "or\t%L0, %L0, %M0\n\t" \ 1005 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 1006 ".set\tmips0" \ 1007 : : "r" (val)); \ 1008 local_irq_restore(__flags); \ 1009 } while (0) 1010 1011 #define __readx_32bit_c0_register(source) \ 1012 ({ \ 1013 unsigned int __res; \ 1014 \ 1015 __asm__ __volatile__( \ 1016 " .set push \n" \ 1017 " .set noat \n" \ 1018 " .set mips32r2 \n" \ 1019 " .insn \n" \ 1020 " # mfhc0 $1, %1 \n" \ 1021 " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \ 1022 " move %0, $1 \n" \ 1023 " .set pop \n" \ 1024 : "=r" (__res) \ 1025 : "i" (source)); \ 1026 __res; \ 1027 }) 1028 1029 #define __writex_32bit_c0_register(register, value) \ 1030 do { \ 1031 __asm__ __volatile__( \ 1032 " .set push \n" \ 1033 " .set noat \n" \ 1034 " .set mips32r2 \n" \ 1035 " move $1, %0 \n" \ 1036 " # mthc0 $1, %1 \n" \ 1037 " .insn \n" \ 1038 " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \ 1039 " .set pop \n" \ 1040 : \ 1041 : "r" (value), "i" (register)); \ 1042 } while (0) 1043 1044 #define read_c0_index() __read_32bit_c0_register($0, 0) 1045 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 1046 1047 #define read_c0_random() __read_32bit_c0_register($1, 0) 1048 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 1049 1050 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 1051 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 1052 1053 #define readx_c0_entrylo0() __readx_32bit_c0_register(2) 1054 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val) 1055 1056 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 1057 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 1058 1059 #define readx_c0_entrylo1() __readx_32bit_c0_register(3) 1060 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val) 1061 1062 #define read_c0_conf() __read_32bit_c0_register($3, 0) 1063 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 1064 1065 #define read_c0_context() __read_ulong_c0_register($4, 0) 1066 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 1067 1068 #define read_c0_userlocal() __read_ulong_c0_register($4, 2) 1069 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 1070 1071 #define read_c0_pagemask() __read_32bit_c0_register($5, 0) 1072 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 1073 1074 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1) 1075 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) 1076 1077 #define read_c0_wired() __read_32bit_c0_register($6, 0) 1078 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 1079 1080 #define read_c0_info() __read_32bit_c0_register($7, 0) 1081 1082 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 1083 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 1084 1085 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 1086 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) 1087 1088 #define read_c0_count() __read_32bit_c0_register($9, 0) 1089 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 1090 1091 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ 1092 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 1093 1094 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ 1095 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 1096 1097 #define read_c0_entryhi() __read_ulong_c0_register($10, 0) 1098 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 1099 1100 #define read_c0_compare() __read_32bit_c0_register($11, 0) 1101 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 1102 1103 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ 1104 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 1105 1106 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ 1107 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 1108 1109 #define read_c0_status() __read_32bit_c0_register($12, 0) 1110 1111 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 1112 1113 #define read_c0_cause() __read_32bit_c0_register($13, 0) 1114 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 1115 1116 #define read_c0_epc() __read_ulong_c0_register($14, 0) 1117 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 1118 1119 #define read_c0_prid() __read_32bit_c0_register($15, 0) 1120 1121 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3) 1122 1123 #define read_c0_config() __read_32bit_c0_register($16, 0) 1124 #define read_c0_config1() __read_32bit_c0_register($16, 1) 1125 #define read_c0_config2() __read_32bit_c0_register($16, 2) 1126 #define read_c0_config3() __read_32bit_c0_register($16, 3) 1127 #define read_c0_config4() __read_32bit_c0_register($16, 4) 1128 #define read_c0_config5() __read_32bit_c0_register($16, 5) 1129 #define read_c0_config6() __read_32bit_c0_register($16, 6) 1130 #define read_c0_config7() __read_32bit_c0_register($16, 7) 1131 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 1132 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 1133 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 1134 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 1135 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) 1136 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) 1137 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 1138 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 1139 1140 #define read_c0_lladdr() __read_ulong_c0_register($17, 0) 1141 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val) 1142 #define read_c0_maar() __read_ulong_c0_register($17, 1) 1143 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val) 1144 #define read_c0_maari() __read_32bit_c0_register($17, 2) 1145 #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val) 1146 1147 /* 1148 * The WatchLo register. There may be up to 8 of them. 1149 */ 1150 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 1151 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 1152 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 1153 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 1154 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 1155 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 1156 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 1157 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 1158 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 1159 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 1160 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 1161 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 1162 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 1163 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 1164 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 1165 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 1166 1167 /* 1168 * The WatchHi register. There may be up to 8 of them. 1169 */ 1170 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 1171 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 1172 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 1173 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 1174 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 1175 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 1176 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 1177 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 1178 1179 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 1180 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 1181 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 1182 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 1183 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 1184 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 1185 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 1186 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 1187 1188 #define read_c0_xcontext() __read_ulong_c0_register($20, 0) 1189 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 1190 1191 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) 1192 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 1193 1194 #define read_c0_framemask() __read_32bit_c0_register($21, 0) 1195 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 1196 1197 #define read_c0_diag() __read_32bit_c0_register($22, 0) 1198 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 1199 1200 #define read_c0_diag1() __read_32bit_c0_register($22, 1) 1201 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) 1202 1203 #define read_c0_diag2() __read_32bit_c0_register($22, 2) 1204 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) 1205 1206 #define read_c0_diag3() __read_32bit_c0_register($22, 3) 1207 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) 1208 1209 #define read_c0_diag4() __read_32bit_c0_register($22, 4) 1210 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) 1211 1212 #define read_c0_diag5() __read_32bit_c0_register($22, 5) 1213 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) 1214 1215 #define read_c0_debug() __read_32bit_c0_register($23, 0) 1216 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 1217 1218 #define read_c0_depc() __read_ulong_c0_register($24, 0) 1219 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 1220 1221 /* 1222 * MIPS32 / MIPS64 performance counters 1223 */ 1224 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 1225 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 1226 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 1227 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 1228 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) 1229 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) 1230 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 1231 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 1232 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 1233 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 1234 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) 1235 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) 1236 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 1237 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 1238 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 1239 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 1240 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) 1241 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) 1242 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 1243 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 1244 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 1245 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 1246 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) 1247 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) 1248 1249 #define read_c0_ecc() __read_32bit_c0_register($26, 0) 1250 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 1251 1252 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 1253 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 1254 1255 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 1256 1257 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 1258 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 1259 1260 #define read_c0_taglo() __read_32bit_c0_register($28, 0) 1261 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 1262 1263 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) 1264 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) 1265 1266 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3) 1267 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) 1268 1269 #define read_c0_staglo() __read_32bit_c0_register($28, 4) 1270 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) 1271 1272 #define read_c0_taghi() __read_32bit_c0_register($29, 0) 1273 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 1274 1275 #define read_c0_errorepc() __read_ulong_c0_register($30, 0) 1276 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 1277 1278 /* MIPSR2 */ 1279 #define read_c0_hwrena() __read_32bit_c0_register($7, 0) 1280 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 1281 1282 #define read_c0_intctl() __read_32bit_c0_register($12, 1) 1283 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) 1284 1285 #define read_c0_srsctl() __read_32bit_c0_register($12, 2) 1286 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) 1287 1288 #define read_c0_srsmap() __read_32bit_c0_register($12, 3) 1289 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 1290 1291 #define read_c0_ebase() __read_32bit_c0_register($15, 1) 1292 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1293 1294 #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2) 1295 #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val) 1296 1297 /* MIPSR3 */ 1298 #define read_c0_segctl0() __read_32bit_c0_register($5, 2) 1299 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val) 1300 1301 #define read_c0_segctl1() __read_32bit_c0_register($5, 3) 1302 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val) 1303 1304 #define read_c0_segctl2() __read_32bit_c0_register($5, 4) 1305 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val) 1306 1307 /* Hardware Page Table Walker */ 1308 #define read_c0_pwbase() __read_ulong_c0_register($5, 5) 1309 #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val) 1310 1311 #define read_c0_pwfield() __read_ulong_c0_register($5, 6) 1312 #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val) 1313 1314 #define read_c0_pwsize() __read_ulong_c0_register($5, 7) 1315 #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val) 1316 1317 #define read_c0_pwctl() __read_32bit_c0_register($6, 6) 1318 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val) 1319 1320 /* Cavium OCTEON (cnMIPS) */ 1321 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1322 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) 1323 1324 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) 1325 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) 1326 1327 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) 1328 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) 1329 /* 1330 * The cacheerr registers are not standardized. On OCTEON, they are 1331 * 64 bits wide. 1332 */ 1333 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) 1334 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) 1335 1336 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) 1337 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) 1338 1339 /* BMIPS3300 */ 1340 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0) 1341 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) 1342 1343 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4) 1344 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) 1345 1346 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) 1347 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) 1348 1349 /* BMIPS43xx */ 1350 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) 1351 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) 1352 1353 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2) 1354 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) 1355 1356 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3) 1357 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) 1358 1359 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5) 1360 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) 1361 1362 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6) 1363 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) 1364 1365 /* BMIPS5000 */ 1366 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0) 1367 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) 1368 1369 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1) 1370 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) 1371 1372 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2) 1373 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) 1374 1375 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3) 1376 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) 1377 1378 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4) 1379 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) 1380 1381 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7) 1382 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) 1383 1384 /* 1385 * Macros to access the floating point coprocessor control registers 1386 */ 1387 #define _read_32bit_cp1_register(source, gas_hardfloat) \ 1388 ({ \ 1389 int __res; \ 1390 \ 1391 __asm__ __volatile__( \ 1392 " .set push \n" \ 1393 " .set reorder \n" \ 1394 " # gas fails to assemble cfc1 for some archs, \n" \ 1395 " # like Octeon. \n" \ 1396 " .set mips1 \n" \ 1397 " "STR(gas_hardfloat)" \n" \ 1398 " cfc1 %0,"STR(source)" \n" \ 1399 " .set pop \n" \ 1400 : "=r" (__res)); \ 1401 __res; \ 1402 }) 1403 1404 #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \ 1405 do { \ 1406 __asm__ __volatile__( \ 1407 " .set push \n" \ 1408 " .set reorder \n" \ 1409 " "STR(gas_hardfloat)" \n" \ 1410 " ctc1 %0,"STR(dest)" \n" \ 1411 " .set pop \n" \ 1412 : : "r" (val)); \ 1413 } while (0) 1414 1415 #ifdef GAS_HAS_SET_HARDFLOAT 1416 #define read_32bit_cp1_register(source) \ 1417 _read_32bit_cp1_register(source, .set hardfloat) 1418 #define write_32bit_cp1_register(dest, val) \ 1419 _write_32bit_cp1_register(dest, val, .set hardfloat) 1420 #else 1421 #define read_32bit_cp1_register(source) \ 1422 _read_32bit_cp1_register(source, ) 1423 #define write_32bit_cp1_register(dest, val) \ 1424 _write_32bit_cp1_register(dest, val, ) 1425 #endif 1426 1427 #ifdef HAVE_AS_DSP 1428 #define rddsp(mask) \ 1429 ({ \ 1430 unsigned int __dspctl; \ 1431 \ 1432 __asm__ __volatile__( \ 1433 " .set push \n" \ 1434 " .set dsp \n" \ 1435 " rddsp %0, %x1 \n" \ 1436 " .set pop \n" \ 1437 : "=r" (__dspctl) \ 1438 : "i" (mask)); \ 1439 __dspctl; \ 1440 }) 1441 1442 #define wrdsp(val, mask) \ 1443 do { \ 1444 __asm__ __volatile__( \ 1445 " .set push \n" \ 1446 " .set dsp \n" \ 1447 " wrdsp %0, %x1 \n" \ 1448 " .set pop \n" \ 1449 : \ 1450 : "r" (val), "i" (mask)); \ 1451 } while (0) 1452 1453 #define mflo0() \ 1454 ({ \ 1455 long mflo0; \ 1456 __asm__( \ 1457 " .set push \n" \ 1458 " .set dsp \n" \ 1459 " mflo %0, $ac0 \n" \ 1460 " .set pop \n" \ 1461 : "=r" (mflo0)); \ 1462 mflo0; \ 1463 }) 1464 1465 #define mflo1() \ 1466 ({ \ 1467 long mflo1; \ 1468 __asm__( \ 1469 " .set push \n" \ 1470 " .set dsp \n" \ 1471 " mflo %0, $ac1 \n" \ 1472 " .set pop \n" \ 1473 : "=r" (mflo1)); \ 1474 mflo1; \ 1475 }) 1476 1477 #define mflo2() \ 1478 ({ \ 1479 long mflo2; \ 1480 __asm__( \ 1481 " .set push \n" \ 1482 " .set dsp \n" \ 1483 " mflo %0, $ac2 \n" \ 1484 " .set pop \n" \ 1485 : "=r" (mflo2)); \ 1486 mflo2; \ 1487 }) 1488 1489 #define mflo3() \ 1490 ({ \ 1491 long mflo3; \ 1492 __asm__( \ 1493 " .set push \n" \ 1494 " .set dsp \n" \ 1495 " mflo %0, $ac3 \n" \ 1496 " .set pop \n" \ 1497 : "=r" (mflo3)); \ 1498 mflo3; \ 1499 }) 1500 1501 #define mfhi0() \ 1502 ({ \ 1503 long mfhi0; \ 1504 __asm__( \ 1505 " .set push \n" \ 1506 " .set dsp \n" \ 1507 " mfhi %0, $ac0 \n" \ 1508 " .set pop \n" \ 1509 : "=r" (mfhi0)); \ 1510 mfhi0; \ 1511 }) 1512 1513 #define mfhi1() \ 1514 ({ \ 1515 long mfhi1; \ 1516 __asm__( \ 1517 " .set push \n" \ 1518 " .set dsp \n" \ 1519 " mfhi %0, $ac1 \n" \ 1520 " .set pop \n" \ 1521 : "=r" (mfhi1)); \ 1522 mfhi1; \ 1523 }) 1524 1525 #define mfhi2() \ 1526 ({ \ 1527 long mfhi2; \ 1528 __asm__( \ 1529 " .set push \n" \ 1530 " .set dsp \n" \ 1531 " mfhi %0, $ac2 \n" \ 1532 " .set pop \n" \ 1533 : "=r" (mfhi2)); \ 1534 mfhi2; \ 1535 }) 1536 1537 #define mfhi3() \ 1538 ({ \ 1539 long mfhi3; \ 1540 __asm__( \ 1541 " .set push \n" \ 1542 " .set dsp \n" \ 1543 " mfhi %0, $ac3 \n" \ 1544 " .set pop \n" \ 1545 : "=r" (mfhi3)); \ 1546 mfhi3; \ 1547 }) 1548 1549 1550 #define mtlo0(x) \ 1551 ({ \ 1552 __asm__( \ 1553 " .set push \n" \ 1554 " .set dsp \n" \ 1555 " mtlo %0, $ac0 \n" \ 1556 " .set pop \n" \ 1557 : \ 1558 : "r" (x)); \ 1559 }) 1560 1561 #define mtlo1(x) \ 1562 ({ \ 1563 __asm__( \ 1564 " .set push \n" \ 1565 " .set dsp \n" \ 1566 " mtlo %0, $ac1 \n" \ 1567 " .set pop \n" \ 1568 : \ 1569 : "r" (x)); \ 1570 }) 1571 1572 #define mtlo2(x) \ 1573 ({ \ 1574 __asm__( \ 1575 " .set push \n" \ 1576 " .set dsp \n" \ 1577 " mtlo %0, $ac2 \n" \ 1578 " .set pop \n" \ 1579 : \ 1580 : "r" (x)); \ 1581 }) 1582 1583 #define mtlo3(x) \ 1584 ({ \ 1585 __asm__( \ 1586 " .set push \n" \ 1587 " .set dsp \n" \ 1588 " mtlo %0, $ac3 \n" \ 1589 " .set pop \n" \ 1590 : \ 1591 : "r" (x)); \ 1592 }) 1593 1594 #define mthi0(x) \ 1595 ({ \ 1596 __asm__( \ 1597 " .set push \n" \ 1598 " .set dsp \n" \ 1599 " mthi %0, $ac0 \n" \ 1600 " .set pop \n" \ 1601 : \ 1602 : "r" (x)); \ 1603 }) 1604 1605 #define mthi1(x) \ 1606 ({ \ 1607 __asm__( \ 1608 " .set push \n" \ 1609 " .set dsp \n" \ 1610 " mthi %0, $ac1 \n" \ 1611 " .set pop \n" \ 1612 : \ 1613 : "r" (x)); \ 1614 }) 1615 1616 #define mthi2(x) \ 1617 ({ \ 1618 __asm__( \ 1619 " .set push \n" \ 1620 " .set dsp \n" \ 1621 " mthi %0, $ac2 \n" \ 1622 " .set pop \n" \ 1623 : \ 1624 : "r" (x)); \ 1625 }) 1626 1627 #define mthi3(x) \ 1628 ({ \ 1629 __asm__( \ 1630 " .set push \n" \ 1631 " .set dsp \n" \ 1632 " mthi %0, $ac3 \n" \ 1633 " .set pop \n" \ 1634 : \ 1635 : "r" (x)); \ 1636 }) 1637 1638 #else 1639 1640 #ifdef CONFIG_CPU_MICROMIPS 1641 #define rddsp(mask) \ 1642 ({ \ 1643 unsigned int __res; \ 1644 \ 1645 __asm__ __volatile__( \ 1646 " .set push \n" \ 1647 " .set noat \n" \ 1648 " # rddsp $1, %x1 \n" \ 1649 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ 1650 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ 1651 " move %0, $1 \n" \ 1652 " .set pop \n" \ 1653 : "=r" (__res) \ 1654 : "i" (mask)); \ 1655 __res; \ 1656 }) 1657 1658 #define wrdsp(val, mask) \ 1659 do { \ 1660 __asm__ __volatile__( \ 1661 " .set push \n" \ 1662 " .set noat \n" \ 1663 " move $1, %0 \n" \ 1664 " # wrdsp $1, %x1 \n" \ 1665 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ 1666 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ 1667 " .set pop \n" \ 1668 : \ 1669 : "r" (val), "i" (mask)); \ 1670 } while (0) 1671 1672 #define _umips_dsp_mfxxx(ins) \ 1673 ({ \ 1674 unsigned long __treg; \ 1675 \ 1676 __asm__ __volatile__( \ 1677 " .set push \n" \ 1678 " .set noat \n" \ 1679 " .hword 0x0001 \n" \ 1680 " .hword %x1 \n" \ 1681 " move %0, $1 \n" \ 1682 " .set pop \n" \ 1683 : "=r" (__treg) \ 1684 : "i" (ins)); \ 1685 __treg; \ 1686 }) 1687 1688 #define _umips_dsp_mtxxx(val, ins) \ 1689 do { \ 1690 __asm__ __volatile__( \ 1691 " .set push \n" \ 1692 " .set noat \n" \ 1693 " move $1, %0 \n" \ 1694 " .hword 0x0001 \n" \ 1695 " .hword %x1 \n" \ 1696 " .set pop \n" \ 1697 : \ 1698 : "r" (val), "i" (ins)); \ 1699 } while (0) 1700 1701 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) 1702 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) 1703 1704 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) 1705 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) 1706 1707 #define mflo0() _umips_dsp_mflo(0) 1708 #define mflo1() _umips_dsp_mflo(1) 1709 #define mflo2() _umips_dsp_mflo(2) 1710 #define mflo3() _umips_dsp_mflo(3) 1711 1712 #define mfhi0() _umips_dsp_mfhi(0) 1713 #define mfhi1() _umips_dsp_mfhi(1) 1714 #define mfhi2() _umips_dsp_mfhi(2) 1715 #define mfhi3() _umips_dsp_mfhi(3) 1716 1717 #define mtlo0(x) _umips_dsp_mtlo(x, 0) 1718 #define mtlo1(x) _umips_dsp_mtlo(x, 1) 1719 #define mtlo2(x) _umips_dsp_mtlo(x, 2) 1720 #define mtlo3(x) _umips_dsp_mtlo(x, 3) 1721 1722 #define mthi0(x) _umips_dsp_mthi(x, 0) 1723 #define mthi1(x) _umips_dsp_mthi(x, 1) 1724 #define mthi2(x) _umips_dsp_mthi(x, 2) 1725 #define mthi3(x) _umips_dsp_mthi(x, 3) 1726 1727 #else /* !CONFIG_CPU_MICROMIPS */ 1728 #define rddsp(mask) \ 1729 ({ \ 1730 unsigned int __res; \ 1731 \ 1732 __asm__ __volatile__( \ 1733 " .set push \n" \ 1734 " .set noat \n" \ 1735 " # rddsp $1, %x1 \n" \ 1736 " .word 0x7c000cb8 | (%x1 << 16) \n" \ 1737 " move %0, $1 \n" \ 1738 " .set pop \n" \ 1739 : "=r" (__res) \ 1740 : "i" (mask)); \ 1741 __res; \ 1742 }) 1743 1744 #define wrdsp(val, mask) \ 1745 do { \ 1746 __asm__ __volatile__( \ 1747 " .set push \n" \ 1748 " .set noat \n" \ 1749 " move $1, %0 \n" \ 1750 " # wrdsp $1, %x1 \n" \ 1751 " .word 0x7c2004f8 | (%x1 << 11) \n" \ 1752 " .set pop \n" \ 1753 : \ 1754 : "r" (val), "i" (mask)); \ 1755 } while (0) 1756 1757 #define _dsp_mfxxx(ins) \ 1758 ({ \ 1759 unsigned long __treg; \ 1760 \ 1761 __asm__ __volatile__( \ 1762 " .set push \n" \ 1763 " .set noat \n" \ 1764 " .word (0x00000810 | %1) \n" \ 1765 " move %0, $1 \n" \ 1766 " .set pop \n" \ 1767 : "=r" (__treg) \ 1768 : "i" (ins)); \ 1769 __treg; \ 1770 }) 1771 1772 #define _dsp_mtxxx(val, ins) \ 1773 do { \ 1774 __asm__ __volatile__( \ 1775 " .set push \n" \ 1776 " .set noat \n" \ 1777 " move $1, %0 \n" \ 1778 " .word (0x00200011 | %1) \n" \ 1779 " .set pop \n" \ 1780 : \ 1781 : "r" (val), "i" (ins)); \ 1782 } while (0) 1783 1784 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) 1785 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) 1786 1787 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) 1788 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) 1789 1790 #define mflo0() _dsp_mflo(0) 1791 #define mflo1() _dsp_mflo(1) 1792 #define mflo2() _dsp_mflo(2) 1793 #define mflo3() _dsp_mflo(3) 1794 1795 #define mfhi0() _dsp_mfhi(0) 1796 #define mfhi1() _dsp_mfhi(1) 1797 #define mfhi2() _dsp_mfhi(2) 1798 #define mfhi3() _dsp_mfhi(3) 1799 1800 #define mtlo0(x) _dsp_mtlo(x, 0) 1801 #define mtlo1(x) _dsp_mtlo(x, 1) 1802 #define mtlo2(x) _dsp_mtlo(x, 2) 1803 #define mtlo3(x) _dsp_mtlo(x, 3) 1804 1805 #define mthi0(x) _dsp_mthi(x, 0) 1806 #define mthi1(x) _dsp_mthi(x, 1) 1807 #define mthi2(x) _dsp_mthi(x, 2) 1808 #define mthi3(x) _dsp_mthi(x, 3) 1809 1810 #endif /* CONFIG_CPU_MICROMIPS */ 1811 #endif 1812 1813 /* 1814 * TLB operations. 1815 * 1816 * It is responsibility of the caller to take care of any TLB hazards. 1817 */ 1818 static inline void tlb_probe(void) 1819 { 1820 __asm__ __volatile__( 1821 ".set noreorder\n\t" 1822 "tlbp\n\t" 1823 ".set reorder"); 1824 } 1825 1826 static inline void tlb_read(void) 1827 { 1828 #if MIPS34K_MISSED_ITLB_WAR 1829 int res = 0; 1830 1831 __asm__ __volatile__( 1832 " .set push \n" 1833 " .set noreorder \n" 1834 " .set noat \n" 1835 " .set mips32r2 \n" 1836 " .word 0x41610001 # dvpe $1 \n" 1837 " move %0, $1 \n" 1838 " ehb \n" 1839 " .set pop \n" 1840 : "=r" (res)); 1841 1842 instruction_hazard(); 1843 #endif 1844 1845 __asm__ __volatile__( 1846 ".set noreorder\n\t" 1847 "tlbr\n\t" 1848 ".set reorder"); 1849 1850 #if MIPS34K_MISSED_ITLB_WAR 1851 if ((res & _ULCAST_(1))) 1852 __asm__ __volatile__( 1853 " .set push \n" 1854 " .set noreorder \n" 1855 " .set noat \n" 1856 " .set mips32r2 \n" 1857 " .word 0x41600021 # evpe \n" 1858 " ehb \n" 1859 " .set pop \n"); 1860 #endif 1861 } 1862 1863 static inline void tlb_write_indexed(void) 1864 { 1865 __asm__ __volatile__( 1866 ".set noreorder\n\t" 1867 "tlbwi\n\t" 1868 ".set reorder"); 1869 } 1870 1871 static inline void tlb_write_random(void) 1872 { 1873 __asm__ __volatile__( 1874 ".set noreorder\n\t" 1875 "tlbwr\n\t" 1876 ".set reorder"); 1877 } 1878 1879 /* 1880 * Manipulate bits in a c0 register. 1881 */ 1882 #define __BUILD_SET_C0(name) \ 1883 static inline unsigned int \ 1884 set_c0_##name(unsigned int set) \ 1885 { \ 1886 unsigned int res, new; \ 1887 \ 1888 res = read_c0_##name(); \ 1889 new = res | set; \ 1890 write_c0_##name(new); \ 1891 \ 1892 return res; \ 1893 } \ 1894 \ 1895 static inline unsigned int \ 1896 clear_c0_##name(unsigned int clear) \ 1897 { \ 1898 unsigned int res, new; \ 1899 \ 1900 res = read_c0_##name(); \ 1901 new = res & ~clear; \ 1902 write_c0_##name(new); \ 1903 \ 1904 return res; \ 1905 } \ 1906 \ 1907 static inline unsigned int \ 1908 change_c0_##name(unsigned int change, unsigned int val) \ 1909 { \ 1910 unsigned int res, new; \ 1911 \ 1912 res = read_c0_##name(); \ 1913 new = res & ~change; \ 1914 new |= (val & change); \ 1915 write_c0_##name(new); \ 1916 \ 1917 return res; \ 1918 } 1919 1920 __BUILD_SET_C0(status) 1921 __BUILD_SET_C0(cause) 1922 __BUILD_SET_C0(config) 1923 __BUILD_SET_C0(config5) 1924 __BUILD_SET_C0(intcontrol) 1925 __BUILD_SET_C0(intctl) 1926 __BUILD_SET_C0(srsmap) 1927 __BUILD_SET_C0(pagegrain) 1928 __BUILD_SET_C0(brcm_config_0) 1929 __BUILD_SET_C0(brcm_bus_pll) 1930 __BUILD_SET_C0(brcm_reset) 1931 __BUILD_SET_C0(brcm_cmt_intr) 1932 __BUILD_SET_C0(brcm_cmt_ctrl) 1933 __BUILD_SET_C0(brcm_config) 1934 __BUILD_SET_C0(brcm_mode) 1935 1936 /* 1937 * Return low 10 bits of ebase. 1938 * Note that under KVM (MIPSVZ) this returns vcpu id. 1939 */ 1940 static inline unsigned int get_ebase_cpunum(void) 1941 { 1942 return read_c0_ebase() & 0x3ff; 1943 } 1944 1945 #endif /* !__ASSEMBLY__ */ 1946 1947 #endif /* _ASM_MIPSREGS_H */ 1948