1 /* 2 * Copyright (C) 2013 Imagination Technologies 3 * Author: Paul Burton <paul.burton@imgtec.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 */ 10 11 #ifndef __MIPS_ASM_MIPS_CM_H__ 12 #define __MIPS_ASM_MIPS_CM_H__ 13 14 #include <linux/errno.h> 15 #include <linux/io.h> 16 #include <linux/types.h> 17 18 /* The base address of the CM GCR block */ 19 extern void __iomem *mips_cm_base; 20 21 /* The base address of the CM L2-only sync region */ 22 extern void __iomem *mips_cm_l2sync_base; 23 24 /** 25 * __mips_cm_phys_base - retrieve the physical base address of the CM 26 * 27 * This function returns the physical base address of the Coherence Manager 28 * global control block, or 0 if no Coherence Manager is present. It provides 29 * a default implementation which reads the CMGCRBase register where available, 30 * and may be overriden by platforms which determine this address in a 31 * different way by defining a function with the same prototype except for the 32 * name mips_cm_phys_base (without underscores). 33 */ 34 extern phys_addr_t __mips_cm_phys_base(void); 35 36 /* 37 * mips_cm_is64 - determine CM register width 38 * 39 * The CM register width is processor and CM specific. A 64-bit processor 40 * usually has a 64-bit CM and a 32-bit one has a 32-bit CM but a 64-bit 41 * processor could come with a 32-bit CM. Moreover, accesses on 64-bit CMs 42 * can be done either using regular 64-bit load/store instructions, or 32-bit 43 * load/store instruction on 32-bit register pairs. We opt for using 64-bit 44 * accesses on 64-bit CMs and kernels and 32-bit in any other case. 45 * 46 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses. 47 */ 48 extern int mips_cm_is64; 49 50 /** 51 * mips_cm_error_report - Report CM cache errors 52 */ 53 #ifdef CONFIG_MIPS_CM 54 extern void mips_cm_error_report(void); 55 #else 56 static inline void mips_cm_error_report(void) {} 57 #endif 58 59 /** 60 * mips_cm_probe - probe for a Coherence Manager 61 * 62 * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM 63 * is successfully detected, else -errno. 64 */ 65 #ifdef CONFIG_MIPS_CM 66 extern int mips_cm_probe(void); 67 #else 68 static inline int mips_cm_probe(void) 69 { 70 return -ENODEV; 71 } 72 #endif 73 74 /** 75 * mips_cm_present - determine whether a Coherence Manager is present 76 * 77 * Returns true if a CM is present in the system, else false. 78 */ 79 static inline bool mips_cm_present(void) 80 { 81 #ifdef CONFIG_MIPS_CM 82 return mips_cm_base != NULL; 83 #else 84 return false; 85 #endif 86 } 87 88 /** 89 * mips_cm_has_l2sync - determine whether an L2-only sync region is present 90 * 91 * Returns true if the system implements an L2-only sync region, else false. 92 */ 93 static inline bool mips_cm_has_l2sync(void) 94 { 95 #ifdef CONFIG_MIPS_CM 96 return mips_cm_l2sync_base != NULL; 97 #else 98 return false; 99 #endif 100 } 101 102 /* Offsets to register blocks from the CM base address */ 103 #define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */ 104 #define MIPS_CM_CLCB_OFS 0x2000 /* Core Local Control Block */ 105 #define MIPS_CM_COCB_OFS 0x4000 /* Core Other Control Block */ 106 #define MIPS_CM_GDB_OFS 0x6000 /* Global Debug Block */ 107 108 /* Total size of the CM memory mapped registers */ 109 #define MIPS_CM_GCR_SIZE 0x8000 110 111 /* Size of the L2-only sync region */ 112 #define MIPS_CM_L2SYNC_SIZE 0x1000 113 114 /* Macros to ease the creation of register access functions */ 115 #define BUILD_CM_R_(name, off) \ 116 static inline unsigned long __iomem *addr_gcr_##name(void) \ 117 { \ 118 return (unsigned long __iomem *)(mips_cm_base + (off)); \ 119 } \ 120 \ 121 static inline u32 read32_gcr_##name(void) \ 122 { \ 123 return __raw_readl(addr_gcr_##name()); \ 124 } \ 125 \ 126 static inline u64 read64_gcr_##name(void) \ 127 { \ 128 return __raw_readq(addr_gcr_##name()); \ 129 } \ 130 \ 131 static inline unsigned long read_gcr_##name(void) \ 132 { \ 133 if (mips_cm_is64) \ 134 return read64_gcr_##name(); \ 135 else \ 136 return read32_gcr_##name(); \ 137 } 138 139 #define BUILD_CM__W(name, off) \ 140 static inline void write32_gcr_##name(u32 value) \ 141 { \ 142 __raw_writel(value, addr_gcr_##name()); \ 143 } \ 144 \ 145 static inline void write64_gcr_##name(u64 value) \ 146 { \ 147 __raw_writeq(value, addr_gcr_##name()); \ 148 } \ 149 \ 150 static inline void write_gcr_##name(unsigned long value) \ 151 { \ 152 if (mips_cm_is64) \ 153 write64_gcr_##name(value); \ 154 else \ 155 write32_gcr_##name(value); \ 156 } 157 158 #define BUILD_CM_RW(name, off) \ 159 BUILD_CM_R_(name, off) \ 160 BUILD_CM__W(name, off) 161 162 #define BUILD_CM_Cx_R_(name, off) \ 163 BUILD_CM_R_(cl_##name, MIPS_CM_CLCB_OFS + (off)) \ 164 BUILD_CM_R_(co_##name, MIPS_CM_COCB_OFS + (off)) 165 166 #define BUILD_CM_Cx__W(name, off) \ 167 BUILD_CM__W(cl_##name, MIPS_CM_CLCB_OFS + (off)) \ 168 BUILD_CM__W(co_##name, MIPS_CM_COCB_OFS + (off)) 169 170 #define BUILD_CM_Cx_RW(name, off) \ 171 BUILD_CM_Cx_R_(name, off) \ 172 BUILD_CM_Cx__W(name, off) 173 174 /* GCB register accessor functions */ 175 BUILD_CM_R_(config, MIPS_CM_GCB_OFS + 0x00) 176 BUILD_CM_RW(base, MIPS_CM_GCB_OFS + 0x08) 177 BUILD_CM_RW(access, MIPS_CM_GCB_OFS + 0x20) 178 BUILD_CM_R_(rev, MIPS_CM_GCB_OFS + 0x30) 179 BUILD_CM_RW(error_mask, MIPS_CM_GCB_OFS + 0x40) 180 BUILD_CM_RW(error_cause, MIPS_CM_GCB_OFS + 0x48) 181 BUILD_CM_RW(error_addr, MIPS_CM_GCB_OFS + 0x50) 182 BUILD_CM_RW(error_mult, MIPS_CM_GCB_OFS + 0x58) 183 BUILD_CM_RW(l2_only_sync_base, MIPS_CM_GCB_OFS + 0x70) 184 BUILD_CM_RW(gic_base, MIPS_CM_GCB_OFS + 0x80) 185 BUILD_CM_RW(cpc_base, MIPS_CM_GCB_OFS + 0x88) 186 BUILD_CM_RW(reg0_base, MIPS_CM_GCB_OFS + 0x90) 187 BUILD_CM_RW(reg0_mask, MIPS_CM_GCB_OFS + 0x98) 188 BUILD_CM_RW(reg1_base, MIPS_CM_GCB_OFS + 0xa0) 189 BUILD_CM_RW(reg1_mask, MIPS_CM_GCB_OFS + 0xa8) 190 BUILD_CM_RW(reg2_base, MIPS_CM_GCB_OFS + 0xb0) 191 BUILD_CM_RW(reg2_mask, MIPS_CM_GCB_OFS + 0xb8) 192 BUILD_CM_RW(reg3_base, MIPS_CM_GCB_OFS + 0xc0) 193 BUILD_CM_RW(reg3_mask, MIPS_CM_GCB_OFS + 0xc8) 194 BUILD_CM_R_(gic_status, MIPS_CM_GCB_OFS + 0xd0) 195 BUILD_CM_R_(cpc_status, MIPS_CM_GCB_OFS + 0xf0) 196 BUILD_CM_RW(l2_config, MIPS_CM_GCB_OFS + 0x130) 197 BUILD_CM_RW(sys_config2, MIPS_CM_GCB_OFS + 0x150) 198 199 /* Core Local & Core Other register accessor functions */ 200 BUILD_CM_Cx_RW(reset_release, 0x00) 201 BUILD_CM_Cx_RW(coherence, 0x08) 202 BUILD_CM_Cx_R_(config, 0x10) 203 BUILD_CM_Cx_RW(other, 0x18) 204 BUILD_CM_Cx_RW(reset_base, 0x20) 205 BUILD_CM_Cx_R_(id, 0x28) 206 BUILD_CM_Cx_RW(reset_ext_base, 0x30) 207 BUILD_CM_Cx_R_(tcid_0_priority, 0x40) 208 BUILD_CM_Cx_R_(tcid_1_priority, 0x48) 209 BUILD_CM_Cx_R_(tcid_2_priority, 0x50) 210 BUILD_CM_Cx_R_(tcid_3_priority, 0x58) 211 BUILD_CM_Cx_R_(tcid_4_priority, 0x60) 212 BUILD_CM_Cx_R_(tcid_5_priority, 0x68) 213 BUILD_CM_Cx_R_(tcid_6_priority, 0x70) 214 BUILD_CM_Cx_R_(tcid_7_priority, 0x78) 215 BUILD_CM_Cx_R_(tcid_8_priority, 0x80) 216 217 /* GCR_CONFIG register fields */ 218 #define CM_GCR_CONFIG_NUMIOCU_SHF 8 219 #define CM_GCR_CONFIG_NUMIOCU_MSK (_ULCAST_(0xf) << 8) 220 #define CM_GCR_CONFIG_PCORES_SHF 0 221 #define CM_GCR_CONFIG_PCORES_MSK (_ULCAST_(0xff) << 0) 222 223 /* GCR_BASE register fields */ 224 #define CM_GCR_BASE_GCRBASE_SHF 15 225 #define CM_GCR_BASE_GCRBASE_MSK (_ULCAST_(0x1ffff) << 15) 226 #define CM_GCR_BASE_CMDEFTGT_SHF 0 227 #define CM_GCR_BASE_CMDEFTGT_MSK (_ULCAST_(0x3) << 0) 228 #define CM_GCR_BASE_CMDEFTGT_DISABLED 0 229 #define CM_GCR_BASE_CMDEFTGT_MEM 1 230 #define CM_GCR_BASE_CMDEFTGT_IOCU0 2 231 #define CM_GCR_BASE_CMDEFTGT_IOCU1 3 232 233 /* GCR_ACCESS register fields */ 234 #define CM_GCR_ACCESS_ACCESSEN_SHF 0 235 #define CM_GCR_ACCESS_ACCESSEN_MSK (_ULCAST_(0xff) << 0) 236 237 /* GCR_REV register fields */ 238 #define CM_GCR_REV_MAJOR_SHF 8 239 #define CM_GCR_REV_MAJOR_MSK (_ULCAST_(0xff) << 8) 240 #define CM_GCR_REV_MINOR_SHF 0 241 #define CM_GCR_REV_MINOR_MSK (_ULCAST_(0xff) << 0) 242 243 #define CM_ENCODE_REV(major, minor) \ 244 (((major) << CM_GCR_REV_MAJOR_SHF) | \ 245 ((minor) << CM_GCR_REV_MINOR_SHF)) 246 247 #define CM_REV_CM2 CM_ENCODE_REV(6, 0) 248 #define CM_REV_CM3 CM_ENCODE_REV(8, 0) 249 250 /* GCR_ERROR_CAUSE register fields */ 251 #define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF 27 252 #define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK (_ULCAST_(0x1f) << 27) 253 #define CM_GCR_ERROR_CAUSE_ERRINFO_SHF 0 254 #define CM_GCR_ERROR_CAUSE_ERRINGO_MSK (_ULCAST_(0x7ffffff) << 0) 255 256 /* GCR_ERROR_MULT register fields */ 257 #define CM_GCR_ERROR_MULT_ERR2ND_SHF 0 258 #define CM_GCR_ERROR_MULT_ERR2ND_MSK (_ULCAST_(0x1f) << 0) 259 260 /* GCR_L2_ONLY_SYNC_BASE register fields */ 261 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_SHF 12 262 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK (_ULCAST_(0xfffff) << 12) 263 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_SHF 0 264 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK (_ULCAST_(0x1) << 0) 265 266 /* GCR_GIC_BASE register fields */ 267 #define CM_GCR_GIC_BASE_GICBASE_SHF 17 268 #define CM_GCR_GIC_BASE_GICBASE_MSK (_ULCAST_(0x7fff) << 17) 269 #define CM_GCR_GIC_BASE_GICEN_SHF 0 270 #define CM_GCR_GIC_BASE_GICEN_MSK (_ULCAST_(0x1) << 0) 271 272 /* GCR_CPC_BASE register fields */ 273 #define CM_GCR_CPC_BASE_CPCBASE_SHF 17 274 #define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x7fff) << 17) 275 #define CM_GCR_CPC_BASE_CPCEN_SHF 0 276 #define CM_GCR_CPC_BASE_CPCEN_MSK (_ULCAST_(0x1) << 0) 277 278 /* GCR_GIC_STATUS register fields */ 279 #define CM_GCR_GIC_STATUS_GICEX_SHF 0 280 #define CM_GCR_GIC_STATUS_GICEX_MSK (_ULCAST_(0x1) << 0) 281 282 /* GCR_REGn_BASE register fields */ 283 #define CM_GCR_REGn_BASE_BASEADDR_SHF 16 284 #define CM_GCR_REGn_BASE_BASEADDR_MSK (_ULCAST_(0xffff) << 16) 285 286 /* GCR_REGn_MASK register fields */ 287 #define CM_GCR_REGn_MASK_ADDRMASK_SHF 16 288 #define CM_GCR_REGn_MASK_ADDRMASK_MSK (_ULCAST_(0xffff) << 16) 289 #define CM_GCR_REGn_MASK_CCAOVR_SHF 5 290 #define CM_GCR_REGn_MASK_CCAOVR_MSK (_ULCAST_(0x3) << 5) 291 #define CM_GCR_REGn_MASK_CCAOVREN_SHF 4 292 #define CM_GCR_REGn_MASK_CCAOVREN_MSK (_ULCAST_(0x1) << 4) 293 #define CM_GCR_REGn_MASK_DROPL2_SHF 2 294 #define CM_GCR_REGn_MASK_DROPL2_MSK (_ULCAST_(0x1) << 2) 295 #define CM_GCR_REGn_MASK_CMTGT_SHF 0 296 #define CM_GCR_REGn_MASK_CMTGT_MSK (_ULCAST_(0x3) << 0) 297 #define CM_GCR_REGn_MASK_CMTGT_DISABLED (_ULCAST_(0x0) << 0) 298 #define CM_GCR_REGn_MASK_CMTGT_MEM (_ULCAST_(0x1) << 0) 299 #define CM_GCR_REGn_MASK_CMTGT_IOCU0 (_ULCAST_(0x2) << 0) 300 #define CM_GCR_REGn_MASK_CMTGT_IOCU1 (_ULCAST_(0x3) << 0) 301 302 /* GCR_GIC_STATUS register fields */ 303 #define CM_GCR_GIC_STATUS_EX_SHF 0 304 #define CM_GCR_GIC_STATUS_EX_MSK (_ULCAST_(0x1) << 0) 305 306 /* GCR_CPC_STATUS register fields */ 307 #define CM_GCR_CPC_STATUS_EX_SHF 0 308 #define CM_GCR_CPC_STATUS_EX_MSK (_ULCAST_(0x1) << 0) 309 310 /* GCR_L2_CONFIG register fields */ 311 #define CM_GCR_L2_CONFIG_BYPASS_SHF 20 312 #define CM_GCR_L2_CONFIG_BYPASS_MSK (_ULCAST_(0x1) << 20) 313 #define CM_GCR_L2_CONFIG_SET_SIZE_SHF 12 314 #define CM_GCR_L2_CONFIG_SET_SIZE_MSK (_ULCAST_(0xf) << 12) 315 #define CM_GCR_L2_CONFIG_LINE_SIZE_SHF 8 316 #define CM_GCR_L2_CONFIG_LINE_SIZE_MSK (_ULCAST_(0xf) << 8) 317 #define CM_GCR_L2_CONFIG_ASSOC_SHF 0 318 #define CM_GCR_L2_CONFIG_ASSOC_MSK (_ULCAST_(0xff) << 0) 319 320 /* GCR_SYS_CONFIG2 register fields */ 321 #define CM_GCR_SYS_CONFIG2_MAXVPW_SHF 0 322 #define CM_GCR_SYS_CONFIG2_MAXVPW_MSK (_ULCAST_(0xf) << 0) 323 324 /* GCR_Cx_COHERENCE register fields */ 325 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF 0 326 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK (_ULCAST_(0xff) << 0) 327 328 /* GCR_Cx_CONFIG register fields */ 329 #define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF 10 330 #define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK (_ULCAST_(0x3) << 10) 331 #define CM_GCR_Cx_CONFIG_PVPE_SHF 0 332 #define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x1ff) << 0) 333 334 /* GCR_Cx_OTHER register fields */ 335 #define CM_GCR_Cx_OTHER_CORENUM_SHF 16 336 #define CM_GCR_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xffff) << 16) 337 338 /* GCR_Cx_RESET_BASE register fields */ 339 #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_SHF 12 340 #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_MSK (_ULCAST_(0xfffff) << 12) 341 342 /* GCR_Cx_RESET_EXT_BASE register fields */ 343 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_SHF 31 344 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_MSK (_ULCAST_(0x1) << 31) 345 #define CM_GCR_Cx_RESET_EXT_BASE_UEB_SHF 30 346 #define CM_GCR_Cx_RESET_EXT_BASE_UEB_MSK (_ULCAST_(0x1) << 30) 347 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_SHF 20 348 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_MSK (_ULCAST_(0xff) << 20) 349 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_SHF 1 350 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_MSK (_ULCAST_(0x7f) << 1) 351 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_SHF 0 352 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK (_ULCAST_(0x1) << 0) 353 354 /** 355 * mips_cm_numcores - return the number of cores present in the system 356 * 357 * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or 358 * zero if no Coherence Manager is present. 359 */ 360 static inline unsigned mips_cm_numcores(void) 361 { 362 if (!mips_cm_present()) 363 return 0; 364 365 return ((read_gcr_config() & CM_GCR_CONFIG_PCORES_MSK) 366 >> CM_GCR_CONFIG_PCORES_SHF) + 1; 367 } 368 369 /** 370 * mips_cm_numiocu - return the number of IOCUs present in the system 371 * 372 * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero 373 * if no Coherence Manager is present. 374 */ 375 static inline unsigned mips_cm_numiocu(void) 376 { 377 if (!mips_cm_present()) 378 return 0; 379 380 return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU_MSK) 381 >> CM_GCR_CONFIG_NUMIOCU_SHF; 382 } 383 384 /** 385 * mips_cm_l2sync - perform an L2-only sync operation 386 * 387 * If an L2-only sync region is present in the system then this function 388 * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV. 389 */ 390 static inline int mips_cm_l2sync(void) 391 { 392 if (!mips_cm_has_l2sync()) 393 return -ENODEV; 394 395 writel(0, mips_cm_l2sync_base); 396 return 0; 397 } 398 399 /** 400 * mips_cm_revision() - return CM revision 401 * 402 * Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The 403 * return value should be checked against the CM_REV_* macros. 404 */ 405 static inline int mips_cm_revision(void) 406 { 407 if (!mips_cm_present()) 408 return 0; 409 410 return read_gcr_rev(); 411 } 412 413 /** 414 * mips_cm_max_vp_width() - return the width in bits of VP indices 415 * 416 * Return: the width, in bits, of VP indices in fields that combine core & VP 417 * indices. 418 */ 419 static inline unsigned int mips_cm_max_vp_width(void) 420 { 421 extern int smp_num_siblings; 422 423 if (mips_cm_revision() >= CM_REV_CM3) 424 return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW_MSK; 425 426 return smp_num_siblings; 427 } 428 429 /** 430 * mips_cm_vp_id() - calculate the hardware VP ID for a CPU 431 * @cpu: the CPU whose VP ID to calculate 432 * 433 * Hardware such as the GIC uses identifiers for VPs which may not match the 434 * CPU numbers used by Linux. This function calculates the hardware VP 435 * identifier corresponding to a given CPU. 436 * 437 * Return: the VP ID for the CPU. 438 */ 439 static inline unsigned int mips_cm_vp_id(unsigned int cpu) 440 { 441 unsigned int core = cpu_data[cpu].core; 442 unsigned int vp = cpu_vpe_id(&cpu_data[cpu]); 443 444 return (core * mips_cm_max_vp_width()) + vp; 445 } 446 447 #endif /* __MIPS_ASM_MIPS_CM_H__ */ 448