1*be2d960eSRalf Baechle /* 2*be2d960eSRalf Baechle * This file is subject to the terms and conditions of the GNU General Public 3*be2d960eSRalf Baechle * License. See the file "COPYING" in the main directory of this archive 4*be2d960eSRalf Baechle * for more details. 5*be2d960eSRalf Baechle * 6*be2d960eSRalf Baechle * Copyright (C) 2015 Imagination Technologies, Inc. 7*be2d960eSRalf Baechle * written by Ralf Baechle <ralf@linux-mips.org> 8*be2d960eSRalf Baechle */ 9*be2d960eSRalf Baechle #ifndef __ASM_MIPS_BOARDS_SEAD3_ADDR_H 10*be2d960eSRalf Baechle #define __ASM_MIPS_BOARDS_SEAD3_ADDR_H 11*be2d960eSRalf Baechle 12*be2d960eSRalf Baechle /* 13*be2d960eSRalf Baechle * Target #0 Register Decode 14*be2d960eSRalf Baechle */ 15*be2d960eSRalf Baechle #define SEAD3_SD_SPDCNF 0xbb000040 16*be2d960eSRalf Baechle #define SEAD3_SD_SPADDR 0xbb000048 17*be2d960eSRalf Baechle #define SEAD3_SD_DATA 0xbb000050 18*be2d960eSRalf Baechle 19*be2d960eSRalf Baechle /* 20*be2d960eSRalf Baechle * Target #1 Register Decode 21*be2d960eSRalf Baechle */ 22*be2d960eSRalf Baechle #define SEAD3_CFG 0xbb100110 23*be2d960eSRalf Baechle #define SEAD3_GIC_BASE_ADDRESS 0xbb1c0000 24*be2d960eSRalf Baechle #define SEAD3_SHARED_SECTION 0xbb1c0000 25*be2d960eSRalf Baechle #define SEAD3_VPE_LOCAL_SECTION 0xbb1c8000 26*be2d960eSRalf Baechle #define SEAD3_VPE_OTHER_SECTION 0xbb1cc000 27*be2d960eSRalf Baechle #define SEAD3_USER_MODE_VISIBLE_SECTION 0xbb1d0000 28*be2d960eSRalf Baechle 29*be2d960eSRalf Baechle /* 30*be2d960eSRalf Baechle * Target #3 Register Decode 31*be2d960eSRalf Baechle */ 32*be2d960eSRalf Baechle #define SEAD3_USB_HS_BASE 0xbb200000 33*be2d960eSRalf Baechle #define SEAD3_USB_HS_IDENTIFICATION_REGS 0xbb200000 34*be2d960eSRalf Baechle #define SEAD3_USB_HS_CAPABILITY_REGS 0xbb200100 35*be2d960eSRalf Baechle #define SEAD3_USB_HS_OPERATIONAL_REGS 0xbb200140 36*be2d960eSRalf Baechle #define SEAD3_RESERVED 0xbe800000 37*be2d960eSRalf Baechle 38*be2d960eSRalf Baechle /* 39*be2d960eSRalf Baechle * Target #3 Register Decode 40*be2d960eSRalf Baechle */ 41*be2d960eSRalf Baechle #define SEAD3_SRAM 0xbe000000 42*be2d960eSRalf Baechle #define SEAD3_OPTIONAL_SRAM 0xbe400000 43*be2d960eSRalf Baechle #define SEAD3_FPGA 0xbf000000 44*be2d960eSRalf Baechle 45*be2d960eSRalf Baechle #define SEAD3_PI_PIC32_USB_STATUS 0xbf000060 46*be2d960eSRalf Baechle #define SEAD3_PI_PIC32_USB_STATUS_IO_RDY (1 << 0) 47*be2d960eSRalf Baechle #define SEAD3_PI_PIC32_USB_STATUS_SPL_INT (1 << 1) 48*be2d960eSRalf Baechle #define SEAD3_PI_PIC32_USB_STATUS_GPIOA_INT (1 << 2) 49*be2d960eSRalf Baechle #define SEAD3_PI_PIC32_USB_STATUS_GPIOB_INT (1 << 3) 50*be2d960eSRalf Baechle 51*be2d960eSRalf Baechle #define SEAD3_PI_SOFT_ENDIAN 0xbf000070 52*be2d960eSRalf Baechle 53*be2d960eSRalf Baechle #define SEAD3_CPLD_P_SWITCH 0xbf000200 54*be2d960eSRalf Baechle #define SEAD3_CPLD_F_SWITCH 0xbf000208 55*be2d960eSRalf Baechle #define SEAD3_CPLD_P_LED 0xbf000210 56*be2d960eSRalf Baechle #define SEAD3_CPLD_F_LED 0xbf000218 57*be2d960eSRalf Baechle #define SEAD3_NEWSC_LIVE 0xbf000220 58*be2d960eSRalf Baechle #define SEAD3_NEWSC_REG 0xbf000228 59*be2d960eSRalf Baechle #define SEAD3_NEWSC_CTRL 0xbf000230 60*be2d960eSRalf Baechle 61*be2d960eSRalf Baechle #define SEAD3_LCD_CONTROL 0xbf000400 62*be2d960eSRalf Baechle #define SEAD3_LCD_DATA 0xbf000408 63*be2d960eSRalf Baechle #define SEAD3_CPLD_LCD_STATUS 0xbf000410 64*be2d960eSRalf Baechle #define SEAD3_CPLD_LCD_DATA 0xbf000418 65*be2d960eSRalf Baechle 66*be2d960eSRalf Baechle #define SEAD3_CPLD_PI_DEVRST 0xbf000480 67*be2d960eSRalf Baechle #define SEAD3_CPLD_PI_DEVRST_IC32_RST (1 << 0) 68*be2d960eSRalf Baechle #define SEAD3_RESERVED_0 0xbf000500 69*be2d960eSRalf Baechle 70*be2d960eSRalf Baechle #define SEAD3_PIC32_REGISTERS 0xbf000600 71*be2d960eSRalf Baechle #define SEAD3_RESERVED_1 0xbf000700 72*be2d960eSRalf Baechle #define SEAD3_UART_CH_0 0xbf000800 73*be2d960eSRalf Baechle #define SEAD3_UART_CH_1 0xbf000900 74*be2d960eSRalf Baechle #define SEAD3_RESERVED_2 0xbf000a00 75*be2d960eSRalf Baechle #define SEAD3_ETHERNET 0xbf010000 76*be2d960eSRalf Baechle #define SEAD3_RESERVED_3 0xbf020000 77*be2d960eSRalf Baechle #define SEAD3_USER_EXPANSION 0xbf400000 78*be2d960eSRalf Baechle #define SEAD3_RESERVED_4 0xbf800000 79*be2d960eSRalf Baechle #define SEAD3_BOOT_FLASH_EXTENSION 0xbfa00000 80*be2d960eSRalf Baechle #define SEAD3_BOOT_FLASH 0xbfc00000 81*be2d960eSRalf Baechle #define SEAD3_REVISION_REGISTER 0xbfc00010 82*be2d960eSRalf Baechle 83*be2d960eSRalf Baechle #endif /* __ASM_MIPS_BOARDS_SEAD3_ADDR_H */ 84