1384740dcSRalf Baechle /* 2384740dcSRalf Baechle * Carsten Langgaard, carstenl@mips.com 3384740dcSRalf Baechle * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 470002f76SDeng-Cheng Zhu * Copyright (C) 2013 Imagination Technologies Ltd. 5384740dcSRalf Baechle * 6384740dcSRalf Baechle * This program is free software; you can distribute it and/or modify it 7384740dcSRalf Baechle * under the terms of the GNU General Public License (Version 2) as 8384740dcSRalf Baechle * published by the Free Software Foundation. 9384740dcSRalf Baechle * 10384740dcSRalf Baechle * This program is distributed in the hope it will be useful, but WITHOUT 11384740dcSRalf Baechle * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12384740dcSRalf Baechle * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13384740dcSRalf Baechle * for more details. 14384740dcSRalf Baechle * 15384740dcSRalf Baechle * You should have received a copy of the GNU General Public License along 16384740dcSRalf Baechle * with this program; if not, write to the Free Software Foundation, Inc., 17384740dcSRalf Baechle * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 18384740dcSRalf Baechle * 19384740dcSRalf Baechle * Register definitions for Intel PIIX4 South Bridge Device. 20384740dcSRalf Baechle */ 21384740dcSRalf Baechle #ifndef __ASM_MIPS_BOARDS_PIIX4_H 22384740dcSRalf Baechle #define __ASM_MIPS_BOARDS_PIIX4_H 23384740dcSRalf Baechle 2470002f76SDeng-Cheng Zhu /* PIRQX Route Control */ 2570002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_PIRQRC 0x60 2670002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7) 2770002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf 2870002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16 29ae0d7cbcSPaul Burton /* SERIRQ Control */ 30ae0d7cbcSPaul Burton #define PIIX4_FUNC0_SERIRQC 0x64 31ae0d7cbcSPaul Burton #define PIIX4_FUNC0_SERIRQC_EN (1 << 7) 32ae0d7cbcSPaul Burton #define PIIX4_FUNC0_SERIRQC_CONT (1 << 6) 3370002f76SDeng-Cheng Zhu /* Top Of Memory */ 3470002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_TOM 0x69 3570002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0 3670002f76SDeng-Cheng Zhu /* Deterministic Latency Control */ 3770002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_DLC 0x82 3870002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2) 3970002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1) 4070002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0) 41ae0d7cbcSPaul Burton /* General Configuration */ 42ae0d7cbcSPaul Burton #define PIIX4_FUNC0_GENCFG 0xb0 43ae0d7cbcSPaul Burton #define PIIX4_FUNC0_GENCFG_SERIRQ (1 << 16) 4470002f76SDeng-Cheng Zhu 4570002f76SDeng-Cheng Zhu /* IDE Timing */ 4670002f76SDeng-Cheng Zhu #define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40 4770002f76SDeng-Cheng Zhu #define PIIX4_FUNC1_IDETIM_PRIMARY_HI 0x41 4870002f76SDeng-Cheng Zhu #define PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN (1 << 7) 4970002f76SDeng-Cheng Zhu #define PIIX4_FUNC1_IDETIM_SECONDARY_LO 0x42 5070002f76SDeng-Cheng Zhu #define PIIX4_FUNC1_IDETIM_SECONDARY_HI 0x43 5170002f76SDeng-Cheng Zhu #define PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7) 5270002f76SDeng-Cheng Zhu 53*fa12b773SPaul Burton /* Power Management Configuration Space */ 54*fa12b773SPaul Burton #define PIIX4_FUNC3_PMBA 0x40 55*fa12b773SPaul Burton #define PIIX4_FUNC3_PMREGMISC 0x80 56*fa12b773SPaul Burton #define PIIX4_FUNC3_PMREGMISC_EN (1 << 0) 57*fa12b773SPaul Burton 58384740dcSRalf Baechle #endif /* __ASM_MIPS_BOARDS_PIIX4_H */ 59