1*41173abcSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2384740dcSRalf Baechle /* 3384740dcSRalf Baechle * Carsten Langgaard, carstenl@mips.com 4384740dcSRalf Baechle * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 570002f76SDeng-Cheng Zhu * Copyright (C) 2013 Imagination Technologies Ltd. 6384740dcSRalf Baechle * 7384740dcSRalf Baechle * Register definitions for Intel PIIX4 South Bridge Device. 8384740dcSRalf Baechle */ 9384740dcSRalf Baechle #ifndef __ASM_MIPS_BOARDS_PIIX4_H 10384740dcSRalf Baechle #define __ASM_MIPS_BOARDS_PIIX4_H 11384740dcSRalf Baechle 1270002f76SDeng-Cheng Zhu /* PIRQX Route Control */ 1370002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_PIRQRC 0x60 1470002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7) 1570002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf 1670002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16 17ae0d7cbcSPaul Burton /* SERIRQ Control */ 18ae0d7cbcSPaul Burton #define PIIX4_FUNC0_SERIRQC 0x64 19ae0d7cbcSPaul Burton #define PIIX4_FUNC0_SERIRQC_EN (1 << 7) 20ae0d7cbcSPaul Burton #define PIIX4_FUNC0_SERIRQC_CONT (1 << 6) 2170002f76SDeng-Cheng Zhu /* Top Of Memory */ 2270002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_TOM 0x69 2370002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0 2470002f76SDeng-Cheng Zhu /* Deterministic Latency Control */ 2570002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_DLC 0x82 2670002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2) 2770002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1) 2870002f76SDeng-Cheng Zhu #define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0) 29ae0d7cbcSPaul Burton /* General Configuration */ 30ae0d7cbcSPaul Burton #define PIIX4_FUNC0_GENCFG 0xb0 31ae0d7cbcSPaul Burton #define PIIX4_FUNC0_GENCFG_SERIRQ (1 << 16) 3270002f76SDeng-Cheng Zhu 3370002f76SDeng-Cheng Zhu /* IDE Timing */ 3470002f76SDeng-Cheng Zhu #define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40 3570002f76SDeng-Cheng Zhu #define PIIX4_FUNC1_IDETIM_PRIMARY_HI 0x41 3670002f76SDeng-Cheng Zhu #define PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN (1 << 7) 3770002f76SDeng-Cheng Zhu #define PIIX4_FUNC1_IDETIM_SECONDARY_LO 0x42 3870002f76SDeng-Cheng Zhu #define PIIX4_FUNC1_IDETIM_SECONDARY_HI 0x43 3970002f76SDeng-Cheng Zhu #define PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7) 4070002f76SDeng-Cheng Zhu 41fa12b773SPaul Burton /* Power Management Configuration Space */ 42fa12b773SPaul Burton #define PIIX4_FUNC3_PMBA 0x40 43fa12b773SPaul Burton #define PIIX4_FUNC3_PMREGMISC 0x80 44fa12b773SPaul Burton #define PIIX4_FUNC3_PMREGMISC_EN (1 << 0) 45fa12b773SPaul Burton 46643c5705SPaul Burton /* Power Management IO Space */ 47643c5705SPaul Burton #define PIIX4_FUNC3IO_PMSTS 0x00 48643c5705SPaul Burton #define PIIX4_FUNC3IO_PMSTS_PWRBTN_STS (1 << 8) 49643c5705SPaul Burton #define PIIX4_FUNC3IO_PMCNTRL 0x04 50643c5705SPaul Burton #define PIIX4_FUNC3IO_PMCNTRL_SUS_EN (1 << 13) 51643c5705SPaul Burton #define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP (0x7 << 10) 52643c5705SPaul Burton #define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF (0x0 << 10) 53643c5705SPaul Burton #define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_STR (0x1 << 10) 54643c5705SPaul Burton 55643c5705SPaul Burton /* Data for magic special PCI cycle */ 56643c5705SPaul Burton #define PIIX4_SUSPEND_MAGIC 0x00120002 57643c5705SPaul Burton 58384740dcSRalf Baechle #endif /* __ASM_MIPS_BOARDS_PIIX4_H */ 59