1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved. 7 * Carsten Langgaard <carstenl@mips.com> 8 * Steven J. Hill <sjhill@mips.com> 9 */ 10 #ifndef _MIPS_MALTAINT_H 11 #define _MIPS_MALTAINT_H 12 13 #include <linux/irqchip/mips-gic.h> 14 15 /* 16 * Interrupts 0..15 are used for Malta ISA compatible interrupts 17 */ 18 #define MALTA_INT_BASE 0 19 20 /* CPU interrupt offsets */ 21 #define MIPSCPU_INT_SW0 0 22 #define MIPSCPU_INT_SW1 1 23 #define MIPSCPU_INT_MB0 2 24 #define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 25 #define MIPSCPU_INT_GIC MIPSCPU_INT_MB0 /* GIC chained interrupt */ 26 #define MIPSCPU_INT_MB1 3 27 #define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 28 #define MIPSCPU_INT_MB2 4 29 #define MIPSCPU_INT_MB3 5 30 #define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 31 #define MIPSCPU_INT_MB4 6 32 #define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 33 34 /* 35 * Interrupts 96..127 are used for Soc-it Classic interrupts 36 */ 37 #define MSC01C_INT_BASE 96 38 39 /* SOC-it Classic interrupt offsets */ 40 #define MSC01C_INT_TMR 0 41 #define MSC01C_INT_PCI 1 42 43 /* 44 * Interrupts 96..127 are used for Soc-it EIC interrupts 45 */ 46 #define MSC01E_INT_BASE 96 47 48 /* SOC-it EIC interrupt offsets */ 49 #define MSC01E_INT_SW0 1 50 #define MSC01E_INT_SW1 2 51 #define MSC01E_INT_MB0 3 52 #define MSC01E_INT_I8259A MSC01E_INT_MB0 53 #define MSC01E_INT_MB1 4 54 #define MSC01E_INT_SMI MSC01E_INT_MB1 55 #define MSC01E_INT_MB2 5 56 #define MSC01E_INT_MB3 6 57 #define MSC01E_INT_COREHI MSC01E_INT_MB3 58 #define MSC01E_INT_MB4 7 59 #define MSC01E_INT_CORELO MSC01E_INT_MB4 60 #define MSC01E_INT_TMR 8 61 #define MSC01E_INT_PCI 9 62 #define MSC01E_INT_PERFCTR 10 63 #define MSC01E_INT_CPUCTR 11 64 65 /* GIC external interrupts */ 66 #define GIC_INT_I8259A GIC_SHARED_TO_HWIRQ(3) 67 68 #endif /* !(_MIPS_MALTAINT_H) */ 69