1384740dcSRalf Baechle /* 20b271f56SSteven J. Hill * This file is subject to the terms and conditions of the GNU General Public 30b271f56SSteven J. Hill * License. See the file "COPYING" in the main directory of this archive 4384740dcSRalf Baechle * for more details. 5384740dcSRalf Baechle * 60b271f56SSteven J. Hill * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved. 70b271f56SSteven J. Hill * Carsten Langgaard <carstenl@mips.com> 80b271f56SSteven J. Hill * Steven J. Hill <sjhill@mips.com> 9384740dcSRalf Baechle */ 10384740dcSRalf Baechle #ifndef _MIPS_MALTAINT_H 11384740dcSRalf Baechle #define _MIPS_MALTAINT_H 12384740dcSRalf Baechle 130b271f56SSteven J. Hill #define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) 14384740dcSRalf Baechle 15384740dcSRalf Baechle /* 16384740dcSRalf Baechle * Interrupts 0..15 are used for Malta ISA compatible interrupts 17384740dcSRalf Baechle */ 18384740dcSRalf Baechle #define MALTA_INT_BASE 0 19384740dcSRalf Baechle 20384740dcSRalf Baechle /* CPU interrupt offsets */ 21384740dcSRalf Baechle #define MIPSCPU_INT_SW0 0 22384740dcSRalf Baechle #define MIPSCPU_INT_SW1 1 23384740dcSRalf Baechle #define MIPSCPU_INT_MB0 2 24384740dcSRalf Baechle #define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 25384740dcSRalf Baechle #define MIPSCPU_INT_MB1 3 26384740dcSRalf Baechle #define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 27384740dcSRalf Baechle #define MIPSCPU_INT_IPI0 MIPSCPU_INT_MB1 /* GIC IPI */ 28384740dcSRalf Baechle #define MIPSCPU_INT_MB2 4 29384740dcSRalf Baechle #define MIPSCPU_INT_IPI1 MIPSCPU_INT_MB2 /* GIC IPI */ 30384740dcSRalf Baechle #define MIPSCPU_INT_MB3 5 31384740dcSRalf Baechle #define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 32384740dcSRalf Baechle #define MIPSCPU_INT_MB4 6 33384740dcSRalf Baechle #define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 34384740dcSRalf Baechle 35384740dcSRalf Baechle /* 36*aa827b74SAndrew Bresticker * Interrupts 96..127 are used for Soc-it Classic interrupts 37384740dcSRalf Baechle */ 38*aa827b74SAndrew Bresticker #define MSC01C_INT_BASE 96 39384740dcSRalf Baechle 40384740dcSRalf Baechle /* SOC-it Classic interrupt offsets */ 41384740dcSRalf Baechle #define MSC01C_INT_TMR 0 42384740dcSRalf Baechle #define MSC01C_INT_PCI 1 43384740dcSRalf Baechle 44384740dcSRalf Baechle /* 45*aa827b74SAndrew Bresticker * Interrupts 96..127 are used for Soc-it EIC interrupts 46384740dcSRalf Baechle */ 47*aa827b74SAndrew Bresticker #define MSC01E_INT_BASE 96 48384740dcSRalf Baechle 49384740dcSRalf Baechle /* SOC-it EIC interrupt offsets */ 50384740dcSRalf Baechle #define MSC01E_INT_SW0 1 51384740dcSRalf Baechle #define MSC01E_INT_SW1 2 52384740dcSRalf Baechle #define MSC01E_INT_MB0 3 53384740dcSRalf Baechle #define MSC01E_INT_I8259A MSC01E_INT_MB0 54384740dcSRalf Baechle #define MSC01E_INT_MB1 4 55384740dcSRalf Baechle #define MSC01E_INT_SMI MSC01E_INT_MB1 56384740dcSRalf Baechle #define MSC01E_INT_MB2 5 57384740dcSRalf Baechle #define MSC01E_INT_MB3 6 58384740dcSRalf Baechle #define MSC01E_INT_COREHI MSC01E_INT_MB3 59384740dcSRalf Baechle #define MSC01E_INT_MB4 7 60384740dcSRalf Baechle #define MSC01E_INT_CORELO MSC01E_INT_MB4 61384740dcSRalf Baechle #define MSC01E_INT_TMR 8 62384740dcSRalf Baechle #define MSC01E_INT_PCI 9 63384740dcSRalf Baechle #define MSC01E_INT_PERFCTR 10 64384740dcSRalf Baechle #define MSC01E_INT_CPUCTR 11 65384740dcSRalf Baechle 66384740dcSRalf Baechle /* External Interrupts used for IPI */ 67384740dcSRalf Baechle #define GIC_IPI_EXT_INTR_RESCHED_VPE0 16 68384740dcSRalf Baechle #define GIC_IPI_EXT_INTR_CALLFNC_VPE0 17 69384740dcSRalf Baechle #define GIC_IPI_EXT_INTR_RESCHED_VPE1 18 70384740dcSRalf Baechle #define GIC_IPI_EXT_INTR_CALLFNC_VPE1 19 71384740dcSRalf Baechle #define GIC_IPI_EXT_INTR_RESCHED_VPE2 20 72384740dcSRalf Baechle #define GIC_IPI_EXT_INTR_CALLFNC_VPE2 21 73384740dcSRalf Baechle #define GIC_IPI_EXT_INTR_RESCHED_VPE3 22 74384740dcSRalf Baechle #define GIC_IPI_EXT_INTR_CALLFNC_VPE3 23 75384740dcSRalf Baechle 76384740dcSRalf Baechle #endif /* !(_MIPS_MALTAINT_H) */ 77