1*384740dcSRalf Baechle /* 2*384740dcSRalf Baechle * Carsten Langgaard, carstenl@mips.com 3*384740dcSRalf Baechle * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 4*384740dcSRalf Baechle * 5*384740dcSRalf Baechle * This program is free software; you can distribute it and/or modify it 6*384740dcSRalf Baechle * under the terms of the GNU General Public License (Version 2) as 7*384740dcSRalf Baechle * published by the Free Software Foundation. 8*384740dcSRalf Baechle * 9*384740dcSRalf Baechle * This program is distributed in the hope it will be useful, but WITHOUT 10*384740dcSRalf Baechle * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*384740dcSRalf Baechle * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12*384740dcSRalf Baechle * for more details. 13*384740dcSRalf Baechle * 14*384740dcSRalf Baechle * You should have received a copy of the GNU General Public License along 15*384740dcSRalf Baechle * with this program; if not, write to the Free Software Foundation, Inc., 16*384740dcSRalf Baechle * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17*384740dcSRalf Baechle * 18*384740dcSRalf Baechle * Defines of the Malta board specific address-MAP, registers, etc. 19*384740dcSRalf Baechle */ 20*384740dcSRalf Baechle #ifndef __ASM_MIPS_BOARDS_MALTA_H 21*384740dcSRalf Baechle #define __ASM_MIPS_BOARDS_MALTA_H 22*384740dcSRalf Baechle 23*384740dcSRalf Baechle #include <asm/addrspace.h> 24*384740dcSRalf Baechle #include <asm/io.h> 25*384740dcSRalf Baechle #include <asm/mips-boards/msc01_pci.h> 26*384740dcSRalf Baechle #include <asm/gt64120.h> 27*384740dcSRalf Baechle 28*384740dcSRalf Baechle /* Mips interrupt controller found in SOCit variations */ 29*384740dcSRalf Baechle #define MIPS_MSC01_IC_REG_BASE 0x1bc40000 30*384740dcSRalf Baechle #define MIPS_SOCITSC_IC_REG_BASE 0x1ffa0000 31*384740dcSRalf Baechle 32*384740dcSRalf Baechle /* 33*384740dcSRalf Baechle * Malta I/O ports base address for the Galileo GT64120 and Algorithmics 34*384740dcSRalf Baechle * Bonito system controllers. 35*384740dcSRalf Baechle */ 36*384740dcSRalf Baechle #define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS) 37*384740dcSRalf Baechle #define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000)) 38*384740dcSRalf Baechle #define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL) 39*384740dcSRalf Baechle 40*384740dcSRalf Baechle static inline unsigned long get_gt_port_base(unsigned long reg) 41*384740dcSRalf Baechle { 42*384740dcSRalf Baechle unsigned long addr; 43*384740dcSRalf Baechle addr = GT_READ(reg); 44*384740dcSRalf Baechle return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000); 45*384740dcSRalf Baechle } 46*384740dcSRalf Baechle 47*384740dcSRalf Baechle static inline unsigned long get_msc_port_base(unsigned long reg) 48*384740dcSRalf Baechle { 49*384740dcSRalf Baechle unsigned long addr; 50*384740dcSRalf Baechle MSC_READ(reg, addr); 51*384740dcSRalf Baechle return (unsigned long) ioremap(addr, 0x10000); 52*384740dcSRalf Baechle } 53*384740dcSRalf Baechle 54*384740dcSRalf Baechle /* 55*384740dcSRalf Baechle * GCMP Specific definitions 56*384740dcSRalf Baechle */ 57*384740dcSRalf Baechle #define GCMP_BASE_ADDR 0x1fbf8000 58*384740dcSRalf Baechle #define GCMP_ADDRSPACE_SZ (256 * 1024) 59*384740dcSRalf Baechle 60*384740dcSRalf Baechle /* 61*384740dcSRalf Baechle * GIC Specific definitions 62*384740dcSRalf Baechle */ 63*384740dcSRalf Baechle #define GIC_BASE_ADDR 0x1bdc0000 64*384740dcSRalf Baechle #define GIC_ADDRSPACE_SZ (128 * 1024) 65*384740dcSRalf Baechle 66*384740dcSRalf Baechle /* 67*384740dcSRalf Baechle * MSC01 BIU Specific definitions 68*384740dcSRalf Baechle * FIXME : These should be elsewhere ? 69*384740dcSRalf Baechle */ 70*384740dcSRalf Baechle #define MSC01_BIU_REG_BASE 0x1bc80000 71*384740dcSRalf Baechle #define MSC01_BIU_ADDRSPACE_SZ (256 * 1024) 72*384740dcSRalf Baechle #define MSC01_SC_CFG_OFS 0x0110 73*384740dcSRalf Baechle #define MSC01_SC_CFG_GICPRES_MSK 0x00000004 74*384740dcSRalf Baechle #define MSC01_SC_CFG_GICPRES_SHF 2 75*384740dcSRalf Baechle #define MSC01_SC_CFG_GICENA_SHF 3 76*384740dcSRalf Baechle 77*384740dcSRalf Baechle /* 78*384740dcSRalf Baechle * Malta RTC-device indirect register access. 79*384740dcSRalf Baechle */ 80*384740dcSRalf Baechle #define MALTA_RTC_ADR_REG 0x70 81*384740dcSRalf Baechle #define MALTA_RTC_DAT_REG 0x71 82*384740dcSRalf Baechle 83*384740dcSRalf Baechle /* 84*384740dcSRalf Baechle * Malta SMSC FDC37M817 Super I/O Controller register. 85*384740dcSRalf Baechle */ 86*384740dcSRalf Baechle #define SMSC_CONFIG_REG 0x3f0 87*384740dcSRalf Baechle #define SMSC_DATA_REG 0x3f1 88*384740dcSRalf Baechle 89*384740dcSRalf Baechle #define SMSC_CONFIG_DEVNUM 0x7 90*384740dcSRalf Baechle #define SMSC_CONFIG_ACTIVATE 0x30 91*384740dcSRalf Baechle #define SMSC_CONFIG_ENTER 0x55 92*384740dcSRalf Baechle #define SMSC_CONFIG_EXIT 0xaa 93*384740dcSRalf Baechle 94*384740dcSRalf Baechle #define SMSC_CONFIG_DEVNUM_FLOPPY 0 95*384740dcSRalf Baechle 96*384740dcSRalf Baechle #define SMSC_CONFIG_ACTIVATE_ENABLE 1 97*384740dcSRalf Baechle 98*384740dcSRalf Baechle #define SMSC_WRITE(x, a) outb(x, a) 99*384740dcSRalf Baechle 100*384740dcSRalf Baechle #define MALTA_JMPRS_REG 0x1f000210 101*384740dcSRalf Baechle 102*384740dcSRalf Baechle #endif /* __ASM_MIPS_BOARDS_MALTA_H */ 103