xref: /linux/arch/mips/include/asm/mach-rc32434/irq.h (revision c4ee0af3fa0dc65f690fc908f02b8355f9576ea0)
1 #ifndef __ASM_RC32434_IRQ_H
2 #define __ASM_RC32434_IRQ_H
3 
4 #define NR_IRQS 256
5 
6 #include <asm/mach-generic/irq.h>
7 #include <asm/mach-rc32434/rb.h>
8 
9 /* Interrupt Controller */
10 #define IC_GROUP0_PEND		(REGBASE + 0x38000)
11 #define IC_GROUP0_MASK		(REGBASE + 0x38008)
12 #define IC_GROUP_OFFSET		0x0C
13 
14 #define NUM_INTR_GROUPS		5
15 
16 /* 16550 UARTs */
17 #define GROUP0_IRQ_BASE		8	/* GRP2 IRQ numbers start here */
18 					/* GRP3 IRQ numbers start here */
19 #define GROUP1_IRQ_BASE		(GROUP0_IRQ_BASE + 32)
20 					/* GRP4 IRQ numbers start here */
21 #define GROUP2_IRQ_BASE		(GROUP1_IRQ_BASE + 32)
22 					/* GRP5 IRQ numbers start here */
23 #define GROUP3_IRQ_BASE		(GROUP2_IRQ_BASE + 32)
24 #define GROUP4_IRQ_BASE		(GROUP3_IRQ_BASE + 32)
25 
26 #define UART0_IRQ		(GROUP3_IRQ_BASE + 0)
27 
28 #define ETH0_DMA_RX_IRQ		(GROUP1_IRQ_BASE + 0)
29 #define ETH0_DMA_TX_IRQ		(GROUP1_IRQ_BASE + 1)
30 #define ETH0_RX_OVR_IRQ		(GROUP3_IRQ_BASE + 9)
31 #define ETH0_TX_UND_IRQ		(GROUP3_IRQ_BASE + 10)
32 
33 #define GPIO_MAPPED_IRQ_BASE	GROUP4_IRQ_BASE
34 #define GPIO_MAPPED_IRQ_GROUP	4
35 
36 #endif	/* __ASM_RC32434_IRQ_H */
37