xref: /linux/arch/mips/include/asm/mach-rc32434/gpio.h (revision ca55b2fef3a9373fcfc30f82fd26bc7fccbda732)
1 /*
2  * Copyright 2002 Integrated Device Technology, Inc.
3  *	All rights reserved.
4  *
5  * GPIO register definition.
6  *
7  * Author : ryan.holmQVist@idt.com
8  * Date	  : 20011005
9  * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
10  * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
11  */
12 
13 #ifndef _RC32434_GPIO_H_
14 #define _RC32434_GPIO_H_
15 
16 struct rb532_gpio_reg {
17 	u32   gpiofunc;	  /* GPIO Function Register
18 			   * gpiofunc[x]==0 bit = gpio
19 			   * func[x]==1	 bit = altfunc
20 			   */
21 	u32   gpiocfg;	  /* GPIO Configuration Register
22 			   * gpiocfg[x]==0 bit = input
23 			   * gpiocfg[x]==1 bit = output
24 			   */
25 	u32   gpiod;	  /* GPIO Data Register
26 			   * gpiod[x] read/write gpio pinX status
27 			   */
28 	u32   gpioilevel; /* GPIO Interrupt Status Register
29 			   * interrupt level (see gpioistat)
30 			   */
31 	u32   gpioistat;  /* Gpio Interrupt Status Register
32 			   * istat[x] = (gpiod[x] == level[x])
33 			   * cleared in ISR (STICKY bits)
34 			   */
35 	u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
36 };
37 
38 /* UART GPIO signals */
39 #define RC32434_UART0_SOUT	(1 << 0)
40 #define RC32434_UART0_SIN	(1 << 1)
41 #define RC32434_UART0_RTS	(1 << 2)
42 #define RC32434_UART0_CTS	(1 << 3)
43 
44 /* M & P bus GPIO signals */
45 #define RC32434_MP_BIT_22	(1 << 4)
46 #define RC32434_MP_BIT_23	(1 << 5)
47 #define RC32434_MP_BIT_24	(1 << 6)
48 #define RC32434_MP_BIT_25	(1 << 7)
49 
50 /* CPU GPIO signals */
51 #define RC32434_CPU_GPIO	(1 << 8)
52 
53 /* Reserved GPIO signals */
54 #define RC32434_AF_SPARE_6	(1 << 9)
55 #define RC32434_AF_SPARE_4	(1 << 10)
56 #define RC32434_AF_SPARE_3	(1 << 11)
57 #define RC32434_AF_SPARE_2	(1 << 12)
58 
59 /* PCI messaging unit */
60 #define RC32434_PCI_MSU_GPIO	(1 << 13)
61 
62 /* NAND GPIO signals */
63 #define GPIO_RDY		8
64 #define GPIO_WPX	9
65 #define GPIO_ALE		10
66 #define GPIO_CLE		11
67 
68 /* Compact Flash GPIO pin */
69 #define CF_GPIO_NUM		13
70 
71 /* S1 button GPIO (shared with UART0_SIN) */
72 #define GPIO_BTN_S1		1
73 
74 extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
75 extern void rb532_gpio_set_istat(int bit, unsigned gpio);
76 extern void rb532_gpio_set_func(unsigned gpio);
77 
78 #endif /* _RC32434_GPIO_H_ */
79