1*04dc82e1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 22572f00dSJoshua Henderson /* 32572f00dSJoshua Henderson * Joshua Henderson <joshua.henderson@microchip.com> 42572f00dSJoshua Henderson * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. 52572f00dSJoshua Henderson */ 62572f00dSJoshua Henderson #ifndef _ASM_MACH_PIC32_H 72572f00dSJoshua Henderson #define _ASM_MACH_PIC32_H 82572f00dSJoshua Henderson 92572f00dSJoshua Henderson #include <linux/io.h> 102572f00dSJoshua Henderson 112572f00dSJoshua Henderson /* 122572f00dSJoshua Henderson * PIC32 register offsets for SET/CLR/INV where supported. 132572f00dSJoshua Henderson */ 142572f00dSJoshua Henderson #define PIC32_CLR(_reg) ((_reg) + 0x04) 152572f00dSJoshua Henderson #define PIC32_SET(_reg) ((_reg) + 0x08) 162572f00dSJoshua Henderson #define PIC32_INV(_reg) ((_reg) + 0x0C) 172572f00dSJoshua Henderson 182572f00dSJoshua Henderson /* 192572f00dSJoshua Henderson * PIC32 Base Register Offsets 202572f00dSJoshua Henderson */ 212572f00dSJoshua Henderson #define PIC32_BASE_CONFIG 0x1f800000 222572f00dSJoshua Henderson #define PIC32_BASE_OSC 0x1f801200 232572f00dSJoshua Henderson #define PIC32_BASE_RESET 0x1f801240 242572f00dSJoshua Henderson #define PIC32_BASE_PPS 0x1f801400 252572f00dSJoshua Henderson #define PIC32_BASE_UART 0x1f822000 262572f00dSJoshua Henderson #define PIC32_BASE_PORT 0x1f860000 272572f00dSJoshua Henderson #define PIC32_BASE_DEVCFG2 0x1fc4ff44 282572f00dSJoshua Henderson 292572f00dSJoshua Henderson /* 302572f00dSJoshua Henderson * Register unlock sequence required for some register access. 312572f00dSJoshua Henderson */ 322572f00dSJoshua Henderson void pic32_syskey_unlock_debug(const char *fn, const ulong ln); 332572f00dSJoshua Henderson #define pic32_syskey_unlock() \ 342572f00dSJoshua Henderson pic32_syskey_unlock_debug(__func__, __LINE__) 352572f00dSJoshua Henderson 362572f00dSJoshua Henderson #endif /* _ASM_MACH_PIC32_H */ 37