1 /* 2 * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com> 3 * 4 * Loongson 1 MUX Register Definitions. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12 #ifndef __ASM_MACH_LOONGSON32_REGS_MUX_H 13 #define __ASM_MACH_LOONGSON32_REGS_MUX_H 14 15 #define LS1X_MUX_REG(x) \ 16 ((void __iomem *)KSEG1ADDR(LS1X_MUX_BASE + (x))) 17 18 #define LS1X_MUX_CTRL0 LS1X_MUX_REG(0x0) 19 #define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4) 20 21 #if defined(CONFIG_LOONGSON1_LS1B) 22 /* MUX CTRL0 Register Bits */ 23 #define UART0_USE_PWM23 BIT(28) 24 #define UART0_USE_PWM01 BIT(27) 25 #define UART1_USE_LCD0_5_6_11 BIT(26) 26 #define I2C2_USE_CAN1 BIT(25) 27 #define I2C1_USE_CAN0 BIT(24) 28 #define NAND3_USE_UART5 BIT(23) 29 #define NAND3_USE_UART4 BIT(22) 30 #define NAND3_USE_UART1_DAT BIT(21) 31 #define NAND3_USE_UART1_CTS BIT(20) 32 #define NAND3_USE_PWM23 BIT(19) 33 #define NAND3_USE_PWM01 BIT(18) 34 #define NAND2_USE_UART5 BIT(17) 35 #define NAND2_USE_UART4 BIT(16) 36 #define NAND2_USE_UART1_DAT BIT(15) 37 #define NAND2_USE_UART1_CTS BIT(14) 38 #define NAND2_USE_PWM23 BIT(13) 39 #define NAND2_USE_PWM01 BIT(12) 40 #define NAND1_USE_UART5 BIT(11) 41 #define NAND1_USE_UART4 BIT(10) 42 #define NAND1_USE_UART1_DAT BIT(9) 43 #define NAND1_USE_UART1_CTS BIT(8) 44 #define NAND1_USE_PWM23 BIT(7) 45 #define NAND1_USE_PWM01 BIT(6) 46 #define GMAC1_USE_UART1 BIT(4) 47 #define GMAC1_USE_UART0 BIT(3) 48 #define LCD_USE_UART0_DAT BIT(2) 49 #define LCD_USE_UART15 BIT(1) 50 #define LCD_USE_UART0 BIT(0) 51 52 /* MUX CTRL1 Register Bits */ 53 #define USB_RESET BIT(31) 54 #define SPI1_CS_USE_PWM01 BIT(24) 55 #define SPI1_USE_CAN BIT(23) 56 #define DISABLE_DDR_CONFSPACE BIT(20) 57 #define DDR32TO16EN BIT(16) 58 #define GMAC1_SHUT BIT(13) 59 #define GMAC0_SHUT BIT(12) 60 #define USB_SHUT BIT(11) 61 #define UART1_3_USE_CAN1 BIT(5) 62 #define UART1_2_USE_CAN0 BIT(4) 63 #define GMAC1_USE_TXCLK BIT(3) 64 #define GMAC0_USE_TXCLK BIT(2) 65 #define GMAC1_USE_PWM23 BIT(1) 66 #define GMAC0_USE_PWM01 BIT(0) 67 68 #elif defined(CONFIG_LOONGSON1_LS1C) 69 70 /* SHUT_CTRL Register Bits */ 71 #define UART_SPLIT GENMASK(31, 30) 72 #define OUTPUT_CLK GENMASK(29, 26) 73 #define ADC_SHUT BIT(25) 74 #define SDIO_SHUT BIT(24) 75 #define DMA2_SHUT BIT(23) 76 #define DMA1_SHUT BIT(22) 77 #define DMA0_SHUT BIT(21) 78 #define SPI1_SHUT BIT(20) 79 #define SPI0_SHUT BIT(19) 80 #define I2C2_SHUT BIT(18) 81 #define I2C1_SHUT BIT(17) 82 #define I2C0_SHUT BIT(16) 83 #define AC97_SHUT BIT(15) 84 #define I2S_SHUT BIT(14) 85 #define UART3_SHUT BIT(13) 86 #define UART2_SHUT BIT(12) 87 #define UART1_SHUT BIT(11) 88 #define UART0_SHUT BIT(10) 89 #define CAN1_SHUT BIT(9) 90 #define CAN0_SHUT BIT(8) 91 #define ECC_SHUT BIT(7) 92 #define GMAC_SHUT BIT(6) 93 #define USBHOST_SHUT BIT(5) 94 #define USBOTG_SHUT BIT(4) 95 #define SDRAM_SHUT BIT(3) 96 #define SRAM_SHUT BIT(2) 97 #define CAM_SHUT BIT(1) 98 #define LCD_SHUT BIT(0) 99 100 #define UART_SPLIT_SHIFT 30 101 #define OUTPUT_CLK_SHIFT 26 102 103 /* MISC_CTRL Register Bits */ 104 #define USBHOST_RSTN BIT(31) 105 #define PHY_INTF_SELI GENMASK(30, 28) 106 #define AC97_EN BIT(25) 107 #define SDIO_DMA_EN GENMASK(24, 23) 108 #define ADC_DMA_EN BIT(22) 109 #define SDIO_USE_SPI1 BIT(17) 110 #define SDIO_USE_SPI0 BIT(16) 111 #define SRAM_CTRL GENMASK(15, 0) 112 113 #define PHY_INTF_SELI_SHIFT 28 114 #define SDIO_DMA_EN_SHIFT 23 115 #define SRAM_CTRL_SHIFT 0 116 117 #define LS1X_CBUS_REG(n, x) \ 118 ((void __iomem *)KSEG1ADDR(LS1X_CBUS_BASE + (n * 0x04) + (x))) 119 120 #define LS1X_CBUS_FIRST(n) LS1X_CBUS_REG(n, 0x00) 121 #define LS1X_CBUS_SECOND(n) LS1X_CBUS_REG(n, 0x10) 122 #define LS1X_CBUS_THIRD(n) LS1X_CBUS_REG(n, 0x20) 123 #define LS1X_CBUS_FOURTHT(n) LS1X_CBUS_REG(n, 0x30) 124 #define LS1X_CBUS_FIFTHT(n) LS1X_CBUS_REG(n, 0x40) 125 126 #endif 127 128 #endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */ 129