1 /* 2 * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com> 3 * 4 * Loongson 1 MUX Register Definitions. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12 #ifndef __ASM_MACH_LOONGSON32_REGS_MUX_H 13 #define __ASM_MACH_LOONGSON32_REGS_MUX_H 14 15 #define LS1X_MUX_REG(x) \ 16 ((void __iomem *)KSEG1ADDR(LS1X_MUX_BASE + (x))) 17 18 #define LS1X_MUX_CTRL0 LS1X_MUX_REG(0x0) 19 #define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4) 20 21 /* MUX CTRL0 Register Bits */ 22 #define UART0_USE_PWM23 BIT(28) 23 #define UART0_USE_PWM01 BIT(27) 24 #define UART1_USE_LCD0_5_6_11 BIT(26) 25 #define I2C2_USE_CAN1 BIT(25) 26 #define I2C1_USE_CAN0 BIT(24) 27 #define NAND3_USE_UART5 BIT(23) 28 #define NAND3_USE_UART4 BIT(22) 29 #define NAND3_USE_UART1_DAT BIT(21) 30 #define NAND3_USE_UART1_CTS BIT(20) 31 #define NAND3_USE_PWM23 BIT(19) 32 #define NAND3_USE_PWM01 BIT(18) 33 #define NAND2_USE_UART5 BIT(17) 34 #define NAND2_USE_UART4 BIT(16) 35 #define NAND2_USE_UART1_DAT BIT(15) 36 #define NAND2_USE_UART1_CTS BIT(14) 37 #define NAND2_USE_PWM23 BIT(13) 38 #define NAND2_USE_PWM01 BIT(12) 39 #define NAND1_USE_UART5 BIT(11) 40 #define NAND1_USE_UART4 BIT(10) 41 #define NAND1_USE_UART1_DAT BIT(9) 42 #define NAND1_USE_UART1_CTS BIT(8) 43 #define NAND1_USE_PWM23 BIT(7) 44 #define NAND1_USE_PWM01 BIT(6) 45 #define GMAC1_USE_UART1 BIT(4) 46 #define GMAC1_USE_UART0 BIT(3) 47 #define LCD_USE_UART0_DAT BIT(2) 48 #define LCD_USE_UART15 BIT(1) 49 #define LCD_USE_UART0 BIT(0) 50 51 /* MUX CTRL1 Register Bits */ 52 #define USB_RESET BIT(31) 53 #define SPI1_CS_USE_PWM01 BIT(24) 54 #define SPI1_USE_CAN BIT(23) 55 #define DISABLE_DDR_CONFSPACE BIT(20) 56 #define DDR32TO16EN BIT(16) 57 #define GMAC1_SHUT BIT(13) 58 #define GMAC0_SHUT BIT(12) 59 #define USB_SHUT BIT(11) 60 #define UART1_3_USE_CAN1 BIT(5) 61 #define UART1_2_USE_CAN0 BIT(4) 62 #define GMAC1_USE_TXCLK BIT(3) 63 #define GMAC0_USE_TXCLK BIT(2) 64 #define GMAC1_USE_PWM23 BIT(1) 65 #define GMAC0_USE_PWM01 BIT(0) 66 67 #endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */ 68