1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com> 4 * 5 * Loongson 1 MUX Register Definitions. 6 */ 7 8 #ifndef __ASM_MACH_LOONGSON32_REGS_MUX_H 9 #define __ASM_MACH_LOONGSON32_REGS_MUX_H 10 11 #define LS1X_MUX_REG(x) \ 12 ((void __iomem *)KSEG1ADDR(LS1X_MUX_BASE + (x))) 13 14 #define LS1X_MUX_CTRL0 LS1X_MUX_REG(0x0) 15 #define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4) 16 17 #if defined(CONFIG_LOONGSON1_LS1B) 18 /* MUX CTRL0 Register Bits */ 19 #define UART0_USE_PWM23 BIT(28) 20 #define UART0_USE_PWM01 BIT(27) 21 #define UART1_USE_LCD0_5_6_11 BIT(26) 22 #define I2C2_USE_CAN1 BIT(25) 23 #define I2C1_USE_CAN0 BIT(24) 24 #define NAND3_USE_UART5 BIT(23) 25 #define NAND3_USE_UART4 BIT(22) 26 #define NAND3_USE_UART1_DAT BIT(21) 27 #define NAND3_USE_UART1_CTS BIT(20) 28 #define NAND3_USE_PWM23 BIT(19) 29 #define NAND3_USE_PWM01 BIT(18) 30 #define NAND2_USE_UART5 BIT(17) 31 #define NAND2_USE_UART4 BIT(16) 32 #define NAND2_USE_UART1_DAT BIT(15) 33 #define NAND2_USE_UART1_CTS BIT(14) 34 #define NAND2_USE_PWM23 BIT(13) 35 #define NAND2_USE_PWM01 BIT(12) 36 #define NAND1_USE_UART5 BIT(11) 37 #define NAND1_USE_UART4 BIT(10) 38 #define NAND1_USE_UART1_DAT BIT(9) 39 #define NAND1_USE_UART1_CTS BIT(8) 40 #define NAND1_USE_PWM23 BIT(7) 41 #define NAND1_USE_PWM01 BIT(6) 42 #define GMAC1_USE_UART1 BIT(4) 43 #define GMAC1_USE_UART0 BIT(3) 44 #define LCD_USE_UART0_DAT BIT(2) 45 #define LCD_USE_UART15 BIT(1) 46 #define LCD_USE_UART0 BIT(0) 47 48 /* MUX CTRL1 Register Bits */ 49 #define USB_RESET BIT(31) 50 #define SPI1_CS_USE_PWM01 BIT(24) 51 #define SPI1_USE_CAN BIT(23) 52 #define DISABLE_DDR_CONFSPACE BIT(20) 53 #define DDR32TO16EN BIT(16) 54 #define GMAC1_SHUT BIT(13) 55 #define GMAC0_SHUT BIT(12) 56 #define USB_SHUT BIT(11) 57 #define UART1_3_USE_CAN1 BIT(5) 58 #define UART1_2_USE_CAN0 BIT(4) 59 #define GMAC1_USE_TXCLK BIT(3) 60 #define GMAC0_USE_TXCLK BIT(2) 61 #define GMAC1_USE_PWM23 BIT(1) 62 #define GMAC0_USE_PWM01 BIT(0) 63 64 #elif defined(CONFIG_LOONGSON1_LS1C) 65 66 /* SHUT_CTRL Register Bits */ 67 #define UART_SPLIT GENMASK(31, 30) 68 #define OUTPUT_CLK GENMASK(29, 26) 69 #define ADC_SHUT BIT(25) 70 #define SDIO_SHUT BIT(24) 71 #define DMA2_SHUT BIT(23) 72 #define DMA1_SHUT BIT(22) 73 #define DMA0_SHUT BIT(21) 74 #define SPI1_SHUT BIT(20) 75 #define SPI0_SHUT BIT(19) 76 #define I2C2_SHUT BIT(18) 77 #define I2C1_SHUT BIT(17) 78 #define I2C0_SHUT BIT(16) 79 #define AC97_SHUT BIT(15) 80 #define I2S_SHUT BIT(14) 81 #define UART3_SHUT BIT(13) 82 #define UART2_SHUT BIT(12) 83 #define UART1_SHUT BIT(11) 84 #define UART0_SHUT BIT(10) 85 #define CAN1_SHUT BIT(9) 86 #define CAN0_SHUT BIT(8) 87 #define ECC_SHUT BIT(7) 88 #define GMAC_SHUT BIT(6) 89 #define USBHOST_SHUT BIT(5) 90 #define USBOTG_SHUT BIT(4) 91 #define SDRAM_SHUT BIT(3) 92 #define SRAM_SHUT BIT(2) 93 #define CAM_SHUT BIT(1) 94 #define LCD_SHUT BIT(0) 95 96 #define UART_SPLIT_SHIFT 30 97 #define OUTPUT_CLK_SHIFT 26 98 99 /* MISC_CTRL Register Bits */ 100 #define USBHOST_RSTN BIT(31) 101 #define PHY_INTF_SELI GENMASK(30, 28) 102 #define AC97_EN BIT(25) 103 #define SDIO_DMA_EN GENMASK(24, 23) 104 #define ADC_DMA_EN BIT(22) 105 #define SDIO_USE_SPI1 BIT(17) 106 #define SDIO_USE_SPI0 BIT(16) 107 #define SRAM_CTRL GENMASK(15, 0) 108 109 #define PHY_INTF_SELI_SHIFT 28 110 #define SDIO_DMA_EN_SHIFT 23 111 #define SRAM_CTRL_SHIFT 0 112 113 #define LS1X_CBUS_REG(n, x) \ 114 ((void __iomem *)KSEG1ADDR(LS1X_CBUS_BASE + (n * 0x04) + (x))) 115 116 #define LS1X_CBUS_FIRST(n) LS1X_CBUS_REG(n, 0x00) 117 #define LS1X_CBUS_SECOND(n) LS1X_CBUS_REG(n, 0x10) 118 #define LS1X_CBUS_THIRD(n) LS1X_CBUS_REG(n, 0x20) 119 #define LS1X_CBUS_FOURTHT(n) LS1X_CBUS_REG(n, 0x30) 120 #define LS1X_CBUS_FIFTHT(n) LS1X_CBUS_REG(n, 0x40) 121 122 #endif 123 124 #endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */ 125