1*30ad29bbSHuacai Chen /* 2*30ad29bbSHuacai Chen * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> 3*30ad29bbSHuacai Chen * 4*30ad29bbSHuacai Chen * IRQ mappings for Loongson 1 5*30ad29bbSHuacai Chen * 6*30ad29bbSHuacai Chen * This program is free software; you can redistribute it and/or modify it 7*30ad29bbSHuacai Chen * under the terms of the GNU General Public License as published by the 8*30ad29bbSHuacai Chen * Free Software Foundation; either version 2 of the License, or (at your 9*30ad29bbSHuacai Chen * option) any later version. 10*30ad29bbSHuacai Chen */ 11*30ad29bbSHuacai Chen 12*30ad29bbSHuacai Chen 13*30ad29bbSHuacai Chen #ifndef __ASM_MACH_LOONGSON32_IRQ_H 14*30ad29bbSHuacai Chen #define __ASM_MACH_LOONGSON32_IRQ_H 15*30ad29bbSHuacai Chen 16*30ad29bbSHuacai Chen /* 17*30ad29bbSHuacai Chen * CPU core Interrupt Numbers 18*30ad29bbSHuacai Chen */ 19*30ad29bbSHuacai Chen #define MIPS_CPU_IRQ_BASE 0 20*30ad29bbSHuacai Chen #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) 21*30ad29bbSHuacai Chen 22*30ad29bbSHuacai Chen #define SOFTINT0_IRQ MIPS_CPU_IRQ(0) 23*30ad29bbSHuacai Chen #define SOFTINT1_IRQ MIPS_CPU_IRQ(1) 24*30ad29bbSHuacai Chen #define INT0_IRQ MIPS_CPU_IRQ(2) 25*30ad29bbSHuacai Chen #define INT1_IRQ MIPS_CPU_IRQ(3) 26*30ad29bbSHuacai Chen #define INT2_IRQ MIPS_CPU_IRQ(4) 27*30ad29bbSHuacai Chen #define INT3_IRQ MIPS_CPU_IRQ(5) 28*30ad29bbSHuacai Chen #define INT4_IRQ MIPS_CPU_IRQ(6) 29*30ad29bbSHuacai Chen #define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */ 30*30ad29bbSHuacai Chen 31*30ad29bbSHuacai Chen #define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE) 32*30ad29bbSHuacai Chen 33*30ad29bbSHuacai Chen /* 34*30ad29bbSHuacai Chen * INT0~3 Interrupt Numbers 35*30ad29bbSHuacai Chen */ 36*30ad29bbSHuacai Chen #define LS1X_IRQ_BASE MIPS_CPU_IRQS 37*30ad29bbSHuacai Chen #define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x)) 38*30ad29bbSHuacai Chen 39*30ad29bbSHuacai Chen #define LS1X_UART0_IRQ LS1X_IRQ(0, 2) 40*30ad29bbSHuacai Chen #define LS1X_UART1_IRQ LS1X_IRQ(0, 3) 41*30ad29bbSHuacai Chen #define LS1X_UART2_IRQ LS1X_IRQ(0, 4) 42*30ad29bbSHuacai Chen #define LS1X_UART3_IRQ LS1X_IRQ(0, 5) 43*30ad29bbSHuacai Chen #define LS1X_CAN0_IRQ LS1X_IRQ(0, 6) 44*30ad29bbSHuacai Chen #define LS1X_CAN1_IRQ LS1X_IRQ(0, 7) 45*30ad29bbSHuacai Chen #define LS1X_SPI0_IRQ LS1X_IRQ(0, 8) 46*30ad29bbSHuacai Chen #define LS1X_SPI1_IRQ LS1X_IRQ(0, 9) 47*30ad29bbSHuacai Chen #define LS1X_AC97_IRQ LS1X_IRQ(0, 10) 48*30ad29bbSHuacai Chen #define LS1X_DMA0_IRQ LS1X_IRQ(0, 13) 49*30ad29bbSHuacai Chen #define LS1X_DMA1_IRQ LS1X_IRQ(0, 14) 50*30ad29bbSHuacai Chen #define LS1X_DMA2_IRQ LS1X_IRQ(0, 15) 51*30ad29bbSHuacai Chen #define LS1X_PWM0_IRQ LS1X_IRQ(0, 17) 52*30ad29bbSHuacai Chen #define LS1X_PWM1_IRQ LS1X_IRQ(0, 18) 53*30ad29bbSHuacai Chen #define LS1X_PWM2_IRQ LS1X_IRQ(0, 19) 54*30ad29bbSHuacai Chen #define LS1X_PWM3_IRQ LS1X_IRQ(0, 20) 55*30ad29bbSHuacai Chen #define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21) 56*30ad29bbSHuacai Chen #define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22) 57*30ad29bbSHuacai Chen #define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23) 58*30ad29bbSHuacai Chen #define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24) 59*30ad29bbSHuacai Chen #define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25) 60*30ad29bbSHuacai Chen #define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26) 61*30ad29bbSHuacai Chen #define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27) 62*30ad29bbSHuacai Chen #define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28) 63*30ad29bbSHuacai Chen 64*30ad29bbSHuacai Chen #define LS1X_EHCI_IRQ LS1X_IRQ(1, 0) 65*30ad29bbSHuacai Chen #define LS1X_OHCI_IRQ LS1X_IRQ(1, 1) 66*30ad29bbSHuacai Chen #define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2) 67*30ad29bbSHuacai Chen #define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3) 68*30ad29bbSHuacai Chen 69*30ad29bbSHuacai Chen #define LS1X_IRQS (LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE) 70*30ad29bbSHuacai Chen 71*30ad29bbSHuacai Chen #define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS) 72*30ad29bbSHuacai Chen 73*30ad29bbSHuacai Chen #endif /* __ASM_MACH_LOONGSON32_IRQ_H */ 74