145051539SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2dfec1a82SJohn Crispin /* 3dfec1a82SJohn Crispin * 497b92108SJohn Crispin * Copyright (C) 2011 John Crispin <john@phrozen.org> 5dfec1a82SJohn Crispin */ 6dfec1a82SJohn Crispin 7dfec1a82SJohn Crispin #ifndef LTQ_DMA_H__ 8dfec1a82SJohn Crispin #define LTQ_DMA_H__ 9dfec1a82SJohn Crispin 10dfec1a82SJohn Crispin #define LTQ_DESC_SIZE 0x08 /* each descriptor is 64bit */ 11*5112e923SAleksander Jan Bajkowski #define LTQ_DESC_NUM 0xC0 /* 192 descriptors / channel */ 12dfec1a82SJohn Crispin 13dfec1a82SJohn Crispin #define LTQ_DMA_OWN BIT(31) /* owner bit */ 14dfec1a82SJohn Crispin #define LTQ_DMA_C BIT(30) /* complete bit */ 15dfec1a82SJohn Crispin #define LTQ_DMA_SOP BIT(29) /* start of packet */ 16dfec1a82SJohn Crispin #define LTQ_DMA_EOP BIT(28) /* end of packet */ 17dfec1a82SJohn Crispin #define LTQ_DMA_TX_OFFSET(x) ((x & 0x1f) << 23) /* data bytes offset */ 18dfec1a82SJohn Crispin #define LTQ_DMA_RX_OFFSET(x) ((x & 0x7) << 23) /* data bytes offset */ 19dfec1a82SJohn Crispin #define LTQ_DMA_SIZE_MASK (0xffff) /* the size field is 16 bit */ 20dfec1a82SJohn Crispin 21dfec1a82SJohn Crispin struct ltq_dma_desc { 22dfec1a82SJohn Crispin u32 ctl; 23dfec1a82SJohn Crispin u32 addr; 24dfec1a82SJohn Crispin }; 25dfec1a82SJohn Crispin 26dfec1a82SJohn Crispin struct ltq_dma_channel { 27dfec1a82SJohn Crispin int nr; /* the channel number */ 28dfec1a82SJohn Crispin int irq; /* the mapped irq */ 29dfec1a82SJohn Crispin int desc; /* the current descriptor */ 30dfec1a82SJohn Crispin struct ltq_dma_desc *desc_base; /* the descriptor base */ 31dfec1a82SJohn Crispin int phys; /* physical addr */ 322d946e5bSHauke Mehrtens struct device *dev; 33dfec1a82SJohn Crispin }; 34dfec1a82SJohn Crispin 35dfec1a82SJohn Crispin enum { 36dfec1a82SJohn Crispin DMA_PORT_ETOP = 0, 37dfec1a82SJohn Crispin DMA_PORT_DEU, 38dfec1a82SJohn Crispin }; 39dfec1a82SJohn Crispin 40dfec1a82SJohn Crispin extern void ltq_dma_enable_irq(struct ltq_dma_channel *ch); 41dfec1a82SJohn Crispin extern void ltq_dma_disable_irq(struct ltq_dma_channel *ch); 42dfec1a82SJohn Crispin extern void ltq_dma_ack_irq(struct ltq_dma_channel *ch); 43dfec1a82SJohn Crispin extern void ltq_dma_open(struct ltq_dma_channel *ch); 44dfec1a82SJohn Crispin extern void ltq_dma_close(struct ltq_dma_channel *ch); 45dfec1a82SJohn Crispin extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch); 46dfec1a82SJohn Crispin extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch); 47dfec1a82SJohn Crispin extern void ltq_dma_free(struct ltq_dma_channel *ch); 4849293bbcSAleksander Jan Bajkowski extern void ltq_dma_init_port(int p, int tx_burst, int rx_burst); 49dfec1a82SJohn Crispin 50dfec1a82SJohn Crispin #endif 51