1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction. 4 * 5 * All Alchemy development boards (except, of course, the weird PB1000) 6 * have a few registers in a CPLD with standardised layout; they mostly 7 * only differ in base address and bit meanings in the RESETS and BOARD 8 * registers. 9 * 10 * All data taken from the official AMD board documentation sheets. 11 */ 12 13 #ifndef _DB1XXX_BCSR_H_ 14 #define _DB1XXX_BCSR_H_ 15 16 17 /* BCSR base addresses on various boards. BCSR base 2 refers to the 18 * physical address of the first HEXLEDS register, which is usually 19 * a variable offset from the WHOAMI register. 20 */ 21 22 /* DB1000, DB1100, DB1500, PB1100, PB1500 */ 23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000 24 #define DB1000_BCSR_HEXLED_OFS 0x01000000 25 26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000 27 #define DB1550_BCSR_HEXLED_OFS 0x00400000 28 29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000 30 #define PB1550_BCSR_HEXLED_OFS 0x00800000 31 32 #define DB1200_BCSR_PHYS_ADDR 0x19800000 33 #define DB1200_BCSR_HEXLED_OFS 0x00400000 34 35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000 36 #define PB1200_BCSR_HEXLED_OFS 0x00400000 37 38 #define DB1300_BCSR_PHYS_ADDR 0x19800000 39 #define DB1300_BCSR_HEXLED_OFS 0x00400000 40 41 enum bcsr_id { 42 /* BCSR base 1 */ 43 BCSR_WHOAMI = 0, 44 BCSR_STATUS, 45 BCSR_SWITCHES, 46 BCSR_RESETS, 47 BCSR_PCMCIA, 48 BCSR_BOARD, 49 BCSR_LEDS, 50 BCSR_SYSTEM, 51 /* Au1200/1300 based boards */ 52 BCSR_INTCLR, 53 BCSR_INTSET, 54 BCSR_MASKCLR, 55 BCSR_MASKSET, 56 BCSR_SIGSTAT, 57 BCSR_INTSTAT, 58 59 /* BCSR base 2 */ 60 BCSR_HEXLEDS, 61 BCSR_RSVD1, 62 BCSR_HEXCLEAR, 63 64 BCSR_CNT, 65 }; 66 67 /* register offsets, valid for all Db1xxx/Pb1xxx boards */ 68 #define BCSR_REG_WHOAMI 0x00 69 #define BCSR_REG_STATUS 0x04 70 #define BCSR_REG_SWITCHES 0x08 71 #define BCSR_REG_RESETS 0x0c 72 #define BCSR_REG_PCMCIA 0x10 73 #define BCSR_REG_BOARD 0x14 74 #define BCSR_REG_LEDS 0x18 75 #define BCSR_REG_SYSTEM 0x1c 76 /* Au1200/Au1300 based boards: CPLD IRQ muxer */ 77 #define BCSR_REG_INTCLR 0x20 78 #define BCSR_REG_INTSET 0x24 79 #define BCSR_REG_MASKCLR 0x28 80 #define BCSR_REG_MASKSET 0x2c 81 #define BCSR_REG_SIGSTAT 0x30 82 #define BCSR_REG_INTSTAT 0x34 83 84 /* hexled control, offset from BCSR base 2 */ 85 #define BCSR_REG_HEXLEDS 0x00 86 #define BCSR_REG_HEXCLEAR 0x08 87 88 /* 89 * Register Bits and Pieces. 90 */ 91 #define BCSR_WHOAMI_DCID(x) ((x) & 0xf) 92 #define BCSR_WHOAMI_CPLD(x) (((x) >> 4) & 0xf) 93 #define BCSR_WHOAMI_BOARD(x) (((x) >> 8) & 0xf) 94 95 /* register "WHOAMI" bits 11:8 identify the board */ 96 enum bcsr_whoami_boards { 97 BCSR_WHOAMI_PB1500 = 1, 98 BCSR_WHOAMI_PB1500R2, 99 BCSR_WHOAMI_PB1100, 100 BCSR_WHOAMI_DB1000, 101 BCSR_WHOAMI_DB1100, 102 BCSR_WHOAMI_DB1500, 103 BCSR_WHOAMI_DB1550, 104 BCSR_WHOAMI_PB1550_DDR, 105 BCSR_WHOAMI_PB1550 = BCSR_WHOAMI_PB1550_DDR, 106 BCSR_WHOAMI_PB1550_SDR, 107 BCSR_WHOAMI_PB1200_DDR1, 108 BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1, 109 BCSR_WHOAMI_PB1200_DDR2, 110 BCSR_WHOAMI_DB1200, 111 BCSR_WHOAMI_DB1300, 112 }; 113 114 /* STATUS reg. Unless otherwise noted, they're valid on all boards. 115 * PB1200 = DB1200. 116 */ 117 #define BCSR_STATUS_PC0VS 0x0003 118 #define BCSR_STATUS_PC1VS 0x000C 119 #define BCSR_STATUS_PC0FI 0x0010 120 #define BCSR_STATUS_PC1FI 0x0020 121 #define BCSR_STATUS_PB1550_SWAPBOOT 0x0040 122 #define BCSR_STATUS_SRAMWIDTH 0x0080 123 #define BCSR_STATUS_FLASHBUSY 0x0100 124 #define BCSR_STATUS_ROMBUSY 0x0400 125 #define BCSR_STATUS_SD0WP 0x0400 /* DB1200/DB1300:SD1 */ 126 #define BCSR_STATUS_SD1WP 0x0800 127 #define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */ 128 #define BCSR_STATUS_DB1000_SWAPBOOT 0x2000 129 #define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200/1300 */ 130 #define BCSR_STATUS_IDECBLID 0x0200 /* DB1200/1300 */ 131 #define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */ 132 #define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */ 133 #define BCSR_STATUS_FLASHDEN 0xC000 134 #define BCSR_STATUS_DB1550_U0RXD 0x1000 /* DB1550 */ 135 #define BCSR_STATUS_DB1550_U3RXD 0x2000 /* DB1550 */ 136 #define BCSR_STATUS_PB1550_U0RXD 0x1000 /* PB1550 */ 137 #define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */ 138 #define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */ 139 140 #define BCSR_STATUS_CFWP 0x4000 /* DB1300 */ 141 #define BCSR_STATUS_USBOCn 0x2000 /* DB1300 */ 142 #define BCSR_STATUS_OTGOCn 0x1000 /* DB1300 */ 143 #define BCSR_STATUS_DCDMARQ 0x0010 /* DB1300 */ 144 #define BCSR_STATUS_IDEDMARQ 0x0020 /* DB1300 */ 145 146 /* DB/PB1000,1100,1500,1550 */ 147 #define BCSR_RESETS_PHY0 0x0001 148 #define BCSR_RESETS_PHY1 0x0002 149 #define BCSR_RESETS_DC 0x0004 150 #define BCSR_RESETS_FIR_SEL 0x2000 151 #define BCSR_RESETS_IRDA_MODE_MASK 0xC000 152 #define BCSR_RESETS_IRDA_MODE_FULL 0x0000 153 #define BCSR_RESETS_PB1550_WSCFSM 0x2000 154 #define BCSR_RESETS_IRDA_MODE_OFF 0x4000 155 #define BCSR_RESETS_IRDA_MODE_2_3 0x8000 156 #define BCSR_RESETS_IRDA_MODE_1_3 0xC000 157 #define BCSR_RESETS_DMAREQ 0x8000 /* PB1550 */ 158 159 #define BCSR_BOARD_PCIM66EN 0x0001 160 #define BCSR_BOARD_SD0PWR 0x0040 161 #define BCSR_BOARD_SD1PWR 0x0080 162 #define BCSR_BOARD_PCIM33 0x0100 163 #define BCSR_BOARD_PCIEXTARB 0x0200 164 #define BCSR_BOARD_GPIO200RST 0x0400 165 #define BCSR_BOARD_PCICLKOUT 0x0800 166 #define BCSR_BOARD_PB1100_SD0PWR 0x0400 167 #define BCSR_BOARD_PB1100_SD1PWR 0x0800 168 #define BCSR_BOARD_PCICFG 0x1000 169 #define BCSR_BOARD_SPISEL 0x2000 /* PB/DB1550 */ 170 #define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */ 171 #define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ 172 173 174 /* DB/PB1200/1300 */ 175 #define BCSR_RESETS_ETH 0x0001 176 #define BCSR_RESETS_CAMERA 0x0002 177 #define BCSR_RESETS_DC 0x0004 178 #define BCSR_RESETS_IDE 0x0008 179 #define BCSR_RESETS_TV 0x0010 /* DB1200/1300 */ 180 /* Not resets but in the same register */ 181 #define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */ 182 #define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */ 183 #define BCSR_RESETS_PSC0MUX 0x1000 184 #define BCSR_RESETS_PSC1MUX 0x2000 185 #define BCSR_RESETS_SPISEL 0x4000 186 #define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */ 187 188 #define BCSR_RESETS_VDDQSHDN 0x0200 /* DB1300 */ 189 #define BCSR_RESETS_OTPPGM 0x0400 /* DB1300 */ 190 #define BCSR_RESETS_OTPSCLK 0x0800 /* DB1300 */ 191 #define BCSR_RESETS_OTPWRPROT 0x1000 /* DB1300 */ 192 #define BCSR_RESETS_OTPCSB 0x2000 /* DB1300 */ 193 #define BCSR_RESETS_OTGPWR 0x4000 /* DB1300 */ 194 #define BCSR_RESETS_USBHPWR 0x8000 /* DB1300 */ 195 196 #define BCSR_BOARD_LCDVEE 0x0001 197 #define BCSR_BOARD_LCDVDD 0x0002 198 #define BCSR_BOARD_LCDBL 0x0004 199 #define BCSR_BOARD_CAMSNAP 0x0010 200 #define BCSR_BOARD_CAMPWR 0x0020 201 #define BCSR_BOARD_SD0PWR 0x0040 202 #define BCSR_BOARD_CAMCS 0x0010 /* DB1300 */ 203 #define BCSR_BOARD_HDMI_DE 0x0040 /* DB1300 */ 204 205 #define BCSR_SWITCHES_DIP 0x00FF 206 #define BCSR_SWITCHES_DIP_1 0x0080 207 #define BCSR_SWITCHES_DIP_2 0x0040 208 #define BCSR_SWITCHES_DIP_3 0x0020 209 #define BCSR_SWITCHES_DIP_4 0x0010 210 #define BCSR_SWITCHES_DIP_5 0x0008 211 #define BCSR_SWITCHES_DIP_6 0x0004 212 #define BCSR_SWITCHES_DIP_7 0x0002 213 #define BCSR_SWITCHES_DIP_8 0x0001 214 #define BCSR_SWITCHES_ROTARY 0x0F00 215 216 217 #define BCSR_PCMCIA_PC0VPP 0x0003 218 #define BCSR_PCMCIA_PC0VCC 0x000C 219 #define BCSR_PCMCIA_PC0DRVEN 0x0010 220 #define BCSR_PCMCIA_PC0RST 0x0080 221 #define BCSR_PCMCIA_PC1VPP 0x0300 222 #define BCSR_PCMCIA_PC1VCC 0x0C00 223 #define BCSR_PCMCIA_PC1DRVEN 0x1000 224 #define BCSR_PCMCIA_PC1RST 0x8000 225 226 227 #define BCSR_LEDS_DECIMALS 0x0003 228 #define BCSR_LEDS_LED0 0x0100 229 #define BCSR_LEDS_LED1 0x0200 230 #define BCSR_LEDS_LED2 0x0400 231 #define BCSR_LEDS_LED3 0x0800 232 233 234 #define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */ 235 #define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */ 236 #define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */ 237 #define BCSR_SYSTEM_DEBUGCSMASK 0x003F /* DB1300 */ 238 #define BCSR_SYSTEM_UDMAMODE 0x0100 /* DB1300 */ 239 #define BCSR_SYSTEM_WAKEONIRQ 0x0200 /* DB1300 */ 240 #define BCSR_SYSTEM_VDDI1300 0x3C00 /* DB1300 */ 241 242 243 244 /* initialize BCSR for a board. Provide the PHYSICAL addresses of both 245 * BCSR spaces. 246 */ 247 void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys); 248 249 /* read a board register */ 250 unsigned short bcsr_read(enum bcsr_id reg); 251 252 /* write to a board register */ 253 void bcsr_write(enum bcsr_id reg, unsigned short val); 254 255 /* modify a register. clear bits set in 'clr', set bits set in 'set' */ 256 void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set); 257 258 /* install CPLD IRQ demuxer (DB1200/PB1200) */ 259 void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq); 260 261 #endif 262