1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef BCM63XX_CPU_H_ 3 #define BCM63XX_CPU_H_ 4 5 #include <linux/types.h> 6 #include <linux/init.h> 7 8 /* 9 * Macro to fetch bcm63xx cpu id and revision, should be optimized at 10 * compile time if only one CPU support is enabled (idea stolen from 11 * arm mach-types) 12 */ 13 #define BCM3368_CPU_ID 0x3368 14 #define BCM6328_CPU_ID 0x6328 15 #define BCM6338_CPU_ID 0x6338 16 #define BCM6345_CPU_ID 0x6345 17 #define BCM6348_CPU_ID 0x6348 18 #define BCM6358_CPU_ID 0x6358 19 #define BCM6362_CPU_ID 0x6362 20 #define BCM6368_CPU_ID 0x6368 21 22 void __init bcm63xx_cpu_init(void); 23 u8 bcm63xx_get_cpu_rev(void); 24 unsigned int bcm63xx_get_cpu_freq(void); 25 26 static inline u16 __pure __bcm63xx_get_cpu_id(const u16 cpu_id) 27 { 28 switch (cpu_id) { 29 #ifdef CONFIG_BCM63XX_CPU_3368 30 case BCM3368_CPU_ID: 31 #endif 32 33 #ifdef CONFIG_BCM63XX_CPU_6328 34 case BCM6328_CPU_ID: 35 #endif 36 37 #ifdef CONFIG_BCM63XX_CPU_6338 38 case BCM6338_CPU_ID: 39 #endif 40 41 #ifdef CONFIG_BCM63XX_CPU_6345 42 case BCM6345_CPU_ID: 43 #endif 44 45 #ifdef CONFIG_BCM63XX_CPU_6348 46 case BCM6348_CPU_ID: 47 #endif 48 49 #ifdef CONFIG_BCM63XX_CPU_6358 50 case BCM6358_CPU_ID: 51 #endif 52 53 #ifdef CONFIG_BCM63XX_CPU_6362 54 case BCM6362_CPU_ID: 55 #endif 56 57 #ifdef CONFIG_BCM63XX_CPU_6368 58 case BCM6368_CPU_ID: 59 #endif 60 break; 61 default: 62 unreachable(); 63 } 64 65 return cpu_id; 66 } 67 68 extern u16 bcm63xx_cpu_id; 69 70 static inline u16 __pure bcm63xx_get_cpu_id(void) 71 { 72 const u16 cpu_id = bcm63xx_cpu_id; 73 74 return __bcm63xx_get_cpu_id(cpu_id); 75 } 76 77 #define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID) 78 #define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID) 79 #define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID) 80 #define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) 81 #define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID) 82 #define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) 83 #define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) 84 #define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) 85 86 /* 87 * While registers sets are (mostly) the same across 63xx CPU, base 88 * address of these sets do change. 89 */ 90 enum bcm63xx_regs_set { 91 RSET_DSL_LMEM = 0, 92 RSET_PERF, 93 RSET_TIMER, 94 RSET_WDT, 95 RSET_UART0, 96 RSET_UART1, 97 RSET_GPIO, 98 RSET_SPI, 99 RSET_HSSPI, 100 RSET_UDC0, 101 RSET_OHCI0, 102 RSET_OHCI_PRIV, 103 RSET_USBH_PRIV, 104 RSET_USBD, 105 RSET_USBDMA, 106 RSET_MPI, 107 RSET_PCMCIA, 108 RSET_PCIE, 109 RSET_DSL, 110 RSET_ENET0, 111 RSET_ENET1, 112 RSET_ENETDMA, 113 RSET_ENETDMAC, 114 RSET_ENETDMAS, 115 RSET_ENETSW, 116 RSET_EHCI0, 117 RSET_SDRAM, 118 RSET_MEMC, 119 RSET_DDR, 120 RSET_M2M, 121 RSET_ATM, 122 RSET_XTM, 123 RSET_XTMDMA, 124 RSET_XTMDMAC, 125 RSET_XTMDMAS, 126 RSET_PCM, 127 RSET_PCMDMA, 128 RSET_PCMDMAC, 129 RSET_PCMDMAS, 130 RSET_RNG, 131 RSET_MISC 132 }; 133 134 #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) 135 #define RSET_DSL_SIZE 4096 136 #define RSET_WDT_SIZE 12 137 #define BCM_6338_RSET_SPI_SIZE 64 138 #define BCM_6348_RSET_SPI_SIZE 64 139 #define BCM_6358_RSET_SPI_SIZE 1804 140 #define BCM_6368_RSET_SPI_SIZE 1804 141 #define RSET_ENET_SIZE 2048 142 #define RSET_ENETDMA_SIZE 256 143 #define RSET_6345_ENETDMA_SIZE 64 144 #define RSET_ENETDMAC_SIZE(chans) (16 * (chans)) 145 #define RSET_ENETDMAS_SIZE(chans) (16 * (chans)) 146 #define RSET_ENETSW_SIZE 65536 147 #define RSET_UART_SIZE 24 148 #define RSET_HSSPI_SIZE 1536 149 #define RSET_UDC_SIZE 256 150 #define RSET_OHCI_SIZE 256 151 #define RSET_EHCI_SIZE 256 152 #define RSET_USBD_SIZE 256 153 #define RSET_USBDMA_SIZE 1280 154 #define RSET_PCMCIA_SIZE 12 155 #define RSET_M2M_SIZE 256 156 #define RSET_ATM_SIZE 4096 157 #define RSET_XTM_SIZE 10240 158 #define RSET_XTMDMA_SIZE 256 159 #define RSET_XTMDMAC_SIZE(chans) (16 * (chans)) 160 #define RSET_XTMDMAS_SIZE(chans) (16 * (chans)) 161 #define RSET_RNG_SIZE 20 162 163 /* 164 * 3368 register sets base address 165 */ 166 #define BCM_3368_DSL_LMEM_BASE (0xdeadbeef) 167 #define BCM_3368_PERF_BASE (0xfff8c000) 168 #define BCM_3368_TIMER_BASE (0xfff8c040) 169 #define BCM_3368_WDT_BASE (0xfff8c080) 170 #define BCM_3368_UART0_BASE (0xfff8c100) 171 #define BCM_3368_UART1_BASE (0xfff8c120) 172 #define BCM_3368_GPIO_BASE (0xfff8c080) 173 #define BCM_3368_SPI_BASE (0xfff8c800) 174 #define BCM_3368_HSSPI_BASE (0xdeadbeef) 175 #define BCM_3368_UDC0_BASE (0xdeadbeef) 176 #define BCM_3368_USBDMA_BASE (0xdeadbeef) 177 #define BCM_3368_OHCI0_BASE (0xdeadbeef) 178 #define BCM_3368_OHCI_PRIV_BASE (0xdeadbeef) 179 #define BCM_3368_USBH_PRIV_BASE (0xdeadbeef) 180 #define BCM_3368_USBD_BASE (0xdeadbeef) 181 #define BCM_3368_MPI_BASE (0xfff80000) 182 #define BCM_3368_PCMCIA_BASE (0xfff80054) 183 #define BCM_3368_PCIE_BASE (0xdeadbeef) 184 #define BCM_3368_SDRAM_REGS_BASE (0xdeadbeef) 185 #define BCM_3368_DSL_BASE (0xdeadbeef) 186 #define BCM_3368_UBUS_BASE (0xdeadbeef) 187 #define BCM_3368_ENET0_BASE (0xfff98000) 188 #define BCM_3368_ENET1_BASE (0xfff98800) 189 #define BCM_3368_ENETDMA_BASE (0xfff99800) 190 #define BCM_3368_ENETDMAC_BASE (0xfff99900) 191 #define BCM_3368_ENETDMAS_BASE (0xfff99a00) 192 #define BCM_3368_ENETSW_BASE (0xdeadbeef) 193 #define BCM_3368_EHCI0_BASE (0xdeadbeef) 194 #define BCM_3368_SDRAM_BASE (0xdeadbeef) 195 #define BCM_3368_MEMC_BASE (0xfff84000) 196 #define BCM_3368_DDR_BASE (0xdeadbeef) 197 #define BCM_3368_M2M_BASE (0xdeadbeef) 198 #define BCM_3368_ATM_BASE (0xdeadbeef) 199 #define BCM_3368_XTM_BASE (0xdeadbeef) 200 #define BCM_3368_XTMDMA_BASE (0xdeadbeef) 201 #define BCM_3368_XTMDMAC_BASE (0xdeadbeef) 202 #define BCM_3368_XTMDMAS_BASE (0xdeadbeef) 203 #define BCM_3368_PCM_BASE (0xfff9c200) 204 #define BCM_3368_PCMDMA_BASE (0xdeadbeef) 205 #define BCM_3368_PCMDMAC_BASE (0xdeadbeef) 206 #define BCM_3368_PCMDMAS_BASE (0xdeadbeef) 207 #define BCM_3368_RNG_BASE (0xdeadbeef) 208 #define BCM_3368_MISC_BASE (0xdeadbeef) 209 210 /* 211 * 6328 register sets base address 212 */ 213 #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef) 214 #define BCM_6328_PERF_BASE (0xb0000000) 215 #define BCM_6328_TIMER_BASE (0xb0000040) 216 #define BCM_6328_WDT_BASE (0xb000005c) 217 #define BCM_6328_UART0_BASE (0xb0000100) 218 #define BCM_6328_UART1_BASE (0xb0000120) 219 #define BCM_6328_GPIO_BASE (0xb0000080) 220 #define BCM_6328_SPI_BASE (0xdeadbeef) 221 #define BCM_6328_HSSPI_BASE (0xb0001000) 222 #define BCM_6328_UDC0_BASE (0xdeadbeef) 223 #define BCM_6328_USBDMA_BASE (0xb000c000) 224 #define BCM_6328_OHCI0_BASE (0xb0002600) 225 #define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef) 226 #define BCM_6328_USBH_PRIV_BASE (0xb0002700) 227 #define BCM_6328_USBD_BASE (0xb0002400) 228 #define BCM_6328_MPI_BASE (0xdeadbeef) 229 #define BCM_6328_PCMCIA_BASE (0xdeadbeef) 230 #define BCM_6328_PCIE_BASE (0xb0e40000) 231 #define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef) 232 #define BCM_6328_DSL_BASE (0xb0001900) 233 #define BCM_6328_UBUS_BASE (0xdeadbeef) 234 #define BCM_6328_ENET0_BASE (0xdeadbeef) 235 #define BCM_6328_ENET1_BASE (0xdeadbeef) 236 #define BCM_6328_ENETDMA_BASE (0xb000d800) 237 #define BCM_6328_ENETDMAC_BASE (0xb000da00) 238 #define BCM_6328_ENETDMAS_BASE (0xb000dc00) 239 #define BCM_6328_ENETSW_BASE (0xb0e00000) 240 #define BCM_6328_EHCI0_BASE (0xb0002500) 241 #define BCM_6328_SDRAM_BASE (0xdeadbeef) 242 #define BCM_6328_MEMC_BASE (0xdeadbeef) 243 #define BCM_6328_DDR_BASE (0xb0003000) 244 #define BCM_6328_M2M_BASE (0xdeadbeef) 245 #define BCM_6328_ATM_BASE (0xdeadbeef) 246 #define BCM_6328_XTM_BASE (0xdeadbeef) 247 #define BCM_6328_XTMDMA_BASE (0xb000b800) 248 #define BCM_6328_XTMDMAC_BASE (0xdeadbeef) 249 #define BCM_6328_XTMDMAS_BASE (0xdeadbeef) 250 #define BCM_6328_PCM_BASE (0xb000a800) 251 #define BCM_6328_PCMDMA_BASE (0xdeadbeef) 252 #define BCM_6328_PCMDMAC_BASE (0xdeadbeef) 253 #define BCM_6328_PCMDMAS_BASE (0xdeadbeef) 254 #define BCM_6328_RNG_BASE (0xdeadbeef) 255 #define BCM_6328_MISC_BASE (0xb0001800) 256 #define BCM_6328_OTP_BASE (0xb0000600) 257 258 /* 259 * 6338 register sets base address 260 */ 261 #define BCM_6338_DSL_LMEM_BASE (0xfff00000) 262 #define BCM_6338_PERF_BASE (0xfffe0000) 263 #define BCM_6338_BB_BASE (0xfffe0100) 264 #define BCM_6338_TIMER_BASE (0xfffe0200) 265 #define BCM_6338_WDT_BASE (0xfffe021c) 266 #define BCM_6338_UART0_BASE (0xfffe0300) 267 #define BCM_6338_UART1_BASE (0xdeadbeef) 268 #define BCM_6338_GPIO_BASE (0xfffe0400) 269 #define BCM_6338_SPI_BASE (0xfffe0c00) 270 #define BCM_6338_HSSPI_BASE (0xdeadbeef) 271 #define BCM_6338_UDC0_BASE (0xdeadbeef) 272 #define BCM_6338_USBDMA_BASE (0xfffe2400) 273 #define BCM_6338_OHCI0_BASE (0xdeadbeef) 274 #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) 275 #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) 276 #define BCM_6338_USBD_BASE (0xdeadbeef) 277 #define BCM_6338_MPI_BASE (0xfffe3160) 278 #define BCM_6338_PCMCIA_BASE (0xdeadbeef) 279 #define BCM_6338_PCIE_BASE (0xdeadbeef) 280 #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) 281 #define BCM_6338_DSL_BASE (0xfffe1000) 282 #define BCM_6338_UBUS_BASE (0xdeadbeef) 283 #define BCM_6338_ENET0_BASE (0xfffe2800) 284 #define BCM_6338_ENET1_BASE (0xdeadbeef) 285 #define BCM_6338_ENETDMA_BASE (0xfffe2400) 286 #define BCM_6338_ENETDMAC_BASE (0xfffe2500) 287 #define BCM_6338_ENETDMAS_BASE (0xfffe2600) 288 #define BCM_6338_ENETSW_BASE (0xdeadbeef) 289 #define BCM_6338_EHCI0_BASE (0xdeadbeef) 290 #define BCM_6338_SDRAM_BASE (0xfffe3100) 291 #define BCM_6338_MEMC_BASE (0xdeadbeef) 292 #define BCM_6338_DDR_BASE (0xdeadbeef) 293 #define BCM_6338_M2M_BASE (0xdeadbeef) 294 #define BCM_6338_ATM_BASE (0xfffe2000) 295 #define BCM_6338_XTM_BASE (0xdeadbeef) 296 #define BCM_6338_XTMDMA_BASE (0xdeadbeef) 297 #define BCM_6338_XTMDMAC_BASE (0xdeadbeef) 298 #define BCM_6338_XTMDMAS_BASE (0xdeadbeef) 299 #define BCM_6338_PCM_BASE (0xdeadbeef) 300 #define BCM_6338_PCMDMA_BASE (0xdeadbeef) 301 #define BCM_6338_PCMDMAC_BASE (0xdeadbeef) 302 #define BCM_6338_PCMDMAS_BASE (0xdeadbeef) 303 #define BCM_6338_RNG_BASE (0xdeadbeef) 304 #define BCM_6338_MISC_BASE (0xdeadbeef) 305 306 /* 307 * 6345 register sets base address 308 */ 309 #define BCM_6345_DSL_LMEM_BASE (0xfff00000) 310 #define BCM_6345_PERF_BASE (0xfffe0000) 311 #define BCM_6345_BB_BASE (0xfffe0100) 312 #define BCM_6345_TIMER_BASE (0xfffe0200) 313 #define BCM_6345_WDT_BASE (0xfffe021c) 314 #define BCM_6345_UART0_BASE (0xfffe0300) 315 #define BCM_6345_UART1_BASE (0xdeadbeef) 316 #define BCM_6345_GPIO_BASE (0xfffe0400) 317 #define BCM_6345_SPI_BASE (0xdeadbeef) 318 #define BCM_6345_HSSPI_BASE (0xdeadbeef) 319 #define BCM_6345_UDC0_BASE (0xdeadbeef) 320 #define BCM_6345_USBDMA_BASE (0xfffe2800) 321 #define BCM_6345_ENET0_BASE (0xfffe1800) 322 #define BCM_6345_ENETDMA_BASE (0xfffe2800) 323 #define BCM_6345_ENETDMAC_BASE (0xfffe2840) 324 #define BCM_6345_ENETDMAS_BASE (0xfffe2a00) 325 #define BCM_6345_ENETSW_BASE (0xdeadbeef) 326 #define BCM_6345_PCMCIA_BASE (0xfffe2028) 327 #define BCM_6345_MPI_BASE (0xfffe2000) 328 #define BCM_6345_PCIE_BASE (0xdeadbeef) 329 #define BCM_6345_OHCI0_BASE (0xfffe2100) 330 #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) 331 #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) 332 #define BCM_6345_USBD_BASE (0xdeadbeef) 333 #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) 334 #define BCM_6345_DSL_BASE (0xdeadbeef) 335 #define BCM_6345_UBUS_BASE (0xdeadbeef) 336 #define BCM_6345_ENET1_BASE (0xdeadbeef) 337 #define BCM_6345_EHCI0_BASE (0xdeadbeef) 338 #define BCM_6345_SDRAM_BASE (0xfffe2300) 339 #define BCM_6345_MEMC_BASE (0xdeadbeef) 340 #define BCM_6345_DDR_BASE (0xdeadbeef) 341 #define BCM_6345_M2M_BASE (0xdeadbeef) 342 #define BCM_6345_ATM_BASE (0xfffe4000) 343 #define BCM_6345_XTM_BASE (0xdeadbeef) 344 #define BCM_6345_XTMDMA_BASE (0xdeadbeef) 345 #define BCM_6345_XTMDMAC_BASE (0xdeadbeef) 346 #define BCM_6345_XTMDMAS_BASE (0xdeadbeef) 347 #define BCM_6345_PCM_BASE (0xdeadbeef) 348 #define BCM_6345_PCMDMA_BASE (0xdeadbeef) 349 #define BCM_6345_PCMDMAC_BASE (0xdeadbeef) 350 #define BCM_6345_PCMDMAS_BASE (0xdeadbeef) 351 #define BCM_6345_RNG_BASE (0xdeadbeef) 352 #define BCM_6345_MISC_BASE (0xdeadbeef) 353 354 /* 355 * 6348 register sets base address 356 */ 357 #define BCM_6348_DSL_LMEM_BASE (0xfff00000) 358 #define BCM_6348_PERF_BASE (0xfffe0000) 359 #define BCM_6348_TIMER_BASE (0xfffe0200) 360 #define BCM_6348_WDT_BASE (0xfffe021c) 361 #define BCM_6348_UART0_BASE (0xfffe0300) 362 #define BCM_6348_UART1_BASE (0xdeadbeef) 363 #define BCM_6348_GPIO_BASE (0xfffe0400) 364 #define BCM_6348_SPI_BASE (0xfffe0c00) 365 #define BCM_6348_HSSPI_BASE (0xdeadbeef) 366 #define BCM_6348_UDC0_BASE (0xfffe1000) 367 #define BCM_6348_USBDMA_BASE (0xdeadbeef) 368 #define BCM_6348_OHCI0_BASE (0xfffe1b00) 369 #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) 370 #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) 371 #define BCM_6348_USBD_BASE (0xdeadbeef) 372 #define BCM_6348_MPI_BASE (0xfffe2000) 373 #define BCM_6348_PCMCIA_BASE (0xfffe2054) 374 #define BCM_6348_PCIE_BASE (0xdeadbeef) 375 #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) 376 #define BCM_6348_M2M_BASE (0xfffe2800) 377 #define BCM_6348_DSL_BASE (0xfffe3000) 378 #define BCM_6348_ENET0_BASE (0xfffe6000) 379 #define BCM_6348_ENET1_BASE (0xfffe6800) 380 #define BCM_6348_ENETDMA_BASE (0xfffe7000) 381 #define BCM_6348_ENETDMAC_BASE (0xfffe7100) 382 #define BCM_6348_ENETDMAS_BASE (0xfffe7200) 383 #define BCM_6348_ENETSW_BASE (0xdeadbeef) 384 #define BCM_6348_EHCI0_BASE (0xdeadbeef) 385 #define BCM_6348_SDRAM_BASE (0xfffe2300) 386 #define BCM_6348_MEMC_BASE (0xdeadbeef) 387 #define BCM_6348_DDR_BASE (0xdeadbeef) 388 #define BCM_6348_ATM_BASE (0xfffe4000) 389 #define BCM_6348_XTM_BASE (0xdeadbeef) 390 #define BCM_6348_XTMDMA_BASE (0xdeadbeef) 391 #define BCM_6348_XTMDMAC_BASE (0xdeadbeef) 392 #define BCM_6348_XTMDMAS_BASE (0xdeadbeef) 393 #define BCM_6348_PCM_BASE (0xdeadbeef) 394 #define BCM_6348_PCMDMA_BASE (0xdeadbeef) 395 #define BCM_6348_PCMDMAC_BASE (0xdeadbeef) 396 #define BCM_6348_PCMDMAS_BASE (0xdeadbeef) 397 #define BCM_6348_RNG_BASE (0xdeadbeef) 398 #define BCM_6348_MISC_BASE (0xdeadbeef) 399 400 /* 401 * 6358 register sets base address 402 */ 403 #define BCM_6358_DSL_LMEM_BASE (0xfff00000) 404 #define BCM_6358_PERF_BASE (0xfffe0000) 405 #define BCM_6358_TIMER_BASE (0xfffe0040) 406 #define BCM_6358_WDT_BASE (0xfffe005c) 407 #define BCM_6358_UART0_BASE (0xfffe0100) 408 #define BCM_6358_UART1_BASE (0xfffe0120) 409 #define BCM_6358_GPIO_BASE (0xfffe0080) 410 #define BCM_6358_SPI_BASE (0xfffe0800) 411 #define BCM_6358_HSSPI_BASE (0xdeadbeef) 412 #define BCM_6358_UDC0_BASE (0xfffe0800) 413 #define BCM_6358_USBDMA_BASE (0xdeadbeef) 414 #define BCM_6358_OHCI0_BASE (0xfffe1400) 415 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) 416 #define BCM_6358_USBH_PRIV_BASE (0xfffe1500) 417 #define BCM_6358_USBD_BASE (0xdeadbeef) 418 #define BCM_6358_MPI_BASE (0xfffe1000) 419 #define BCM_6358_PCMCIA_BASE (0xfffe1054) 420 #define BCM_6358_PCIE_BASE (0xdeadbeef) 421 #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) 422 #define BCM_6358_M2M_BASE (0xdeadbeef) 423 #define BCM_6358_DSL_BASE (0xfffe3000) 424 #define BCM_6358_ENET0_BASE (0xfffe4000) 425 #define BCM_6358_ENET1_BASE (0xfffe4800) 426 #define BCM_6358_ENETDMA_BASE (0xfffe5000) 427 #define BCM_6358_ENETDMAC_BASE (0xfffe5100) 428 #define BCM_6358_ENETDMAS_BASE (0xfffe5200) 429 #define BCM_6358_ENETSW_BASE (0xdeadbeef) 430 #define BCM_6358_EHCI0_BASE (0xfffe1300) 431 #define BCM_6358_SDRAM_BASE (0xdeadbeef) 432 #define BCM_6358_MEMC_BASE (0xfffe1200) 433 #define BCM_6358_DDR_BASE (0xfffe12a0) 434 #define BCM_6358_ATM_BASE (0xfffe2000) 435 #define BCM_6358_XTM_BASE (0xdeadbeef) 436 #define BCM_6358_XTMDMA_BASE (0xdeadbeef) 437 #define BCM_6358_XTMDMAC_BASE (0xdeadbeef) 438 #define BCM_6358_XTMDMAS_BASE (0xdeadbeef) 439 #define BCM_6358_PCM_BASE (0xfffe1600) 440 #define BCM_6358_PCMDMA_BASE (0xfffe1800) 441 #define BCM_6358_PCMDMAC_BASE (0xfffe1900) 442 #define BCM_6358_PCMDMAS_BASE (0xfffe1a00) 443 #define BCM_6358_RNG_BASE (0xdeadbeef) 444 #define BCM_6358_MISC_BASE (0xdeadbeef) 445 446 447 /* 448 * 6362 register sets base address 449 */ 450 #define BCM_6362_DSL_LMEM_BASE (0xdeadbeef) 451 #define BCM_6362_PERF_BASE (0xb0000000) 452 #define BCM_6362_TIMER_BASE (0xb0000040) 453 #define BCM_6362_WDT_BASE (0xb000005c) 454 #define BCM_6362_UART0_BASE (0xb0000100) 455 #define BCM_6362_UART1_BASE (0xb0000120) 456 #define BCM_6362_GPIO_BASE (0xb0000080) 457 #define BCM_6362_SPI_BASE (0xb0000800) 458 #define BCM_6362_HSSPI_BASE (0xb0001000) 459 #define BCM_6362_UDC0_BASE (0xdeadbeef) 460 #define BCM_6362_USBDMA_BASE (0xb000c000) 461 #define BCM_6362_OHCI0_BASE (0xb0002600) 462 #define BCM_6362_OHCI_PRIV_BASE (0xdeadbeef) 463 #define BCM_6362_USBH_PRIV_BASE (0xb0002700) 464 #define BCM_6362_USBD_BASE (0xb0002400) 465 #define BCM_6362_MPI_BASE (0xdeadbeef) 466 #define BCM_6362_PCMCIA_BASE (0xdeadbeef) 467 #define BCM_6362_PCIE_BASE (0xb0e40000) 468 #define BCM_6362_SDRAM_REGS_BASE (0xdeadbeef) 469 #define BCM_6362_DSL_BASE (0xdeadbeef) 470 #define BCM_6362_UBUS_BASE (0xdeadbeef) 471 #define BCM_6362_ENET0_BASE (0xdeadbeef) 472 #define BCM_6362_ENET1_BASE (0xdeadbeef) 473 #define BCM_6362_ENETDMA_BASE (0xb000d800) 474 #define BCM_6362_ENETDMAC_BASE (0xb000da00) 475 #define BCM_6362_ENETDMAS_BASE (0xb000dc00) 476 #define BCM_6362_ENETSW_BASE (0xb0e00000) 477 #define BCM_6362_EHCI0_BASE (0xb0002500) 478 #define BCM_6362_SDRAM_BASE (0xdeadbeef) 479 #define BCM_6362_MEMC_BASE (0xdeadbeef) 480 #define BCM_6362_DDR_BASE (0xb0003000) 481 #define BCM_6362_M2M_BASE (0xdeadbeef) 482 #define BCM_6362_ATM_BASE (0xdeadbeef) 483 #define BCM_6362_XTM_BASE (0xb0007800) 484 #define BCM_6362_XTMDMA_BASE (0xb000b800) 485 #define BCM_6362_XTMDMAC_BASE (0xdeadbeef) 486 #define BCM_6362_XTMDMAS_BASE (0xdeadbeef) 487 #define BCM_6362_PCM_BASE (0xb000a800) 488 #define BCM_6362_PCMDMA_BASE (0xdeadbeef) 489 #define BCM_6362_PCMDMAC_BASE (0xdeadbeef) 490 #define BCM_6362_PCMDMAS_BASE (0xdeadbeef) 491 #define BCM_6362_RNG_BASE (0xdeadbeef) 492 #define BCM_6362_MISC_BASE (0xb0001800) 493 494 #define BCM_6362_NAND_REG_BASE (0xb0000200) 495 #define BCM_6362_NAND_CACHE_BASE (0xb0000600) 496 #define BCM_6362_LED_BASE (0xb0001900) 497 #define BCM_6362_IPSEC_BASE (0xb0002800) 498 #define BCM_6362_IPSEC_DMA_BASE (0xb000d000) 499 #define BCM_6362_WLAN_CHIPCOMMON_BASE (0xb0004000) 500 #define BCM_6362_WLAN_D11_BASE (0xb0005000) 501 #define BCM_6362_WLAN_SHIM_BASE (0xb0007000) 502 503 /* 504 * 6368 register sets base address 505 */ 506 #define BCM_6368_DSL_LMEM_BASE (0xdeadbeef) 507 #define BCM_6368_PERF_BASE (0xb0000000) 508 #define BCM_6368_TIMER_BASE (0xb0000040) 509 #define BCM_6368_WDT_BASE (0xb000005c) 510 #define BCM_6368_UART0_BASE (0xb0000100) 511 #define BCM_6368_UART1_BASE (0xb0000120) 512 #define BCM_6368_GPIO_BASE (0xb0000080) 513 #define BCM_6368_SPI_BASE (0xb0000800) 514 #define BCM_6368_HSSPI_BASE (0xdeadbeef) 515 #define BCM_6368_UDC0_BASE (0xdeadbeef) 516 #define BCM_6368_USBDMA_BASE (0xb0004800) 517 #define BCM_6368_OHCI0_BASE (0xb0001600) 518 #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) 519 #define BCM_6368_USBH_PRIV_BASE (0xb0001700) 520 #define BCM_6368_USBD_BASE (0xb0001400) 521 #define BCM_6368_MPI_BASE (0xb0001000) 522 #define BCM_6368_PCMCIA_BASE (0xb0001054) 523 #define BCM_6368_PCIE_BASE (0xdeadbeef) 524 #define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef) 525 #define BCM_6368_M2M_BASE (0xdeadbeef) 526 #define BCM_6368_DSL_BASE (0xdeadbeef) 527 #define BCM_6368_ENET0_BASE (0xdeadbeef) 528 #define BCM_6368_ENET1_BASE (0xdeadbeef) 529 #define BCM_6368_ENETDMA_BASE (0xb0006800) 530 #define BCM_6368_ENETDMAC_BASE (0xb0006a00) 531 #define BCM_6368_ENETDMAS_BASE (0xb0006c00) 532 #define BCM_6368_ENETSW_BASE (0xb0f00000) 533 #define BCM_6368_EHCI0_BASE (0xb0001500) 534 #define BCM_6368_SDRAM_BASE (0xdeadbeef) 535 #define BCM_6368_MEMC_BASE (0xb0001200) 536 #define BCM_6368_DDR_BASE (0xb0001280) 537 #define BCM_6368_ATM_BASE (0xdeadbeef) 538 #define BCM_6368_XTM_BASE (0xb0001800) 539 #define BCM_6368_XTMDMA_BASE (0xb0005000) 540 #define BCM_6368_XTMDMAC_BASE (0xb0005200) 541 #define BCM_6368_XTMDMAS_BASE (0xb0005400) 542 #define BCM_6368_PCM_BASE (0xb0004000) 543 #define BCM_6368_PCMDMA_BASE (0xb0005800) 544 #define BCM_6368_PCMDMAC_BASE (0xb0005a00) 545 #define BCM_6368_PCMDMAS_BASE (0xb0005c00) 546 #define BCM_6368_RNG_BASE (0xb0004180) 547 #define BCM_6368_MISC_BASE (0xdeadbeef) 548 549 550 extern const unsigned long *bcm63xx_regs_base; 551 552 #define __GEN_CPU_REGS_TABLE(__cpu) \ 553 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \ 554 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \ 555 [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \ 556 [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \ 557 [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \ 558 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ 559 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ 560 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ 561 [RSET_HSSPI] = BCM_## __cpu ##_HSSPI_BASE, \ 562 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ 563 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ 564 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ 565 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \ 566 [RSET_USBD] = BCM_## __cpu ##_USBD_BASE, \ 567 [RSET_USBDMA] = BCM_## __cpu ##_USBDMA_BASE, \ 568 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \ 569 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \ 570 [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \ 571 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \ 572 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \ 573 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \ 574 [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \ 575 [RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \ 576 [RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \ 577 [RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \ 578 [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \ 579 [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \ 580 [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \ 581 [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \ 582 [RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \ 583 [RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \ 584 [RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \ 585 [RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \ 586 [RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \ 587 [RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \ 588 [RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \ 589 [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \ 590 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \ 591 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \ 592 [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \ 593 [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \ 594 595 596 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 597 { 598 return bcm63xx_regs_base[set]; 599 } 600 601 /* 602 * IRQ number changes across CPU too 603 */ 604 enum bcm63xx_irq { 605 IRQ_TIMER = 0, 606 IRQ_SPI, 607 IRQ_UART0, 608 IRQ_UART1, 609 IRQ_DSL, 610 IRQ_ENET0, 611 IRQ_ENET1, 612 IRQ_ENET_PHY, 613 IRQ_HSSPI, 614 IRQ_OHCI0, 615 IRQ_EHCI0, 616 IRQ_USBD, 617 IRQ_USBD_RXDMA0, 618 IRQ_USBD_TXDMA0, 619 IRQ_USBD_RXDMA1, 620 IRQ_USBD_TXDMA1, 621 IRQ_USBD_RXDMA2, 622 IRQ_USBD_TXDMA2, 623 IRQ_ENET0_RXDMA, 624 IRQ_ENET0_TXDMA, 625 IRQ_ENET1_RXDMA, 626 IRQ_ENET1_TXDMA, 627 IRQ_PCI, 628 IRQ_PCMCIA, 629 IRQ_ATM, 630 IRQ_ENETSW_RXDMA0, 631 IRQ_ENETSW_RXDMA1, 632 IRQ_ENETSW_RXDMA2, 633 IRQ_ENETSW_RXDMA3, 634 IRQ_ENETSW_TXDMA0, 635 IRQ_ENETSW_TXDMA1, 636 IRQ_ENETSW_TXDMA2, 637 IRQ_ENETSW_TXDMA3, 638 IRQ_XTM, 639 IRQ_XTM_DMA0, 640 }; 641 642 /* 643 * 3368 irqs 644 */ 645 #define BCM_3368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 646 #define BCM_3368_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 647 #define BCM_3368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 648 #define BCM_3368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 649 #define BCM_3368_DSL_IRQ 0 650 #define BCM_3368_UDC0_IRQ 0 651 #define BCM_3368_OHCI0_IRQ 0 652 #define BCM_3368_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 653 #define BCM_3368_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 654 #define BCM_3368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 655 #define BCM_3368_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 656 #define BCM_3368_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 657 #define BCM_3368_HSSPI_IRQ 0 658 #define BCM_3368_EHCI0_IRQ 0 659 #define BCM_3368_USBD_IRQ 0 660 #define BCM_3368_USBD_RXDMA0_IRQ 0 661 #define BCM_3368_USBD_TXDMA0_IRQ 0 662 #define BCM_3368_USBD_RXDMA1_IRQ 0 663 #define BCM_3368_USBD_TXDMA1_IRQ 0 664 #define BCM_3368_USBD_RXDMA2_IRQ 0 665 #define BCM_3368_USBD_TXDMA2_IRQ 0 666 #define BCM_3368_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 667 #define BCM_3368_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 668 #define BCM_3368_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 669 #define BCM_3368_PCMCIA_IRQ 0 670 #define BCM_3368_ATM_IRQ 0 671 #define BCM_3368_ENETSW_RXDMA0_IRQ 0 672 #define BCM_3368_ENETSW_RXDMA1_IRQ 0 673 #define BCM_3368_ENETSW_RXDMA2_IRQ 0 674 #define BCM_3368_ENETSW_RXDMA3_IRQ 0 675 #define BCM_3368_ENETSW_TXDMA0_IRQ 0 676 #define BCM_3368_ENETSW_TXDMA1_IRQ 0 677 #define BCM_3368_ENETSW_TXDMA2_IRQ 0 678 #define BCM_3368_ENETSW_TXDMA3_IRQ 0 679 #define BCM_3368_XTM_IRQ 0 680 #define BCM_3368_XTM_DMA0_IRQ 0 681 682 #define BCM_3368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25) 683 #define BCM_3368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26) 684 #define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) 685 #define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) 686 687 688 /* 689 * 6328 irqs 690 */ 691 #define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 692 693 #define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31) 694 #define BCM_6328_SPI_IRQ 0 695 #define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28) 696 #define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7) 697 #define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 698 #define BCM_6328_UDC0_IRQ 0 699 #define BCM_6328_ENET0_IRQ 0 700 #define BCM_6328_ENET1_IRQ 0 701 #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 702 #define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29) 703 #define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9) 704 #define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10) 705 #define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4) 706 #define BCM_6328_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5) 707 #define BCM_6328_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6) 708 #define BCM_6328_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7) 709 #define BCM_6328_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8) 710 #define BCM_6328_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9) 711 #define BCM_6328_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10) 712 #define BCM_6328_PCMCIA_IRQ 0 713 #define BCM_6328_ENET0_RXDMA_IRQ 0 714 #define BCM_6328_ENET0_TXDMA_IRQ 0 715 #define BCM_6328_ENET1_RXDMA_IRQ 0 716 #define BCM_6328_ENET1_TXDMA_IRQ 0 717 #define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23) 718 #define BCM_6328_ATM_IRQ 0 719 #define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0) 720 #define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1) 721 #define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2) 722 #define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3) 723 #define BCM_6328_ENETSW_TXDMA0_IRQ 0 724 #define BCM_6328_ENETSW_TXDMA1_IRQ 0 725 #define BCM_6328_ENETSW_TXDMA2_IRQ 0 726 #define BCM_6328_ENETSW_TXDMA3_IRQ 0 727 #define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31) 728 #define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11) 729 730 #define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2) 731 #define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3) 732 #define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24) 733 #define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25) 734 #define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26) 735 #define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27) 736 737 /* 738 * 6338 irqs 739 */ 740 #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 741 #define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 742 #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 743 #define BCM_6338_UART1_IRQ 0 744 #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) 745 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 746 #define BCM_6338_ENET1_IRQ 0 747 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 748 #define BCM_6338_HSSPI_IRQ 0 749 #define BCM_6338_OHCI0_IRQ 0 750 #define BCM_6338_EHCI0_IRQ 0 751 #define BCM_6338_USBD_IRQ 0 752 #define BCM_6338_USBD_RXDMA0_IRQ 0 753 #define BCM_6338_USBD_TXDMA0_IRQ 0 754 #define BCM_6338_USBD_RXDMA1_IRQ 0 755 #define BCM_6338_USBD_TXDMA1_IRQ 0 756 #define BCM_6338_USBD_RXDMA2_IRQ 0 757 #define BCM_6338_USBD_TXDMA2_IRQ 0 758 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 759 #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 760 #define BCM_6338_ENET1_RXDMA_IRQ 0 761 #define BCM_6338_ENET1_TXDMA_IRQ 0 762 #define BCM_6338_PCI_IRQ 0 763 #define BCM_6338_PCMCIA_IRQ 0 764 #define BCM_6338_ATM_IRQ 0 765 #define BCM_6338_ENETSW_RXDMA0_IRQ 0 766 #define BCM_6338_ENETSW_RXDMA1_IRQ 0 767 #define BCM_6338_ENETSW_RXDMA2_IRQ 0 768 #define BCM_6338_ENETSW_RXDMA3_IRQ 0 769 #define BCM_6338_ENETSW_TXDMA0_IRQ 0 770 #define BCM_6338_ENETSW_TXDMA1_IRQ 0 771 #define BCM_6338_ENETSW_TXDMA2_IRQ 0 772 #define BCM_6338_ENETSW_TXDMA3_IRQ 0 773 #define BCM_6338_XTM_IRQ 0 774 #define BCM_6338_XTM_DMA0_IRQ 0 775 776 /* 777 * 6345 irqs 778 */ 779 #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 780 #define BCM_6345_SPI_IRQ 0 781 #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 782 #define BCM_6345_UART1_IRQ 0 783 #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) 784 #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 785 #define BCM_6345_ENET1_IRQ 0 786 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 787 #define BCM_6345_HSSPI_IRQ 0 788 #define BCM_6345_OHCI0_IRQ 0 789 #define BCM_6345_EHCI0_IRQ 0 790 #define BCM_6345_USBD_IRQ 0 791 #define BCM_6345_USBD_RXDMA0_IRQ 0 792 #define BCM_6345_USBD_TXDMA0_IRQ 0 793 #define BCM_6345_USBD_RXDMA1_IRQ 0 794 #define BCM_6345_USBD_TXDMA1_IRQ 0 795 #define BCM_6345_USBD_RXDMA2_IRQ 0 796 #define BCM_6345_USBD_TXDMA2_IRQ 0 797 #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) 798 #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) 799 #define BCM_6345_ENET1_RXDMA_IRQ 0 800 #define BCM_6345_ENET1_TXDMA_IRQ 0 801 #define BCM_6345_PCI_IRQ 0 802 #define BCM_6345_PCMCIA_IRQ 0 803 #define BCM_6345_ATM_IRQ 0 804 #define BCM_6345_ENETSW_RXDMA0_IRQ 0 805 #define BCM_6345_ENETSW_RXDMA1_IRQ 0 806 #define BCM_6345_ENETSW_RXDMA2_IRQ 0 807 #define BCM_6345_ENETSW_RXDMA3_IRQ 0 808 #define BCM_6345_ENETSW_TXDMA0_IRQ 0 809 #define BCM_6345_ENETSW_TXDMA1_IRQ 0 810 #define BCM_6345_ENETSW_TXDMA2_IRQ 0 811 #define BCM_6345_ENETSW_TXDMA3_IRQ 0 812 #define BCM_6345_XTM_IRQ 0 813 #define BCM_6345_XTM_DMA0_IRQ 0 814 815 /* 816 * 6348 irqs 817 */ 818 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 819 #define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 820 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 821 #define BCM_6348_UART1_IRQ 0 822 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 823 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 824 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) 825 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 826 #define BCM_6348_HSSPI_IRQ 0 827 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 828 #define BCM_6348_EHCI0_IRQ 0 829 #define BCM_6348_USBD_IRQ 0 830 #define BCM_6348_USBD_RXDMA0_IRQ 0 831 #define BCM_6348_USBD_TXDMA0_IRQ 0 832 #define BCM_6348_USBD_RXDMA1_IRQ 0 833 #define BCM_6348_USBD_TXDMA1_IRQ 0 834 #define BCM_6348_USBD_RXDMA2_IRQ 0 835 #define BCM_6348_USBD_TXDMA2_IRQ 0 836 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) 837 #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) 838 #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) 839 #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) 840 #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) 841 #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 842 #define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5) 843 #define BCM_6348_ENETSW_RXDMA0_IRQ 0 844 #define BCM_6348_ENETSW_RXDMA1_IRQ 0 845 #define BCM_6348_ENETSW_RXDMA2_IRQ 0 846 #define BCM_6348_ENETSW_RXDMA3_IRQ 0 847 #define BCM_6348_ENETSW_TXDMA0_IRQ 0 848 #define BCM_6348_ENETSW_TXDMA1_IRQ 0 849 #define BCM_6348_ENETSW_TXDMA2_IRQ 0 850 #define BCM_6348_ENETSW_TXDMA3_IRQ 0 851 #define BCM_6348_XTM_IRQ 0 852 #define BCM_6348_XTM_DMA0_IRQ 0 853 854 /* 855 * 6358 irqs 856 */ 857 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 858 #define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 859 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 860 #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 861 #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) 862 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 863 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 864 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 865 #define BCM_6358_HSSPI_IRQ 0 866 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 867 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 868 #define BCM_6358_USBD_IRQ 0 869 #define BCM_6358_USBD_RXDMA0_IRQ 0 870 #define BCM_6358_USBD_TXDMA0_IRQ 0 871 #define BCM_6358_USBD_RXDMA1_IRQ 0 872 #define BCM_6358_USBD_TXDMA1_IRQ 0 873 #define BCM_6358_USBD_RXDMA2_IRQ 0 874 #define BCM_6358_USBD_TXDMA2_IRQ 0 875 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 876 #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 877 #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 878 #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 879 #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 880 #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 881 #define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19) 882 #define BCM_6358_ENETSW_RXDMA0_IRQ 0 883 #define BCM_6358_ENETSW_RXDMA1_IRQ 0 884 #define BCM_6358_ENETSW_RXDMA2_IRQ 0 885 #define BCM_6358_ENETSW_RXDMA3_IRQ 0 886 #define BCM_6358_ENETSW_TXDMA0_IRQ 0 887 #define BCM_6358_ENETSW_TXDMA1_IRQ 0 888 #define BCM_6358_ENETSW_TXDMA2_IRQ 0 889 #define BCM_6358_ENETSW_TXDMA3_IRQ 0 890 #define BCM_6358_XTM_IRQ 0 891 #define BCM_6358_XTM_DMA0_IRQ 0 892 893 #define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23) 894 #define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24) 895 #define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25) 896 #define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26) 897 #define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) 898 #define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) 899 900 /* 901 * 6362 irqs 902 */ 903 #define BCM_6362_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 904 905 #define BCM_6362_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 906 #define BCM_6362_SPI_IRQ (IRQ_INTERNAL_BASE + 2) 907 #define BCM_6362_UART0_IRQ (IRQ_INTERNAL_BASE + 3) 908 #define BCM_6362_UART1_IRQ (IRQ_INTERNAL_BASE + 4) 909 #define BCM_6362_DSL_IRQ (IRQ_INTERNAL_BASE + 28) 910 #define BCM_6362_UDC0_IRQ 0 911 #define BCM_6362_ENET0_IRQ 0 912 #define BCM_6362_ENET1_IRQ 0 913 #define BCM_6362_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 14) 914 #define BCM_6362_HSSPI_IRQ (IRQ_INTERNAL_BASE + 5) 915 #define BCM_6362_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) 916 #define BCM_6362_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 917 #define BCM_6362_USBD_IRQ (IRQ_INTERNAL_BASE + 11) 918 #define BCM_6362_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 20) 919 #define BCM_6362_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 21) 920 #define BCM_6362_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 22) 921 #define BCM_6362_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 23) 922 #define BCM_6362_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 24) 923 #define BCM_6362_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 25) 924 #define BCM_6362_PCMCIA_IRQ 0 925 #define BCM_6362_ENET0_RXDMA_IRQ 0 926 #define BCM_6362_ENET0_TXDMA_IRQ 0 927 #define BCM_6362_ENET1_RXDMA_IRQ 0 928 #define BCM_6362_ENET1_TXDMA_IRQ 0 929 #define BCM_6362_PCI_IRQ (IRQ_INTERNAL_BASE + 30) 930 #define BCM_6362_ATM_IRQ 0 931 #define BCM_6362_ENETSW_RXDMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 0) 932 #define BCM_6362_ENETSW_RXDMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 1) 933 #define BCM_6362_ENETSW_RXDMA2_IRQ (BCM_6362_HIGH_IRQ_BASE + 2) 934 #define BCM_6362_ENETSW_RXDMA3_IRQ (BCM_6362_HIGH_IRQ_BASE + 3) 935 #define BCM_6362_ENETSW_TXDMA0_IRQ 0 936 #define BCM_6362_ENETSW_TXDMA1_IRQ 0 937 #define BCM_6362_ENETSW_TXDMA2_IRQ 0 938 #define BCM_6362_ENETSW_TXDMA3_IRQ 0 939 #define BCM_6362_XTM_IRQ 0 940 #define BCM_6362_XTM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 12) 941 942 #define BCM_6362_RING_OSC_IRQ (IRQ_INTERNAL_BASE + 1) 943 #define BCM_6362_WLAN_GPIO_IRQ (IRQ_INTERNAL_BASE + 6) 944 #define BCM_6362_WLAN_IRQ (IRQ_INTERNAL_BASE + 7) 945 #define BCM_6362_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8) 946 #define BCM_6362_NAND_IRQ (IRQ_INTERNAL_BASE + 12) 947 #define BCM_6362_PCM_IRQ (IRQ_INTERNAL_BASE + 13) 948 #define BCM_6362_DG_IRQ (IRQ_INTERNAL_BASE + 15) 949 #define BCM_6362_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16) 950 #define BCM_6362_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17) 951 #define BCM_6362_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18) 952 #define BCM_6362_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19) 953 #define BCM_6362_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 26) 954 #define BCM_6362_IPSEC_DMA1_IRQ (IRQ_INTERNAL_BASE + 27) 955 #define BCM_6362_FAP0_IRQ (IRQ_INTERNAL_BASE + 29) 956 #define BCM_6362_PCM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 4) 957 #define BCM_6362_PCM_DMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 5) 958 #define BCM_6362_DECT0_IRQ (BCM_6362_HIGH_IRQ_BASE + 6) 959 #define BCM_6362_DECT1_IRQ (BCM_6362_HIGH_IRQ_BASE + 7) 960 #define BCM_6362_EXT_IRQ0 (BCM_6362_HIGH_IRQ_BASE + 8) 961 #define BCM_6362_EXT_IRQ1 (BCM_6362_HIGH_IRQ_BASE + 9) 962 #define BCM_6362_EXT_IRQ2 (BCM_6362_HIGH_IRQ_BASE + 10) 963 #define BCM_6362_EXT_IRQ3 (BCM_6362_HIGH_IRQ_BASE + 11) 964 965 /* 966 * 6368 irqs 967 */ 968 #define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 969 970 #define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 971 #define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 972 #define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 973 #define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 974 #define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 975 #define BCM_6368_ENET0_IRQ 0 976 #define BCM_6368_ENET1_IRQ 0 977 #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) 978 #define BCM_6368_HSSPI_IRQ 0 979 #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 980 #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) 981 #define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8) 982 #define BCM_6368_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 26) 983 #define BCM_6368_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 27) 984 #define BCM_6368_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 28) 985 #define BCM_6368_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 29) 986 #define BCM_6368_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 30) 987 #define BCM_6368_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 31) 988 #define BCM_6368_PCMCIA_IRQ 0 989 #define BCM_6368_ENET0_RXDMA_IRQ 0 990 #define BCM_6368_ENET0_TXDMA_IRQ 0 991 #define BCM_6368_ENET1_RXDMA_IRQ 0 992 #define BCM_6368_ENET1_TXDMA_IRQ 0 993 #define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13) 994 #define BCM_6368_ATM_IRQ 0 995 #define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0) 996 #define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1) 997 #define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2) 998 #define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3) 999 #define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4) 1000 #define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5) 1001 #define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6) 1002 #define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7) 1003 #define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11) 1004 #define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8) 1005 1006 #define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30) 1007 #define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31) 1008 #define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20) 1009 #define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21) 1010 #define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22) 1011 #define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23) 1012 #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24) 1013 #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25) 1014 1015 extern const int *bcm63xx_irqs; 1016 1017 #define __GEN_CPU_IRQ_TABLE(__cpu) \ 1018 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \ 1019 [IRQ_SPI] = BCM_## __cpu ##_SPI_IRQ, \ 1020 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \ 1021 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \ 1022 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \ 1023 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \ 1024 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \ 1025 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ 1026 [IRQ_HSSPI] = BCM_## __cpu ##_HSSPI_IRQ, \ 1027 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ 1028 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ 1029 [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \ 1030 [IRQ_USBD_RXDMA0] = BCM_## __cpu ##_USBD_RXDMA0_IRQ, \ 1031 [IRQ_USBD_TXDMA0] = BCM_## __cpu ##_USBD_TXDMA0_IRQ, \ 1032 [IRQ_USBD_RXDMA1] = BCM_## __cpu ##_USBD_RXDMA1_IRQ, \ 1033 [IRQ_USBD_TXDMA1] = BCM_## __cpu ##_USBD_TXDMA1_IRQ, \ 1034 [IRQ_USBD_RXDMA2] = BCM_## __cpu ##_USBD_RXDMA2_IRQ, \ 1035 [IRQ_USBD_TXDMA2] = BCM_## __cpu ##_USBD_TXDMA2_IRQ, \ 1036 [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \ 1037 [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \ 1038 [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \ 1039 [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \ 1040 [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \ 1041 [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \ 1042 [IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \ 1043 [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \ 1044 [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \ 1045 [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \ 1046 [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \ 1047 [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \ 1048 [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \ 1049 [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \ 1050 [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \ 1051 [IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \ 1052 [IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \ 1053 1054 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) 1055 { 1056 return bcm63xx_irqs[irq]; 1057 } 1058 1059 /* 1060 * return installed memory size 1061 */ 1062 unsigned int bcm63xx_get_memory_size(void); 1063 1064 void bcm63xx_machine_halt(void); 1065 1066 void bcm63xx_machine_reboot(void); 1067 1068 #endif /* !BCM63XX_CPU_H_ */ 1069