1 /* 2 * BRIEF MODULE DESCRIPTION 3 * Defines for using the MMC/SD controllers on the 4 * Alchemy Au1100 mips processor. 5 * 6 * Copyright (c) 2003 Embedded Edge, LLC. 7 * Author: Embedded Edge, LLC. 8 * dan@embeddededge.com or tim@embeddededge.com 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * You should have received a copy of the GNU General Public License along 27 * with this program; if not, write to the Free Software Foundation, Inc., 28 * 675 Mass Ave, Cambridge, MA 02139, USA. 29 * 30 */ 31 /* 32 * AU1100 MMC/SD definitions. 33 * 34 * From "AMD Alchemy Solutions Au1100 Processor Data Book - Preliminary" 35 * June, 2003 36 */ 37 38 #ifndef __ASM_AU1100_MMC_H 39 #define __ASM_AU1100_MMC_H 40 41 #include <linux/leds.h> 42 43 struct au1xmmc_platform_data { 44 int(*cd_setup)(void *mmc_host, int on); 45 int(*card_inserted)(void *mmc_host); 46 int(*card_readonly)(void *mmc_host); 47 void(*set_power)(void *mmc_host, int state); 48 struct led_classdev *led; 49 unsigned long mask_host_caps; 50 }; 51 52 #define SD0_BASE 0xB0600000 53 #define SD1_BASE 0xB0680000 54 55 56 /* 57 * Register offsets. 58 */ 59 #define SD_TXPORT (0x0000) 60 #define SD_RXPORT (0x0004) 61 #define SD_CONFIG (0x0008) 62 #define SD_ENABLE (0x000C) 63 #define SD_CONFIG2 (0x0010) 64 #define SD_BLKSIZE (0x0014) 65 #define SD_STATUS (0x0018) 66 #define SD_DEBUG (0x001C) 67 #define SD_CMD (0x0020) 68 #define SD_CMDARG (0x0024) 69 #define SD_RESP3 (0x0028) 70 #define SD_RESP2 (0x002C) 71 #define SD_RESP1 (0x0030) 72 #define SD_RESP0 (0x0034) 73 #define SD_TIMEOUT (0x0038) 74 75 76 /* 77 * SD_TXPORT bit definitions. 78 */ 79 #define SD_TXPORT_TXD (0x000000ff) 80 81 82 /* 83 * SD_RXPORT bit definitions. 84 */ 85 #define SD_RXPORT_RXD (0x000000ff) 86 87 88 /* 89 * SD_CONFIG bit definitions. 90 */ 91 #define SD_CONFIG_DIV (0x000001ff) 92 #define SD_CONFIG_DE (0x00000200) 93 #define SD_CONFIG_NE (0x00000400) 94 #define SD_CONFIG_TU (0x00000800) 95 #define SD_CONFIG_TO (0x00001000) 96 #define SD_CONFIG_RU (0x00002000) 97 #define SD_CONFIG_RO (0x00004000) 98 #define SD_CONFIG_I (0x00008000) 99 #define SD_CONFIG_CR (0x00010000) 100 #define SD_CONFIG_RAT (0x00020000) 101 #define SD_CONFIG_DD (0x00040000) 102 #define SD_CONFIG_DT (0x00080000) 103 #define SD_CONFIG_SC (0x00100000) 104 #define SD_CONFIG_RC (0x00200000) 105 #define SD_CONFIG_WC (0x00400000) 106 #define SD_CONFIG_xxx (0x00800000) 107 #define SD_CONFIG_TH (0x01000000) 108 #define SD_CONFIG_TE (0x02000000) 109 #define SD_CONFIG_TA (0x04000000) 110 #define SD_CONFIG_RH (0x08000000) 111 #define SD_CONFIG_RA (0x10000000) 112 #define SD_CONFIG_RF (0x20000000) 113 #define SD_CONFIG_CD (0x40000000) 114 #define SD_CONFIG_SI (0x80000000) 115 116 117 /* 118 * SD_ENABLE bit definitions. 119 */ 120 #define SD_ENABLE_CE (0x00000001) 121 #define SD_ENABLE_R (0x00000002) 122 123 124 /* 125 * SD_CONFIG2 bit definitions. 126 */ 127 #define SD_CONFIG2_EN (0x00000001) 128 #define SD_CONFIG2_FF (0x00000002) 129 #define SD_CONFIG2_xx1 (0x00000004) 130 #define SD_CONFIG2_DF (0x00000008) 131 #define SD_CONFIG2_DC (0x00000010) 132 #define SD_CONFIG2_xx2 (0x000000e0) 133 #define SD_CONFIG2_BB (0x00000080) 134 #define SD_CONFIG2_WB (0x00000100) 135 #define SD_CONFIG2_RW (0x00000200) 136 #define SD_CONFIG2_DP (0x00000400) 137 138 139 /* 140 * SD_BLKSIZE bit definitions. 141 */ 142 #define SD_BLKSIZE_BS (0x000007ff) 143 #define SD_BLKSIZE_BS_SHIFT (0) 144 #define SD_BLKSIZE_BC (0x01ff0000) 145 #define SD_BLKSIZE_BC_SHIFT (16) 146 147 148 /* 149 * SD_STATUS bit definitions. 150 */ 151 #define SD_STATUS_DCRCW (0x00000007) 152 #define SD_STATUS_xx1 (0x00000008) 153 #define SD_STATUS_CB (0x00000010) 154 #define SD_STATUS_DB (0x00000020) 155 #define SD_STATUS_CF (0x00000040) 156 #define SD_STATUS_D3 (0x00000080) 157 #define SD_STATUS_xx2 (0x00000300) 158 #define SD_STATUS_NE (0x00000400) 159 #define SD_STATUS_TU (0x00000800) 160 #define SD_STATUS_TO (0x00001000) 161 #define SD_STATUS_RU (0x00002000) 162 #define SD_STATUS_RO (0x00004000) 163 #define SD_STATUS_I (0x00008000) 164 #define SD_STATUS_CR (0x00010000) 165 #define SD_STATUS_RAT (0x00020000) 166 #define SD_STATUS_DD (0x00040000) 167 #define SD_STATUS_DT (0x00080000) 168 #define SD_STATUS_SC (0x00100000) 169 #define SD_STATUS_RC (0x00200000) 170 #define SD_STATUS_WC (0x00400000) 171 #define SD_STATUS_xx3 (0x00800000) 172 #define SD_STATUS_TH (0x01000000) 173 #define SD_STATUS_TE (0x02000000) 174 #define SD_STATUS_TA (0x04000000) 175 #define SD_STATUS_RH (0x08000000) 176 #define SD_STATUS_RA (0x10000000) 177 #define SD_STATUS_RF (0x20000000) 178 #define SD_STATUS_CD (0x40000000) 179 #define SD_STATUS_SI (0x80000000) 180 181 182 /* 183 * SD_CMD bit definitions. 184 */ 185 #define SD_CMD_GO (0x00000001) 186 #define SD_CMD_RY (0x00000002) 187 #define SD_CMD_xx1 (0x0000000c) 188 #define SD_CMD_CT_MASK (0x000000f0) 189 #define SD_CMD_CT_0 (0x00000000) 190 #define SD_CMD_CT_1 (0x00000010) 191 #define SD_CMD_CT_2 (0x00000020) 192 #define SD_CMD_CT_3 (0x00000030) 193 #define SD_CMD_CT_4 (0x00000040) 194 #define SD_CMD_CT_5 (0x00000050) 195 #define SD_CMD_CT_6 (0x00000060) 196 #define SD_CMD_CT_7 (0x00000070) 197 #define SD_CMD_CI (0x0000ff00) 198 #define SD_CMD_CI_SHIFT (8) 199 #define SD_CMD_RT_MASK (0x00ff0000) 200 #define SD_CMD_RT_0 (0x00000000) 201 #define SD_CMD_RT_1 (0x00010000) 202 #define SD_CMD_RT_2 (0x00020000) 203 #define SD_CMD_RT_3 (0x00030000) 204 #define SD_CMD_RT_4 (0x00040000) 205 #define SD_CMD_RT_5 (0x00050000) 206 #define SD_CMD_RT_6 (0x00060000) 207 #define SD_CMD_RT_1B (0x00810000) 208 209 210 #endif /* __ASM_AU1100_MMC_H */ 211