1 /* 2 * 3 * BRIEF MODULE DESCRIPTION 4 * Include file for Alchemy Semiconductor's Au1k CPU. 5 * 6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc. 7 * Author: MontaVista Software, Inc. <source@mvista.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, write to the Free Software Foundation, Inc., 27 * 675 Mass Ave, Cambridge, MA 02139, USA. 28 */ 29 30 /* 31 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp 32 */ 33 34 #ifndef _AU1000_H_ 35 #define _AU1000_H_ 36 37 38 #ifndef _LANGUAGE_ASSEMBLY 39 40 #include <linux/delay.h> 41 #include <linux/types.h> 42 43 #include <linux/io.h> 44 #include <linux/irq.h> 45 46 /* cpu pipeline flush */ 47 void static inline au_sync(void) 48 { 49 __asm__ volatile ("sync"); 50 } 51 52 void static inline au_sync_udelay(int us) 53 { 54 __asm__ volatile ("sync"); 55 udelay(us); 56 } 57 58 void static inline au_sync_delay(int ms) 59 { 60 __asm__ volatile ("sync"); 61 mdelay(ms); 62 } 63 64 void static inline au_writeb(u8 val, unsigned long reg) 65 { 66 *(volatile u8 *)reg = val; 67 } 68 69 void static inline au_writew(u16 val, unsigned long reg) 70 { 71 *(volatile u16 *)reg = val; 72 } 73 74 void static inline au_writel(u32 val, unsigned long reg) 75 { 76 *(volatile u32 *)reg = val; 77 } 78 79 static inline u8 au_readb(unsigned long reg) 80 { 81 return *(volatile u8 *)reg; 82 } 83 84 static inline u16 au_readw(unsigned long reg) 85 { 86 return *(volatile u16 *)reg; 87 } 88 89 static inline u32 au_readl(unsigned long reg) 90 { 91 return *(volatile u32 *)reg; 92 } 93 94 /* Early Au1000 have a write-only SYS_CPUPLL register. */ 95 static inline int au1xxx_cpu_has_pll_wo(void) 96 { 97 switch (read_c0_prid()) { 98 case 0x00030100: /* Au1000 DA */ 99 case 0x00030201: /* Au1000 HA */ 100 case 0x00030202: /* Au1000 HB */ 101 return 1; 102 } 103 return 0; 104 } 105 106 /* does CPU need CONFIG[OD] set to fix tons of errata? */ 107 static inline int au1xxx_cpu_needs_config_od(void) 108 { 109 /* 110 * c0_config.od (bit 19) was write only (and read as 0) on the 111 * early revisions of Alchemy SOCs. It disables the bus trans- 112 * action overlapping and needs to be set to fix various errata. 113 */ 114 switch (read_c0_prid()) { 115 case 0x00030100: /* Au1000 DA */ 116 case 0x00030201: /* Au1000 HA */ 117 case 0x00030202: /* Au1000 HB */ 118 case 0x01030200: /* Au1500 AB */ 119 /* 120 * Au1100/Au1200 errata actually keep silence about this bit, 121 * so we set it just in case for those revisions that require 122 * it to be set according to the (now gone) cpu_table. 123 */ 124 case 0x02030200: /* Au1100 AB */ 125 case 0x02030201: /* Au1100 BA */ 126 case 0x02030202: /* Au1100 BC */ 127 case 0x04030201: /* Au1200 AC */ 128 return 1; 129 } 130 return 0; 131 } 132 133 #define ALCHEMY_CPU_UNKNOWN -1 134 #define ALCHEMY_CPU_AU1000 0 135 #define ALCHEMY_CPU_AU1500 1 136 #define ALCHEMY_CPU_AU1100 2 137 #define ALCHEMY_CPU_AU1550 3 138 #define ALCHEMY_CPU_AU1200 4 139 140 static inline int alchemy_get_cputype(void) 141 { 142 switch (read_c0_prid() & 0xffff0000) { 143 case 0x00030000: 144 return ALCHEMY_CPU_AU1000; 145 break; 146 case 0x01030000: 147 return ALCHEMY_CPU_AU1500; 148 break; 149 case 0x02030000: 150 return ALCHEMY_CPU_AU1100; 151 break; 152 case 0x03030000: 153 return ALCHEMY_CPU_AU1550; 154 break; 155 case 0x04030000: 156 case 0x05030000: 157 return ALCHEMY_CPU_AU1200; 158 break; 159 } 160 161 return ALCHEMY_CPU_UNKNOWN; 162 } 163 164 /* return number of uarts on a given cputype */ 165 static inline int alchemy_get_uarts(int type) 166 { 167 switch (type) { 168 case ALCHEMY_CPU_AU1000: 169 return 4; 170 case ALCHEMY_CPU_AU1500: 171 case ALCHEMY_CPU_AU1200: 172 return 2; 173 case ALCHEMY_CPU_AU1100: 174 case ALCHEMY_CPU_AU1550: 175 return 3; 176 } 177 return 0; 178 } 179 180 /* enable an UART block if it isn't already */ 181 static inline void alchemy_uart_enable(u32 uart_phys) 182 { 183 void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys); 184 185 /* reset, enable clock, deassert reset */ 186 if ((__raw_readl(addr + 0x100) & 3) != 3) { 187 __raw_writel(0, addr + 0x100); 188 wmb(); 189 __raw_writel(1, addr + 0x100); 190 wmb(); 191 } 192 __raw_writel(3, addr + 0x100); 193 wmb(); 194 } 195 196 static inline void alchemy_uart_disable(u32 uart_phys) 197 { 198 void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys); 199 __raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */ 200 wmb(); 201 } 202 203 static inline void alchemy_uart_putchar(u32 uart_phys, u8 c) 204 { 205 void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys); 206 int timeout, i; 207 208 /* check LSR TX_EMPTY bit */ 209 timeout = 0xffffff; 210 do { 211 if (__raw_readl(base + 0x1c) & 0x20) 212 break; 213 /* slow down */ 214 for (i = 10000; i; i--) 215 asm volatile ("nop"); 216 } while (--timeout); 217 218 __raw_writel(c, base + 0x04); /* tx */ 219 wmb(); 220 } 221 222 /* return number of ethernet MACs on a given cputype */ 223 static inline int alchemy_get_macs(int type) 224 { 225 switch (type) { 226 case ALCHEMY_CPU_AU1000: 227 case ALCHEMY_CPU_AU1500: 228 case ALCHEMY_CPU_AU1550: 229 return 2; 230 case ALCHEMY_CPU_AU1100: 231 return 1; 232 } 233 return 0; 234 } 235 236 /* arch/mips/au1000/common/clocks.c */ 237 extern void set_au1x00_speed(unsigned int new_freq); 238 extern unsigned int get_au1x00_speed(void); 239 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); 240 extern unsigned long get_au1x00_uart_baud_base(void); 241 extern unsigned long au1xxx_calc_clock(void); 242 243 /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ 244 void alchemy_sleep_au1000(void); 245 void alchemy_sleep_au1550(void); 246 void au_sleep(void); 247 248 /* USB: drivers/usb/host/alchemy-common.c */ 249 enum alchemy_usb_block { 250 ALCHEMY_USB_OHCI0, 251 ALCHEMY_USB_UDC0, 252 ALCHEMY_USB_EHCI0, 253 ALCHEMY_USB_OTG0, 254 }; 255 int alchemy_usb_control(int block, int enable); 256 257 /* PCI controller platform data */ 258 struct alchemy_pci_platdata { 259 int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin); 260 int (*board_pci_idsel)(unsigned int devsel, int assert); 261 /* bits to set/clear in PCI_CONFIG register */ 262 unsigned long pci_cfg_set; 263 unsigned long pci_cfg_clr; 264 }; 265 266 /* SOC Interrupt numbers */ 267 268 #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) 269 #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) 270 #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) 271 #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) 272 #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST 273 274 enum soc_au1000_ints { 275 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, 276 AU1000_UART0_INT = AU1000_FIRST_INT, 277 AU1000_UART1_INT, 278 AU1000_UART2_INT, 279 AU1000_UART3_INT, 280 AU1000_SSI0_INT, 281 AU1000_SSI1_INT, 282 AU1000_DMA_INT_BASE, 283 284 AU1000_TOY_INT = AU1000_FIRST_INT + 14, 285 AU1000_TOY_MATCH0_INT, 286 AU1000_TOY_MATCH1_INT, 287 AU1000_TOY_MATCH2_INT, 288 AU1000_RTC_INT, 289 AU1000_RTC_MATCH0_INT, 290 AU1000_RTC_MATCH1_INT, 291 AU1000_RTC_MATCH2_INT, 292 AU1000_IRDA_TX_INT, 293 AU1000_IRDA_RX_INT, 294 AU1000_USB_DEV_REQ_INT, 295 AU1000_USB_DEV_SUS_INT, 296 AU1000_USB_HOST_INT, 297 AU1000_ACSYNC_INT, 298 AU1000_MAC0_DMA_INT, 299 AU1000_MAC1_DMA_INT, 300 AU1000_I2S_UO_INT, 301 AU1000_AC97C_INT, 302 AU1000_GPIO0_INT, 303 AU1000_GPIO1_INT, 304 AU1000_GPIO2_INT, 305 AU1000_GPIO3_INT, 306 AU1000_GPIO4_INT, 307 AU1000_GPIO5_INT, 308 AU1000_GPIO6_INT, 309 AU1000_GPIO7_INT, 310 AU1000_GPIO8_INT, 311 AU1000_GPIO9_INT, 312 AU1000_GPIO10_INT, 313 AU1000_GPIO11_INT, 314 AU1000_GPIO12_INT, 315 AU1000_GPIO13_INT, 316 AU1000_GPIO14_INT, 317 AU1000_GPIO15_INT, 318 AU1000_GPIO16_INT, 319 AU1000_GPIO17_INT, 320 AU1000_GPIO18_INT, 321 AU1000_GPIO19_INT, 322 AU1000_GPIO20_INT, 323 AU1000_GPIO21_INT, 324 AU1000_GPIO22_INT, 325 AU1000_GPIO23_INT, 326 AU1000_GPIO24_INT, 327 AU1000_GPIO25_INT, 328 AU1000_GPIO26_INT, 329 AU1000_GPIO27_INT, 330 AU1000_GPIO28_INT, 331 AU1000_GPIO29_INT, 332 AU1000_GPIO30_INT, 333 AU1000_GPIO31_INT, 334 }; 335 336 enum soc_au1100_ints { 337 AU1100_FIRST_INT = AU1000_INTC0_INT_BASE, 338 AU1100_UART0_INT = AU1100_FIRST_INT, 339 AU1100_UART1_INT, 340 AU1100_SD_INT, 341 AU1100_UART3_INT, 342 AU1100_SSI0_INT, 343 AU1100_SSI1_INT, 344 AU1100_DMA_INT_BASE, 345 346 AU1100_TOY_INT = AU1100_FIRST_INT + 14, 347 AU1100_TOY_MATCH0_INT, 348 AU1100_TOY_MATCH1_INT, 349 AU1100_TOY_MATCH2_INT, 350 AU1100_RTC_INT, 351 AU1100_RTC_MATCH0_INT, 352 AU1100_RTC_MATCH1_INT, 353 AU1100_RTC_MATCH2_INT, 354 AU1100_IRDA_TX_INT, 355 AU1100_IRDA_RX_INT, 356 AU1100_USB_DEV_REQ_INT, 357 AU1100_USB_DEV_SUS_INT, 358 AU1100_USB_HOST_INT, 359 AU1100_ACSYNC_INT, 360 AU1100_MAC0_DMA_INT, 361 AU1100_GPIO208_215_INT, 362 AU1100_LCD_INT, 363 AU1100_AC97C_INT, 364 AU1100_GPIO0_INT, 365 AU1100_GPIO1_INT, 366 AU1100_GPIO2_INT, 367 AU1100_GPIO3_INT, 368 AU1100_GPIO4_INT, 369 AU1100_GPIO5_INT, 370 AU1100_GPIO6_INT, 371 AU1100_GPIO7_INT, 372 AU1100_GPIO8_INT, 373 AU1100_GPIO9_INT, 374 AU1100_GPIO10_INT, 375 AU1100_GPIO11_INT, 376 AU1100_GPIO12_INT, 377 AU1100_GPIO13_INT, 378 AU1100_GPIO14_INT, 379 AU1100_GPIO15_INT, 380 AU1100_GPIO16_INT, 381 AU1100_GPIO17_INT, 382 AU1100_GPIO18_INT, 383 AU1100_GPIO19_INT, 384 AU1100_GPIO20_INT, 385 AU1100_GPIO21_INT, 386 AU1100_GPIO22_INT, 387 AU1100_GPIO23_INT, 388 AU1100_GPIO24_INT, 389 AU1100_GPIO25_INT, 390 AU1100_GPIO26_INT, 391 AU1100_GPIO27_INT, 392 AU1100_GPIO28_INT, 393 AU1100_GPIO29_INT, 394 AU1100_GPIO30_INT, 395 AU1100_GPIO31_INT, 396 }; 397 398 enum soc_au1500_ints { 399 AU1500_FIRST_INT = AU1000_INTC0_INT_BASE, 400 AU1500_UART0_INT = AU1500_FIRST_INT, 401 AU1500_PCI_INTA, 402 AU1500_PCI_INTB, 403 AU1500_UART3_INT, 404 AU1500_PCI_INTC, 405 AU1500_PCI_INTD, 406 AU1500_DMA_INT_BASE, 407 408 AU1500_TOY_INT = AU1500_FIRST_INT + 14, 409 AU1500_TOY_MATCH0_INT, 410 AU1500_TOY_MATCH1_INT, 411 AU1500_TOY_MATCH2_INT, 412 AU1500_RTC_INT, 413 AU1500_RTC_MATCH0_INT, 414 AU1500_RTC_MATCH1_INT, 415 AU1500_RTC_MATCH2_INT, 416 AU1500_PCI_ERR_INT, 417 AU1500_RESERVED_INT, 418 AU1500_USB_DEV_REQ_INT, 419 AU1500_USB_DEV_SUS_INT, 420 AU1500_USB_HOST_INT, 421 AU1500_ACSYNC_INT, 422 AU1500_MAC0_DMA_INT, 423 AU1500_MAC1_DMA_INT, 424 AU1500_AC97C_INT = AU1500_FIRST_INT + 31, 425 AU1500_GPIO0_INT, 426 AU1500_GPIO1_INT, 427 AU1500_GPIO2_INT, 428 AU1500_GPIO3_INT, 429 AU1500_GPIO4_INT, 430 AU1500_GPIO5_INT, 431 AU1500_GPIO6_INT, 432 AU1500_GPIO7_INT, 433 AU1500_GPIO8_INT, 434 AU1500_GPIO9_INT, 435 AU1500_GPIO10_INT, 436 AU1500_GPIO11_INT, 437 AU1500_GPIO12_INT, 438 AU1500_GPIO13_INT, 439 AU1500_GPIO14_INT, 440 AU1500_GPIO15_INT, 441 AU1500_GPIO200_INT, 442 AU1500_GPIO201_INT, 443 AU1500_GPIO202_INT, 444 AU1500_GPIO203_INT, 445 AU1500_GPIO20_INT, 446 AU1500_GPIO204_INT, 447 AU1500_GPIO205_INT, 448 AU1500_GPIO23_INT, 449 AU1500_GPIO24_INT, 450 AU1500_GPIO25_INT, 451 AU1500_GPIO26_INT, 452 AU1500_GPIO27_INT, 453 AU1500_GPIO28_INT, 454 AU1500_GPIO206_INT, 455 AU1500_GPIO207_INT, 456 AU1500_GPIO208_215_INT, 457 }; 458 459 enum soc_au1550_ints { 460 AU1550_FIRST_INT = AU1000_INTC0_INT_BASE, 461 AU1550_UART0_INT = AU1550_FIRST_INT, 462 AU1550_PCI_INTA, 463 AU1550_PCI_INTB, 464 AU1550_DDMA_INT, 465 AU1550_CRYPTO_INT, 466 AU1550_PCI_INTC, 467 AU1550_PCI_INTD, 468 AU1550_PCI_RST_INT, 469 AU1550_UART1_INT, 470 AU1550_UART3_INT, 471 AU1550_PSC0_INT, 472 AU1550_PSC1_INT, 473 AU1550_PSC2_INT, 474 AU1550_PSC3_INT, 475 AU1550_TOY_INT, 476 AU1550_TOY_MATCH0_INT, 477 AU1550_TOY_MATCH1_INT, 478 AU1550_TOY_MATCH2_INT, 479 AU1550_RTC_INT, 480 AU1550_RTC_MATCH0_INT, 481 AU1550_RTC_MATCH1_INT, 482 AU1550_RTC_MATCH2_INT, 483 484 AU1550_NAND_INT = AU1550_FIRST_INT + 23, 485 AU1550_USB_DEV_REQ_INT, 486 AU1550_USB_DEV_SUS_INT, 487 AU1550_USB_HOST_INT, 488 AU1550_MAC0_DMA_INT, 489 AU1550_MAC1_DMA_INT, 490 AU1550_GPIO0_INT = AU1550_FIRST_INT + 32, 491 AU1550_GPIO1_INT, 492 AU1550_GPIO2_INT, 493 AU1550_GPIO3_INT, 494 AU1550_GPIO4_INT, 495 AU1550_GPIO5_INT, 496 AU1550_GPIO6_INT, 497 AU1550_GPIO7_INT, 498 AU1550_GPIO8_INT, 499 AU1550_GPIO9_INT, 500 AU1550_GPIO10_INT, 501 AU1550_GPIO11_INT, 502 AU1550_GPIO12_INT, 503 AU1550_GPIO13_INT, 504 AU1550_GPIO14_INT, 505 AU1550_GPIO15_INT, 506 AU1550_GPIO200_INT, 507 AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */ 508 AU1550_GPIO16_INT, 509 AU1550_GPIO17_INT, 510 AU1550_GPIO20_INT, 511 AU1550_GPIO21_INT, 512 AU1550_GPIO22_INT, 513 AU1550_GPIO23_INT, 514 AU1550_GPIO24_INT, 515 AU1550_GPIO25_INT, 516 AU1550_GPIO26_INT, 517 AU1550_GPIO27_INT, 518 AU1550_GPIO28_INT, 519 AU1550_GPIO206_INT, 520 AU1550_GPIO207_INT, 521 AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */ 522 }; 523 524 enum soc_au1200_ints { 525 AU1200_FIRST_INT = AU1000_INTC0_INT_BASE, 526 AU1200_UART0_INT = AU1200_FIRST_INT, 527 AU1200_SWT_INT, 528 AU1200_SD_INT, 529 AU1200_DDMA_INT, 530 AU1200_MAE_BE_INT, 531 AU1200_GPIO200_INT, 532 AU1200_GPIO201_INT, 533 AU1200_GPIO202_INT, 534 AU1200_UART1_INT, 535 AU1200_MAE_FE_INT, 536 AU1200_PSC0_INT, 537 AU1200_PSC1_INT, 538 AU1200_AES_INT, 539 AU1200_CAMERA_INT, 540 AU1200_TOY_INT, 541 AU1200_TOY_MATCH0_INT, 542 AU1200_TOY_MATCH1_INT, 543 AU1200_TOY_MATCH2_INT, 544 AU1200_RTC_INT, 545 AU1200_RTC_MATCH0_INT, 546 AU1200_RTC_MATCH1_INT, 547 AU1200_RTC_MATCH2_INT, 548 AU1200_GPIO203_INT, 549 AU1200_NAND_INT, 550 AU1200_GPIO204_INT, 551 AU1200_GPIO205_INT, 552 AU1200_GPIO206_INT, 553 AU1200_GPIO207_INT, 554 AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */ 555 AU1200_USB_INT, 556 AU1200_LCD_INT, 557 AU1200_MAE_BOTH_INT, 558 AU1200_GPIO0_INT, 559 AU1200_GPIO1_INT, 560 AU1200_GPIO2_INT, 561 AU1200_GPIO3_INT, 562 AU1200_GPIO4_INT, 563 AU1200_GPIO5_INT, 564 AU1200_GPIO6_INT, 565 AU1200_GPIO7_INT, 566 AU1200_GPIO8_INT, 567 AU1200_GPIO9_INT, 568 AU1200_GPIO10_INT, 569 AU1200_GPIO11_INT, 570 AU1200_GPIO12_INT, 571 AU1200_GPIO13_INT, 572 AU1200_GPIO14_INT, 573 AU1200_GPIO15_INT, 574 AU1200_GPIO16_INT, 575 AU1200_GPIO17_INT, 576 AU1200_GPIO18_INT, 577 AU1200_GPIO19_INT, 578 AU1200_GPIO20_INT, 579 AU1200_GPIO21_INT, 580 AU1200_GPIO22_INT, 581 AU1200_GPIO23_INT, 582 AU1200_GPIO24_INT, 583 AU1200_GPIO25_INT, 584 AU1200_GPIO26_INT, 585 AU1200_GPIO27_INT, 586 AU1200_GPIO28_INT, 587 AU1200_GPIO29_INT, 588 AU1200_GPIO30_INT, 589 AU1200_GPIO31_INT, 590 }; 591 592 #endif /* !defined (_LANGUAGE_ASSEMBLY) */ 593 594 /* 595 * Physical base addresses for integrated peripherals 596 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 597 */ 598 599 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ 600 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ 601 #define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ 602 #define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */ 603 #define AU1200_AES_PHYS_ADDR 0x10300000 /* 4 */ 604 #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ 605 #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ 606 #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ 607 #define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ 608 #define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */ 609 #define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ 610 #define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */ 611 #define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */ 612 #define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ 613 #define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ 614 #define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ 615 #define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */ 616 #define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */ 617 #define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */ 618 #define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */ 619 #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ 620 #define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */ 621 #define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */ 622 #define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */ 623 #define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ 624 #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ 625 #define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */ 626 #define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */ 627 #define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */ 628 #define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */ 629 #define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */ 630 #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ 631 #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ 632 #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ 633 #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ 634 #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ 635 #define AU1200_CIM_PHYS_ADDR 0x14004000 /* 4 */ 636 #define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */ 637 #define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */ 638 #define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */ 639 #define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */ 640 #define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ 641 #define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ 642 #define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ 643 #define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ 644 #define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ 645 #define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ 646 #define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */ 647 #define AU1200_LCD_PHYS_ADDR 0x15000000 /* 4 */ 648 #define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */ 649 #define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */ 650 #define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */ 651 #define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */ 652 #define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 01234 */ 653 #define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 01234 */ 654 #define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */ 655 656 657 /* Au1000 SDRAM memory controller register offsets */ 658 #define AU1000_MEM_SDMODE0 0x0000 659 #define AU1000_MEM_SDMODE1 0x0004 660 #define AU1000_MEM_SDMODE2 0x0008 661 #define AU1000_MEM_SDADDR0 0x000C 662 #define AU1000_MEM_SDADDR1 0x0010 663 #define AU1000_MEM_SDADDR2 0x0014 664 #define AU1000_MEM_SDREFCFG 0x0018 665 #define AU1000_MEM_SDPRECMD 0x001C 666 #define AU1000_MEM_SDAUTOREF 0x0020 667 #define AU1000_MEM_SDWRMD0 0x0024 668 #define AU1000_MEM_SDWRMD1 0x0028 669 #define AU1000_MEM_SDWRMD2 0x002C 670 #define AU1000_MEM_SDSLEEP 0x0030 671 #define AU1000_MEM_SDSMCKE 0x0034 672 673 /* MEM_SDMODE register content definitions */ 674 #define MEM_SDMODE_F (1 << 22) 675 #define MEM_SDMODE_SR (1 << 21) 676 #define MEM_SDMODE_BS (1 << 20) 677 #define MEM_SDMODE_RS (3 << 18) 678 #define MEM_SDMODE_CS (7 << 15) 679 #define MEM_SDMODE_TRAS (15 << 11) 680 #define MEM_SDMODE_TMRD (3 << 9) 681 #define MEM_SDMODE_TWR (3 << 7) 682 #define MEM_SDMODE_TRP (3 << 5) 683 #define MEM_SDMODE_TRCD (3 << 3) 684 #define MEM_SDMODE_TCL (7 << 0) 685 686 #define MEM_SDMODE_BS_2Bank (0 << 20) 687 #define MEM_SDMODE_BS_4Bank (1 << 20) 688 #define MEM_SDMODE_RS_11Row (0 << 18) 689 #define MEM_SDMODE_RS_12Row (1 << 18) 690 #define MEM_SDMODE_RS_13Row (2 << 18) 691 #define MEM_SDMODE_RS_N(N) ((N) << 18) 692 #define MEM_SDMODE_CS_7Col (0 << 15) 693 #define MEM_SDMODE_CS_8Col (1 << 15) 694 #define MEM_SDMODE_CS_9Col (2 << 15) 695 #define MEM_SDMODE_CS_10Col (3 << 15) 696 #define MEM_SDMODE_CS_11Col (4 << 15) 697 #define MEM_SDMODE_CS_N(N) ((N) << 15) 698 #define MEM_SDMODE_TRAS_N(N) ((N) << 11) 699 #define MEM_SDMODE_TMRD_N(N) ((N) << 9) 700 #define MEM_SDMODE_TWR_N(N) ((N) << 7) 701 #define MEM_SDMODE_TRP_N(N) ((N) << 5) 702 #define MEM_SDMODE_TRCD_N(N) ((N) << 3) 703 #define MEM_SDMODE_TCL_N(N) ((N) << 0) 704 705 /* MEM_SDADDR register contents definitions */ 706 #define MEM_SDADDR_E (1 << 20) 707 #define MEM_SDADDR_CSBA (0x03FF << 10) 708 #define MEM_SDADDR_CSMASK (0x03FF << 0) 709 #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) 710 #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) 711 712 /* MEM_SDREFCFG register content definitions */ 713 #define MEM_SDREFCFG_TRC (15 << 28) 714 #define MEM_SDREFCFG_TRPM (3 << 26) 715 #define MEM_SDREFCFG_E (1 << 25) 716 #define MEM_SDREFCFG_RE (0x1ffffff << 0) 717 #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) 718 #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) 719 #define MEM_SDREFCFG_REF_N(N) (N) 720 721 /* Au1550 SDRAM Register Offsets */ 722 #define AU1550_MEM_SDMODE0 0x0800 723 #define AU1550_MEM_SDMODE1 0x0808 724 #define AU1550_MEM_SDMODE2 0x0810 725 #define AU1550_MEM_SDADDR0 0x0820 726 #define AU1550_MEM_SDADDR1 0x0828 727 #define AU1550_MEM_SDADDR2 0x0830 728 #define AU1550_MEM_SDCONFIGA 0x0840 729 #define AU1550_MEM_SDCONFIGB 0x0848 730 #define AU1550_MEM_SDSTAT 0x0850 731 #define AU1550_MEM_SDERRADDR 0x0858 732 #define AU1550_MEM_SDSTRIDE0 0x0860 733 #define AU1550_MEM_SDSTRIDE1 0x0868 734 #define AU1550_MEM_SDSTRIDE2 0x0870 735 #define AU1550_MEM_SDWRMD0 0x0880 736 #define AU1550_MEM_SDWRMD1 0x0888 737 #define AU1550_MEM_SDWRMD2 0x0890 738 #define AU1550_MEM_SDPRECMD 0x08C0 739 #define AU1550_MEM_SDAUTOREF 0x08C8 740 #define AU1550_MEM_SDSREF 0x08D0 741 #define AU1550_MEM_SDSLEEP MEM_SDSREF 742 743 /* Static Bus Controller */ 744 #define MEM_STCFG0 0xB4001000 745 #define MEM_STTIME0 0xB4001004 746 #define MEM_STADDR0 0xB4001008 747 748 #define MEM_STCFG1 0xB4001010 749 #define MEM_STTIME1 0xB4001014 750 #define MEM_STADDR1 0xB4001018 751 752 #define MEM_STCFG2 0xB4001020 753 #define MEM_STTIME2 0xB4001024 754 #define MEM_STADDR2 0xB4001028 755 756 #define MEM_STCFG3 0xB4001030 757 #define MEM_STTIME3 0xB4001034 758 #define MEM_STADDR3 0xB4001038 759 760 #define MEM_STNDCTL 0xB4001100 761 #define MEM_STSTAT 0xB4001104 762 763 #define MEM_STNAND_CMD 0x0 764 #define MEM_STNAND_ADDR 0x4 765 #define MEM_STNAND_DATA 0x20 766 767 768 /* Programmable Counters 0 and 1 */ 769 #define SYS_BASE 0xB1900000 770 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) 771 # define SYS_CNTRL_E1S (1 << 23) 772 # define SYS_CNTRL_T1S (1 << 20) 773 # define SYS_CNTRL_M21 (1 << 19) 774 # define SYS_CNTRL_M11 (1 << 18) 775 # define SYS_CNTRL_M01 (1 << 17) 776 # define SYS_CNTRL_C1S (1 << 16) 777 # define SYS_CNTRL_BP (1 << 14) 778 # define SYS_CNTRL_EN1 (1 << 13) 779 # define SYS_CNTRL_BT1 (1 << 12) 780 # define SYS_CNTRL_EN0 (1 << 11) 781 # define SYS_CNTRL_BT0 (1 << 10) 782 # define SYS_CNTRL_E0 (1 << 8) 783 # define SYS_CNTRL_E0S (1 << 7) 784 # define SYS_CNTRL_32S (1 << 5) 785 # define SYS_CNTRL_T0S (1 << 4) 786 # define SYS_CNTRL_M20 (1 << 3) 787 # define SYS_CNTRL_M10 (1 << 2) 788 # define SYS_CNTRL_M00 (1 << 1) 789 # define SYS_CNTRL_C0S (1 << 0) 790 791 /* Programmable Counter 0 Registers */ 792 #define SYS_TOYTRIM (SYS_BASE + 0) 793 #define SYS_TOYWRITE (SYS_BASE + 4) 794 #define SYS_TOYMATCH0 (SYS_BASE + 8) 795 #define SYS_TOYMATCH1 (SYS_BASE + 0xC) 796 #define SYS_TOYMATCH2 (SYS_BASE + 0x10) 797 #define SYS_TOYREAD (SYS_BASE + 0x40) 798 799 /* Programmable Counter 1 Registers */ 800 #define SYS_RTCTRIM (SYS_BASE + 0x44) 801 #define SYS_RTCWRITE (SYS_BASE + 0x48) 802 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C) 803 #define SYS_RTCMATCH1 (SYS_BASE + 0x50) 804 #define SYS_RTCMATCH2 (SYS_BASE + 0x54) 805 #define SYS_RTCREAD (SYS_BASE + 0x58) 806 807 /* I2S Controller */ 808 #define I2S_DATA 0xB1000000 809 # define I2S_DATA_MASK 0xffffff 810 #define I2S_CONFIG 0xB1000004 811 # define I2S_CONFIG_XU (1 << 25) 812 # define I2S_CONFIG_XO (1 << 24) 813 # define I2S_CONFIG_RU (1 << 23) 814 # define I2S_CONFIG_RO (1 << 22) 815 # define I2S_CONFIG_TR (1 << 21) 816 # define I2S_CONFIG_TE (1 << 20) 817 # define I2S_CONFIG_TF (1 << 19) 818 # define I2S_CONFIG_RR (1 << 18) 819 # define I2S_CONFIG_RE (1 << 17) 820 # define I2S_CONFIG_RF (1 << 16) 821 # define I2S_CONFIG_PD (1 << 11) 822 # define I2S_CONFIG_LB (1 << 10) 823 # define I2S_CONFIG_IC (1 << 9) 824 # define I2S_CONFIG_FM_BIT 7 825 # define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) 826 # define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) 827 # define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) 828 # define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) 829 # define I2S_CONFIG_TN (1 << 6) 830 # define I2S_CONFIG_RN (1 << 5) 831 # define I2S_CONFIG_SZ_BIT 0 832 # define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) 833 834 #define I2S_CONTROL 0xB1000008 835 # define I2S_CONTROL_D (1 << 1) 836 # define I2S_CONTROL_CE (1 << 0) 837 838 839 /* Ethernet Controllers */ 840 841 /* 4 byte offsets from AU1000_ETH_BASE */ 842 #define MAC_CONTROL 0x0 843 # define MAC_RX_ENABLE (1 << 2) 844 # define MAC_TX_ENABLE (1 << 3) 845 # define MAC_DEF_CHECK (1 << 5) 846 # define MAC_SET_BL(X) (((X) & 0x3) << 6) 847 # define MAC_AUTO_PAD (1 << 8) 848 # define MAC_DISABLE_RETRY (1 << 10) 849 # define MAC_DISABLE_BCAST (1 << 11) 850 # define MAC_LATE_COL (1 << 12) 851 # define MAC_HASH_MODE (1 << 13) 852 # define MAC_HASH_ONLY (1 << 15) 853 # define MAC_PASS_ALL (1 << 16) 854 # define MAC_INVERSE_FILTER (1 << 17) 855 # define MAC_PROMISCUOUS (1 << 18) 856 # define MAC_PASS_ALL_MULTI (1 << 19) 857 # define MAC_FULL_DUPLEX (1 << 20) 858 # define MAC_NORMAL_MODE 0 859 # define MAC_INT_LOOPBACK (1 << 21) 860 # define MAC_EXT_LOOPBACK (1 << 22) 861 # define MAC_DISABLE_RX_OWN (1 << 23) 862 # define MAC_BIG_ENDIAN (1 << 30) 863 # define MAC_RX_ALL (1 << 31) 864 #define MAC_ADDRESS_HIGH 0x4 865 #define MAC_ADDRESS_LOW 0x8 866 #define MAC_MCAST_HIGH 0xC 867 #define MAC_MCAST_LOW 0x10 868 #define MAC_MII_CNTRL 0x14 869 # define MAC_MII_BUSY (1 << 0) 870 # define MAC_MII_READ 0 871 # define MAC_MII_WRITE (1 << 1) 872 # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6) 873 # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11) 874 #define MAC_MII_DATA 0x18 875 #define MAC_FLOW_CNTRL 0x1C 876 # define MAC_FLOW_CNTRL_BUSY (1 << 0) 877 # define MAC_FLOW_CNTRL_ENABLE (1 << 1) 878 # define MAC_PASS_CONTROL (1 << 2) 879 # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16) 880 #define MAC_VLAN1_TAG 0x20 881 #define MAC_VLAN2_TAG 0x24 882 883 /* Ethernet Controller Enable */ 884 885 # define MAC_EN_CLOCK_ENABLE (1 << 0) 886 # define MAC_EN_RESET0 (1 << 1) 887 # define MAC_EN_TOSS (0 << 2) 888 # define MAC_EN_CACHEABLE (1 << 3) 889 # define MAC_EN_RESET1 (1 << 4) 890 # define MAC_EN_RESET2 (1 << 5) 891 # define MAC_DMA_RESET (1 << 6) 892 893 /* Ethernet Controller DMA Channels */ 894 895 #define MAC0_TX_DMA_ADDR 0xB4004000 896 #define MAC1_TX_DMA_ADDR 0xB4004200 897 /* offsets from MAC_TX_RING_ADDR address */ 898 #define MAC_TX_BUFF0_STATUS 0x0 899 # define TX_FRAME_ABORTED (1 << 0) 900 # define TX_JAB_TIMEOUT (1 << 1) 901 # define TX_NO_CARRIER (1 << 2) 902 # define TX_LOSS_CARRIER (1 << 3) 903 # define TX_EXC_DEF (1 << 4) 904 # define TX_LATE_COLL_ABORT (1 << 5) 905 # define TX_EXC_COLL (1 << 6) 906 # define TX_UNDERRUN (1 << 7) 907 # define TX_DEFERRED (1 << 8) 908 # define TX_LATE_COLL (1 << 9) 909 # define TX_COLL_CNT_MASK (0xF << 10) 910 # define TX_PKT_RETRY (1 << 31) 911 #define MAC_TX_BUFF0_ADDR 0x4 912 # define TX_DMA_ENABLE (1 << 0) 913 # define TX_T_DONE (1 << 1) 914 # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) 915 #define MAC_TX_BUFF0_LEN 0x8 916 #define MAC_TX_BUFF1_STATUS 0x10 917 #define MAC_TX_BUFF1_ADDR 0x14 918 #define MAC_TX_BUFF1_LEN 0x18 919 #define MAC_TX_BUFF2_STATUS 0x20 920 #define MAC_TX_BUFF2_ADDR 0x24 921 #define MAC_TX_BUFF2_LEN 0x28 922 #define MAC_TX_BUFF3_STATUS 0x30 923 #define MAC_TX_BUFF3_ADDR 0x34 924 #define MAC_TX_BUFF3_LEN 0x38 925 926 #define MAC0_RX_DMA_ADDR 0xB4004100 927 #define MAC1_RX_DMA_ADDR 0xB4004300 928 /* offsets from MAC_RX_RING_ADDR */ 929 #define MAC_RX_BUFF0_STATUS 0x0 930 # define RX_FRAME_LEN_MASK 0x3fff 931 # define RX_WDOG_TIMER (1 << 14) 932 # define RX_RUNT (1 << 15) 933 # define RX_OVERLEN (1 << 16) 934 # define RX_COLL (1 << 17) 935 # define RX_ETHER (1 << 18) 936 # define RX_MII_ERROR (1 << 19) 937 # define RX_DRIBBLING (1 << 20) 938 # define RX_CRC_ERROR (1 << 21) 939 # define RX_VLAN1 (1 << 22) 940 # define RX_VLAN2 (1 << 23) 941 # define RX_LEN_ERROR (1 << 24) 942 # define RX_CNTRL_FRAME (1 << 25) 943 # define RX_U_CNTRL_FRAME (1 << 26) 944 # define RX_MCAST_FRAME (1 << 27) 945 # define RX_BCAST_FRAME (1 << 28) 946 # define RX_FILTER_FAIL (1 << 29) 947 # define RX_PACKET_FILTER (1 << 30) 948 # define RX_MISSED_FRAME (1 << 31) 949 950 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ 951 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ 952 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) 953 #define MAC_RX_BUFF0_ADDR 0x4 954 # define RX_DMA_ENABLE (1 << 0) 955 # define RX_T_DONE (1 << 1) 956 # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) 957 # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0) 958 #define MAC_RX_BUFF1_STATUS 0x10 959 #define MAC_RX_BUFF1_ADDR 0x14 960 #define MAC_RX_BUFF2_STATUS 0x20 961 #define MAC_RX_BUFF2_ADDR 0x24 962 #define MAC_RX_BUFF3_STATUS 0x30 963 #define MAC_RX_BUFF3_ADDR 0x34 964 965 #define UART_RX 0 /* Receive buffer */ 966 #define UART_TX 4 /* Transmit buffer */ 967 #define UART_IER 8 /* Interrupt Enable Register */ 968 #define UART_IIR 0xC /* Interrupt ID Register */ 969 #define UART_FCR 0x10 /* FIFO Control Register */ 970 #define UART_LCR 0x14 /* Line Control Register */ 971 #define UART_MCR 0x18 /* Modem Control Register */ 972 #define UART_LSR 0x1C /* Line Status Register */ 973 #define UART_MSR 0x20 /* Modem Status Register */ 974 #define UART_CLK 0x28 /* Baud Rate Clock Divider */ 975 #define UART_MOD_CNTRL 0x100 /* Module Control */ 976 977 /* SSIO */ 978 #define SSI0_STATUS 0xB1600000 979 # define SSI_STATUS_BF (1 << 4) 980 # define SSI_STATUS_OF (1 << 3) 981 # define SSI_STATUS_UF (1 << 2) 982 # define SSI_STATUS_D (1 << 1) 983 # define SSI_STATUS_B (1 << 0) 984 #define SSI0_INT 0xB1600004 985 # define SSI_INT_OI (1 << 3) 986 # define SSI_INT_UI (1 << 2) 987 # define SSI_INT_DI (1 << 1) 988 #define SSI0_INT_ENABLE 0xB1600008 989 # define SSI_INTE_OIE (1 << 3) 990 # define SSI_INTE_UIE (1 << 2) 991 # define SSI_INTE_DIE (1 << 1) 992 #define SSI0_CONFIG 0xB1600020 993 # define SSI_CONFIG_AO (1 << 24) 994 # define SSI_CONFIG_DO (1 << 23) 995 # define SSI_CONFIG_ALEN_BIT 20 996 # define SSI_CONFIG_ALEN_MASK (0x7 << 20) 997 # define SSI_CONFIG_DLEN_BIT 16 998 # define SSI_CONFIG_DLEN_MASK (0x7 << 16) 999 # define SSI_CONFIG_DD (1 << 11) 1000 # define SSI_CONFIG_AD (1 << 10) 1001 # define SSI_CONFIG_BM_BIT 8 1002 # define SSI_CONFIG_BM_MASK (0x3 << 8) 1003 # define SSI_CONFIG_CE (1 << 7) 1004 # define SSI_CONFIG_DP (1 << 6) 1005 # define SSI_CONFIG_DL (1 << 5) 1006 # define SSI_CONFIG_EP (1 << 4) 1007 #define SSI0_ADATA 0xB1600024 1008 # define SSI_AD_D (1 << 24) 1009 # define SSI_AD_ADDR_BIT 16 1010 # define SSI_AD_ADDR_MASK (0xff << 16) 1011 # define SSI_AD_DATA_BIT 0 1012 # define SSI_AD_DATA_MASK (0xfff << 0) 1013 #define SSI0_CLKDIV 0xB1600028 1014 #define SSI0_CONTROL 0xB1600100 1015 # define SSI_CONTROL_CD (1 << 1) 1016 # define SSI_CONTROL_E (1 << 0) 1017 1018 /* SSI1 */ 1019 #define SSI1_STATUS 0xB1680000 1020 #define SSI1_INT 0xB1680004 1021 #define SSI1_INT_ENABLE 0xB1680008 1022 #define SSI1_CONFIG 0xB1680020 1023 #define SSI1_ADATA 0xB1680024 1024 #define SSI1_CLKDIV 0xB1680028 1025 #define SSI1_ENABLE 0xB1680100 1026 1027 /* 1028 * Register content definitions 1029 */ 1030 #define SSI_STATUS_BF (1 << 4) 1031 #define SSI_STATUS_OF (1 << 3) 1032 #define SSI_STATUS_UF (1 << 2) 1033 #define SSI_STATUS_D (1 << 1) 1034 #define SSI_STATUS_B (1 << 0) 1035 1036 /* SSI_INT */ 1037 #define SSI_INT_OI (1 << 3) 1038 #define SSI_INT_UI (1 << 2) 1039 #define SSI_INT_DI (1 << 1) 1040 1041 /* SSI_INTEN */ 1042 #define SSI_INTEN_OIE (1 << 3) 1043 #define SSI_INTEN_UIE (1 << 2) 1044 #define SSI_INTEN_DIE (1 << 1) 1045 1046 #define SSI_CONFIG_AO (1 << 24) 1047 #define SSI_CONFIG_DO (1 << 23) 1048 #define SSI_CONFIG_ALEN (7 << 20) 1049 #define SSI_CONFIG_DLEN (15 << 16) 1050 #define SSI_CONFIG_DD (1 << 11) 1051 #define SSI_CONFIG_AD (1 << 10) 1052 #define SSI_CONFIG_BM (3 << 8) 1053 #define SSI_CONFIG_CE (1 << 7) 1054 #define SSI_CONFIG_DP (1 << 6) 1055 #define SSI_CONFIG_DL (1 << 5) 1056 #define SSI_CONFIG_EP (1 << 4) 1057 #define SSI_CONFIG_ALEN_N(N) ((N-1) << 20) 1058 #define SSI_CONFIG_DLEN_N(N) ((N-1) << 16) 1059 #define SSI_CONFIG_BM_HI (0 << 8) 1060 #define SSI_CONFIG_BM_LO (1 << 8) 1061 #define SSI_CONFIG_BM_CY (2 << 8) 1062 1063 #define SSI_ADATA_D (1 << 24) 1064 #define SSI_ADATA_ADDR (0xFF << 16) 1065 #define SSI_ADATA_DATA 0x0FFF 1066 #define SSI_ADATA_ADDR_N(N) (N << 16) 1067 1068 #define SSI_ENABLE_CD (1 << 1) 1069 #define SSI_ENABLE_E (1 << 0) 1070 1071 /* IrDA Controller */ 1072 #define IRDA_BASE 0xB0300000 1073 #define IR_RING_PTR_STATUS (IRDA_BASE + 0x00) 1074 #define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04) 1075 #define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08) 1076 #define IR_RING_SIZE (IRDA_BASE + 0x0C) 1077 #define IR_RING_PROMPT (IRDA_BASE + 0x10) 1078 #define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14) 1079 #define IR_INT_CLEAR (IRDA_BASE + 0x18) 1080 #define IR_CONFIG_1 (IRDA_BASE + 0x20) 1081 # define IR_RX_INVERT_LED (1 << 0) 1082 # define IR_TX_INVERT_LED (1 << 1) 1083 # define IR_ST (1 << 2) 1084 # define IR_SF (1 << 3) 1085 # define IR_SIR (1 << 4) 1086 # define IR_MIR (1 << 5) 1087 # define IR_FIR (1 << 6) 1088 # define IR_16CRC (1 << 7) 1089 # define IR_TD (1 << 8) 1090 # define IR_RX_ALL (1 << 9) 1091 # define IR_DMA_ENABLE (1 << 10) 1092 # define IR_RX_ENABLE (1 << 11) 1093 # define IR_TX_ENABLE (1 << 12) 1094 # define IR_LOOPBACK (1 << 14) 1095 # define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ 1096 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) 1097 #define IR_SIR_FLAGS (IRDA_BASE + 0x24) 1098 #define IR_ENABLE (IRDA_BASE + 0x28) 1099 # define IR_RX_STATUS (1 << 9) 1100 # define IR_TX_STATUS (1 << 10) 1101 #define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C) 1102 #define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30) 1103 #define IR_MAX_PKT_LEN (IRDA_BASE + 0x34) 1104 #define IR_RX_BYTE_CNT (IRDA_BASE + 0x38) 1105 #define IR_CONFIG_2 (IRDA_BASE + 0x3C) 1106 # define IR_MODE_INV (1 << 0) 1107 # define IR_ONE_PIN (1 << 1) 1108 #define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40) 1109 1110 /* GPIO */ 1111 #define SYS_PINFUNC 0xB190002C 1112 # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */ 1113 # define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */ 1114 # define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */ 1115 # define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */ 1116 # define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */ 1117 # define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */ 1118 # define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */ 1119 # define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */ 1120 # define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */ 1121 # define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */ 1122 # define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */ 1123 # define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */ 1124 # define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */ 1125 # define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */ 1126 # define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */ 1127 # define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */ 1128 1129 /* Au1100 only */ 1130 # define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */ 1131 # define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */ 1132 # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */ 1133 # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */ 1134 1135 /* Au1550 only. Redefines lots of pins */ 1136 # define SYS_PF_PSC2_MASK (7 << 17) 1137 # define SYS_PF_PSC2_AC97 0 1138 # define SYS_PF_PSC2_SPI 0 1139 # define SYS_PF_PSC2_I2S (1 << 17) 1140 # define SYS_PF_PSC2_SMBUS (3 << 17) 1141 # define SYS_PF_PSC2_GPIO (7 << 17) 1142 # define SYS_PF_PSC3_MASK (7 << 20) 1143 # define SYS_PF_PSC3_AC97 0 1144 # define SYS_PF_PSC3_SPI 0 1145 # define SYS_PF_PSC3_I2S (1 << 20) 1146 # define SYS_PF_PSC3_SMBUS (3 << 20) 1147 # define SYS_PF_PSC3_GPIO (7 << 20) 1148 # define SYS_PF_PSC1_S1 (1 << 1) 1149 # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) 1150 1151 /* Au1200 only */ 1152 #define SYS_PINFUNC_DMA (1 << 31) 1153 #define SYS_PINFUNC_S0A (1 << 30) 1154 #define SYS_PINFUNC_S1A (1 << 29) 1155 #define SYS_PINFUNC_LP0 (1 << 28) 1156 #define SYS_PINFUNC_LP1 (1 << 27) 1157 #define SYS_PINFUNC_LD16 (1 << 26) 1158 #define SYS_PINFUNC_LD8 (1 << 25) 1159 #define SYS_PINFUNC_LD1 (1 << 24) 1160 #define SYS_PINFUNC_LD0 (1 << 23) 1161 #define SYS_PINFUNC_P1A (3 << 21) 1162 #define SYS_PINFUNC_P1B (1 << 20) 1163 #define SYS_PINFUNC_FS3 (1 << 19) 1164 #define SYS_PINFUNC_P0A (3 << 17) 1165 #define SYS_PINFUNC_CS (1 << 16) 1166 #define SYS_PINFUNC_CIM (1 << 15) 1167 #define SYS_PINFUNC_P1C (1 << 14) 1168 #define SYS_PINFUNC_U1T (1 << 12) 1169 #define SYS_PINFUNC_U1R (1 << 11) 1170 #define SYS_PINFUNC_EX1 (1 << 10) 1171 #define SYS_PINFUNC_EX0 (1 << 9) 1172 #define SYS_PINFUNC_U0R (1 << 8) 1173 #define SYS_PINFUNC_MC (1 << 7) 1174 #define SYS_PINFUNC_S0B (1 << 6) 1175 #define SYS_PINFUNC_S0C (1 << 5) 1176 #define SYS_PINFUNC_P0B (1 << 4) 1177 #define SYS_PINFUNC_U0T (1 << 3) 1178 #define SYS_PINFUNC_S1B (1 << 2) 1179 1180 /* Power Management */ 1181 #define SYS_SCRATCH0 0xB1900018 1182 #define SYS_SCRATCH1 0xB190001C 1183 #define SYS_WAKEMSK 0xB1900034 1184 #define SYS_ENDIAN 0xB1900038 1185 #define SYS_POWERCTRL 0xB190003C 1186 #define SYS_WAKESRC 0xB190005C 1187 #define SYS_SLPPWR 0xB1900078 1188 #define SYS_SLEEP 0xB190007C 1189 1190 #define SYS_WAKEMSK_D2 (1 << 9) 1191 #define SYS_WAKEMSK_M2 (1 << 8) 1192 #define SYS_WAKEMSK_GPIO(x) (1 << (x)) 1193 1194 /* Clock Controller */ 1195 #define SYS_FREQCTRL0 0xB1900020 1196 # define SYS_FC_FRDIV2_BIT 22 1197 # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) 1198 # define SYS_FC_FE2 (1 << 21) 1199 # define SYS_FC_FS2 (1 << 20) 1200 # define SYS_FC_FRDIV1_BIT 12 1201 # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) 1202 # define SYS_FC_FE1 (1 << 11) 1203 # define SYS_FC_FS1 (1 << 10) 1204 # define SYS_FC_FRDIV0_BIT 2 1205 # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) 1206 # define SYS_FC_FE0 (1 << 1) 1207 # define SYS_FC_FS0 (1 << 0) 1208 #define SYS_FREQCTRL1 0xB1900024 1209 # define SYS_FC_FRDIV5_BIT 22 1210 # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) 1211 # define SYS_FC_FE5 (1 << 21) 1212 # define SYS_FC_FS5 (1 << 20) 1213 # define SYS_FC_FRDIV4_BIT 12 1214 # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) 1215 # define SYS_FC_FE4 (1 << 11) 1216 # define SYS_FC_FS4 (1 << 10) 1217 # define SYS_FC_FRDIV3_BIT 2 1218 # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) 1219 # define SYS_FC_FE3 (1 << 1) 1220 # define SYS_FC_FS3 (1 << 0) 1221 #define SYS_CLKSRC 0xB1900028 1222 # define SYS_CS_ME1_BIT 27 1223 # define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT) 1224 # define SYS_CS_DE1 (1 << 26) 1225 # define SYS_CS_CE1 (1 << 25) 1226 # define SYS_CS_ME0_BIT 22 1227 # define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT) 1228 # define SYS_CS_DE0 (1 << 21) 1229 # define SYS_CS_CE0 (1 << 20) 1230 # define SYS_CS_MI2_BIT 17 1231 # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT) 1232 # define SYS_CS_DI2 (1 << 16) 1233 # define SYS_CS_CI2 (1 << 15) 1234 1235 # define SYS_CS_ML_BIT 7 1236 # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT) 1237 # define SYS_CS_DL (1 << 6) 1238 # define SYS_CS_CL (1 << 5) 1239 1240 # define SYS_CS_MUH_BIT 12 1241 # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT) 1242 # define SYS_CS_DUH (1 << 11) 1243 # define SYS_CS_CUH (1 << 10) 1244 # define SYS_CS_MUD_BIT 7 1245 # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT) 1246 # define SYS_CS_DUD (1 << 6) 1247 # define SYS_CS_CUD (1 << 5) 1248 1249 # define SYS_CS_MIR_BIT 2 1250 # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT) 1251 # define SYS_CS_DIR (1 << 1) 1252 # define SYS_CS_CIR (1 << 0) 1253 1254 # define SYS_CS_MUX_AUX 0x1 1255 # define SYS_CS_MUX_FQ0 0x2 1256 # define SYS_CS_MUX_FQ1 0x3 1257 # define SYS_CS_MUX_FQ2 0x4 1258 # define SYS_CS_MUX_FQ3 0x5 1259 # define SYS_CS_MUX_FQ4 0x6 1260 # define SYS_CS_MUX_FQ5 0x7 1261 #define SYS_CPUPLL 0xB1900060 1262 #define SYS_AUXPLL 0xB1900064 1263 1264 /* AC97 Controller */ 1265 #define AC97C_CONFIG 0xB0000000 1266 # define AC97C_RECV_SLOTS_BIT 13 1267 # define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) 1268 # define AC97C_XMIT_SLOTS_BIT 3 1269 # define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) 1270 # define AC97C_SG (1 << 2) 1271 # define AC97C_SYNC (1 << 1) 1272 # define AC97C_RESET (1 << 0) 1273 #define AC97C_STATUS 0xB0000004 1274 # define AC97C_XU (1 << 11) 1275 # define AC97C_XO (1 << 10) 1276 # define AC97C_RU (1 << 9) 1277 # define AC97C_RO (1 << 8) 1278 # define AC97C_READY (1 << 7) 1279 # define AC97C_CP (1 << 6) 1280 # define AC97C_TR (1 << 5) 1281 # define AC97C_TE (1 << 4) 1282 # define AC97C_TF (1 << 3) 1283 # define AC97C_RR (1 << 2) 1284 # define AC97C_RE (1 << 1) 1285 # define AC97C_RF (1 << 0) 1286 #define AC97C_DATA 0xB0000008 1287 #define AC97C_CMD 0xB000000C 1288 # define AC97C_WD_BIT 16 1289 # define AC97C_READ (1 << 7) 1290 # define AC97C_INDEX_MASK 0x7f 1291 #define AC97C_CNTRL 0xB0000010 1292 # define AC97C_RS (1 << 1) 1293 # define AC97C_CE (1 << 0) 1294 1295 1296 /* The PCI chip selects are outside the 32bit space, and since we can't 1297 * just program the 36bit addresses into BARs, we have to take a chunk 1298 * out of the 32bit space and reserve it for PCI. When these addresses 1299 * are ioremap()ed, they'll be fixed up to the real 36bit address before 1300 * being passed to the real ioremap function. 1301 */ 1302 #define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4) 1303 #define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF) 1304 1305 /* for PCI IO it's simpler because we get to do the ioremap ourselves and then 1306 * adjust the device's resources. 1307 */ 1308 #define ALCHEMY_PCI_IOWIN_START 0x00001000 1309 #define ALCHEMY_PCI_IOWIN_END 0x0000FFFF 1310 1311 #ifdef CONFIG_PCI 1312 1313 #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ 1314 #define IOPORT_RESOURCE_END 0xffffffff 1315 #define IOMEM_RESOURCE_START 0x10000000 1316 #define IOMEM_RESOURCE_END 0xfffffffffULL 1317 1318 #else 1319 1320 /* Don't allow any legacy ports probing */ 1321 #define IOPORT_RESOURCE_START 0x10000000 1322 #define IOPORT_RESOURCE_END 0xffffffff 1323 #define IOMEM_RESOURCE_START 0x10000000 1324 #define IOMEM_RESOURCE_END 0xfffffffffULL 1325 1326 #endif 1327 1328 /* PCI controller block register offsets */ 1329 #define PCI_REG_CMEM 0x0000 1330 #define PCI_REG_CONFIG 0x0004 1331 #define PCI_REG_B2BMASK_CCH 0x0008 1332 #define PCI_REG_B2BBASE0_VID 0x000C 1333 #define PCI_REG_B2BBASE1_SID 0x0010 1334 #define PCI_REG_MWMASK_DEV 0x0014 1335 #define PCI_REG_MWBASE_REV_CCL 0x0018 1336 #define PCI_REG_ERR_ADDR 0x001C 1337 #define PCI_REG_SPEC_INTACK 0x0020 1338 #define PCI_REG_ID 0x0100 1339 #define PCI_REG_STATCMD 0x0104 1340 #define PCI_REG_CLASSREV 0x0108 1341 #define PCI_REG_PARAM 0x010C 1342 #define PCI_REG_MBAR 0x0110 1343 #define PCI_REG_TIMEOUT 0x0140 1344 1345 /* PCI controller block register bits */ 1346 #define PCI_CMEM_E (1 << 28) /* enable cacheable memory */ 1347 #define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14) 1348 #define PCI_CMEM_CMMASK(x) ((x) & 0x3fff) 1349 #define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */ 1350 #define PCI_CONFIG_ET (1 << 26) /* error in target mode */ 1351 #define PCI_CONFIG_EF (1 << 25) /* fatal error */ 1352 #define PCI_CONFIG_EP (1 << 24) /* parity error */ 1353 #define PCI_CONFIG_EM (1 << 23) /* multiple errors */ 1354 #define PCI_CONFIG_BM (1 << 22) /* bad master error */ 1355 #define PCI_CONFIG_PD (1 << 20) /* PCI Disable */ 1356 #define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */ 1357 #define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */ 1358 #define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */ 1359 #define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */ 1360 #define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */ 1361 #define PCI_CONFIG_IMM (1 << 11) /* int on master abort */ 1362 #define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */ 1363 #define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */ 1364 #define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */ 1365 #define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */ 1366 #define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */ 1367 #define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */ 1368 #define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */ 1369 #define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */ 1370 #define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */ 1371 #define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */ 1372 #define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */ 1373 #define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */ 1374 #define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */ 1375 #define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16) 1376 #define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */ 1377 #define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16) 1378 #define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff) 1379 #define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16) 1380 #define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff) 1381 #define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16) 1382 #define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff) 1383 #define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16) 1384 #define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8) 1385 #define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff) 1386 #define PCI_ID_DID(x) (((x) & 0xffff) << 16) 1387 #define PCI_ID_VID(x) ((x) & 0xffff) 1388 #define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16) 1389 #define PCI_STATCMD_CMD(x) ((x) & 0xffff) 1390 #define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8) 1391 #define PCI_CLASSREV_REV(x) ((x) & 0xff) 1392 #define PCI_PARAM_BIST(x) (((x) & 0xff) << 24) 1393 #define PCI_PARAM_HT(x) (((x) & 0xff) << 16) 1394 #define PCI_PARAM_LT(x) (((x) & 0xff) << 8) 1395 #define PCI_PARAM_CLS(x) ((x) & 0xff) 1396 #define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */ 1397 #define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */ 1398 1399 #endif 1400