1 /* 2 * Atheros AR71XX/AR724X/AR913X SoC register definitions 3 * 4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 5 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> 6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 7 * 8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 */ 14 15 #ifndef __ASM_MACH_AR71XX_REGS_H 16 #define __ASM_MACH_AR71XX_REGS_H 17 18 #include <linux/types.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/bitops.h> 22 23 #define AR71XX_APB_BASE 0x18000000 24 #define AR71XX_EHCI_BASE 0x1b000000 25 #define AR71XX_EHCI_SIZE 0x1000 26 #define AR71XX_OHCI_BASE 0x1c000000 27 #define AR71XX_OHCI_SIZE 0x1000 28 #define AR71XX_SPI_BASE 0x1f000000 29 #define AR71XX_SPI_SIZE 0x01000000 30 31 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) 32 #define AR71XX_DDR_CTRL_SIZE 0x100 33 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) 34 #define AR71XX_UART_SIZE 0x100 35 #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) 36 #define AR71XX_USB_CTRL_SIZE 0x100 37 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) 38 #define AR71XX_GPIO_SIZE 0x100 39 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) 40 #define AR71XX_PLL_SIZE 0x100 41 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) 42 #define AR71XX_RESET_SIZE 0x100 43 44 #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) 45 #define AR7240_USB_CTRL_SIZE 0x100 46 #define AR7240_OHCI_BASE 0x1b000000 47 #define AR7240_OHCI_SIZE 0x1000 48 49 #define AR724X_EHCI_BASE 0x1b000000 50 #define AR724X_EHCI_SIZE 0x1000 51 52 #define AR913X_EHCI_BASE 0x1b000000 53 #define AR913X_EHCI_SIZE 0x1000 54 #define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) 55 #define AR913X_WMAC_SIZE 0x30000 56 57 #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) 58 #define AR933X_UART_SIZE 0x14 59 #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) 60 #define AR933X_WMAC_SIZE 0x20000 61 #define AR933X_EHCI_BASE 0x1b000000 62 #define AR933X_EHCI_SIZE 0x1000 63 64 #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) 65 #define AR934X_WMAC_SIZE 0x20000 66 #define AR934X_EHCI_BASE 0x1b000000 67 #define AR934X_EHCI_SIZE 0x200 68 #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) 69 #define AR934X_SRIF_SIZE 0x1000 70 71 /* 72 * DDR_CTRL block 73 */ 74 #define AR71XX_DDR_REG_PCI_WIN0 0x7c 75 #define AR71XX_DDR_REG_PCI_WIN1 0x80 76 #define AR71XX_DDR_REG_PCI_WIN2 0x84 77 #define AR71XX_DDR_REG_PCI_WIN3 0x88 78 #define AR71XX_DDR_REG_PCI_WIN4 0x8c 79 #define AR71XX_DDR_REG_PCI_WIN5 0x90 80 #define AR71XX_DDR_REG_PCI_WIN6 0x94 81 #define AR71XX_DDR_REG_PCI_WIN7 0x98 82 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c 83 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0 84 #define AR71XX_DDR_REG_FLUSH_USB 0xa4 85 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8 86 87 #define AR724X_DDR_REG_FLUSH_GE0 0x7c 88 #define AR724X_DDR_REG_FLUSH_GE1 0x80 89 #define AR724X_DDR_REG_FLUSH_USB 0x84 90 #define AR724X_DDR_REG_FLUSH_PCIE 0x88 91 92 #define AR913X_DDR_REG_FLUSH_GE0 0x7c 93 #define AR913X_DDR_REG_FLUSH_GE1 0x80 94 #define AR913X_DDR_REG_FLUSH_USB 0x84 95 #define AR913X_DDR_REG_FLUSH_WMAC 0x88 96 97 #define AR933X_DDR_REG_FLUSH_GE0 0x7c 98 #define AR933X_DDR_REG_FLUSH_GE1 0x80 99 #define AR933X_DDR_REG_FLUSH_USB 0x84 100 #define AR933X_DDR_REG_FLUSH_WMAC 0x88 101 102 #define AR934X_DDR_REG_FLUSH_GE0 0x9c 103 #define AR934X_DDR_REG_FLUSH_GE1 0xa0 104 #define AR934X_DDR_REG_FLUSH_USB 0xa4 105 #define AR934X_DDR_REG_FLUSH_PCIE 0xa8 106 #define AR934X_DDR_REG_FLUSH_WMAC 0xac 107 108 /* 109 * PLL block 110 */ 111 #define AR71XX_PLL_REG_CPU_CONFIG 0x00 112 #define AR71XX_PLL_REG_SEC_CONFIG 0x04 113 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 114 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 115 116 #define AR71XX_PLL_DIV_SHIFT 3 117 #define AR71XX_PLL_DIV_MASK 0x1f 118 #define AR71XX_CPU_DIV_SHIFT 16 119 #define AR71XX_CPU_DIV_MASK 0x3 120 #define AR71XX_DDR_DIV_SHIFT 18 121 #define AR71XX_DDR_DIV_MASK 0x3 122 #define AR71XX_AHB_DIV_SHIFT 20 123 #define AR71XX_AHB_DIV_MASK 0x7 124 125 #define AR724X_PLL_REG_CPU_CONFIG 0x00 126 #define AR724X_PLL_REG_PCIE_CONFIG 0x18 127 128 #define AR724X_PLL_DIV_SHIFT 0 129 #define AR724X_PLL_DIV_MASK 0x3ff 130 #define AR724X_PLL_REF_DIV_SHIFT 10 131 #define AR724X_PLL_REF_DIV_MASK 0xf 132 #define AR724X_AHB_DIV_SHIFT 19 133 #define AR724X_AHB_DIV_MASK 0x1 134 #define AR724X_DDR_DIV_SHIFT 22 135 #define AR724X_DDR_DIV_MASK 0x3 136 137 #define AR913X_PLL_REG_CPU_CONFIG 0x00 138 #define AR913X_PLL_REG_ETH_CONFIG 0x04 139 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 140 #define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 141 142 #define AR913X_PLL_DIV_SHIFT 0 143 #define AR913X_PLL_DIV_MASK 0x3ff 144 #define AR913X_DDR_DIV_SHIFT 22 145 #define AR913X_DDR_DIV_MASK 0x3 146 #define AR913X_AHB_DIV_SHIFT 19 147 #define AR913X_AHB_DIV_MASK 0x1 148 149 #define AR933X_PLL_CPU_CONFIG_REG 0x00 150 #define AR933X_PLL_CLOCK_CTRL_REG 0x08 151 152 #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 153 #define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f 154 #define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 155 #define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 156 #define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 157 #define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 158 159 #define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) 160 #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 161 #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 162 #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 163 #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 164 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 165 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 166 167 #define AR934X_PLL_CPU_CONFIG_REG 0x00 168 #define AR934X_PLL_DDR_CONFIG_REG 0x04 169 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 170 171 #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 172 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 173 #define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 174 #define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f 175 #define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 176 #define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 177 #define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 178 #define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 179 180 #define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 181 #define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 182 #define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 183 #define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f 184 #define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 185 #define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 186 #define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 187 #define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 188 189 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 190 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 191 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 192 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 193 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 194 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 195 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 196 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 197 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 198 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 199 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 200 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 201 202 /* 203 * USB_CONFIG block 204 */ 205 #define AR71XX_USB_CTRL_REG_FLADJ 0x00 206 #define AR71XX_USB_CTRL_REG_CONFIG 0x04 207 208 /* 209 * RESET block 210 */ 211 #define AR71XX_RESET_REG_TIMER 0x00 212 #define AR71XX_RESET_REG_TIMER_RELOAD 0x04 213 #define AR71XX_RESET_REG_WDOG_CTRL 0x08 214 #define AR71XX_RESET_REG_WDOG 0x0c 215 #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 216 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 217 #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 218 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c 219 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 220 #define AR71XX_RESET_REG_RESET_MODULE 0x24 221 #define AR71XX_RESET_REG_PERFC_CTRL 0x2c 222 #define AR71XX_RESET_REG_PERFC0 0x30 223 #define AR71XX_RESET_REG_PERFC1 0x34 224 #define AR71XX_RESET_REG_REV_ID 0x90 225 226 #define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 227 #define AR913X_RESET_REG_RESET_MODULE 0x1c 228 #define AR913X_RESET_REG_PERF_CTRL 0x20 229 #define AR913X_RESET_REG_PERFC0 0x24 230 #define AR913X_RESET_REG_PERFC1 0x28 231 232 #define AR724X_RESET_REG_RESET_MODULE 0x1c 233 234 #define AR933X_RESET_REG_RESET_MODULE 0x1c 235 #define AR933X_RESET_REG_BOOTSTRAP 0xac 236 237 #define AR934X_RESET_REG_RESET_MODULE 0x1c 238 #define AR934X_RESET_REG_BOOTSTRAP 0xb0 239 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac 240 241 #define MISC_INT_ETHSW BIT(12) 242 #define MISC_INT_TIMER4 BIT(10) 243 #define MISC_INT_TIMER3 BIT(9) 244 #define MISC_INT_TIMER2 BIT(8) 245 #define MISC_INT_DMA BIT(7) 246 #define MISC_INT_OHCI BIT(6) 247 #define MISC_INT_PERFC BIT(5) 248 #define MISC_INT_WDOG BIT(4) 249 #define MISC_INT_UART BIT(3) 250 #define MISC_INT_GPIO BIT(2) 251 #define MISC_INT_ERROR BIT(1) 252 #define MISC_INT_TIMER BIT(0) 253 254 #define AR71XX_RESET_EXTERNAL BIT(28) 255 #define AR71XX_RESET_FULL_CHIP BIT(24) 256 #define AR71XX_RESET_CPU_NMI BIT(21) 257 #define AR71XX_RESET_CPU_COLD BIT(20) 258 #define AR71XX_RESET_DMA BIT(19) 259 #define AR71XX_RESET_SLIC BIT(18) 260 #define AR71XX_RESET_STEREO BIT(17) 261 #define AR71XX_RESET_DDR BIT(16) 262 #define AR71XX_RESET_GE1_MAC BIT(13) 263 #define AR71XX_RESET_GE1_PHY BIT(12) 264 #define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) 265 #define AR71XX_RESET_GE0_MAC BIT(9) 266 #define AR71XX_RESET_GE0_PHY BIT(8) 267 #define AR71XX_RESET_USB_OHCI_DLL BIT(6) 268 #define AR71XX_RESET_USB_HOST BIT(5) 269 #define AR71XX_RESET_USB_PHY BIT(4) 270 #define AR71XX_RESET_PCI_BUS BIT(1) 271 #define AR71XX_RESET_PCI_CORE BIT(0) 272 273 #define AR7240_RESET_USB_HOST BIT(5) 274 #define AR7240_RESET_OHCI_DLL BIT(3) 275 276 #define AR724X_RESET_GE1_MDIO BIT(23) 277 #define AR724X_RESET_GE0_MDIO BIT(22) 278 #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) 279 #define AR724X_RESET_PCIE_PHY BIT(7) 280 #define AR724X_RESET_PCIE BIT(6) 281 #define AR724X_RESET_USB_HOST BIT(5) 282 #define AR724X_RESET_USB_PHY BIT(4) 283 #define AR724X_RESET_USBSUS_OVERRIDE BIT(3) 284 285 #define AR913X_RESET_AMBA2WMAC BIT(22) 286 #define AR913X_RESET_USBSUS_OVERRIDE BIT(10) 287 #define AR913X_RESET_USB_HOST BIT(5) 288 #define AR913X_RESET_USB_PHY BIT(4) 289 290 #define AR933X_RESET_WMAC BIT(11) 291 #define AR933X_RESET_USB_HOST BIT(5) 292 #define AR933X_RESET_USB_PHY BIT(4) 293 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) 294 295 #define AR934X_RESET_USB_PHY_ANALOG BIT(11) 296 #define AR934X_RESET_USB_HOST BIT(5) 297 #define AR934X_RESET_USB_PHY BIT(4) 298 #define AR934X_RESET_USBSUS_OVERRIDE BIT(3) 299 300 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) 301 302 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) 303 #define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) 304 #define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) 305 #define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) 306 #define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) 307 #define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) 308 #define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) 309 #define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) 310 #define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) 311 #define AR934X_BOOTSTRAP_PCIE_RC BIT(6) 312 #define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) 313 #define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) 314 #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) 315 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) 316 #define AR934X_BOOTSTRAP_DDR1 BIT(0) 317 318 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) 319 #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) 320 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) 321 #define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) 322 #define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) 323 #define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) 324 #define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) 325 #define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) 326 #define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) 327 #define AR934X_PCIE_WMAC_INT_WMAC_ALL \ 328 (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ 329 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) 330 331 #define AR934X_PCIE_WMAC_INT_PCIE_ALL \ 332 (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ 333 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ 334 AR934X_PCIE_WMAC_INT_PCIE_RC3) 335 336 #define REV_ID_MAJOR_MASK 0xfff0 337 #define REV_ID_MAJOR_AR71XX 0x00a0 338 #define REV_ID_MAJOR_AR913X 0x00b0 339 #define REV_ID_MAJOR_AR7240 0x00c0 340 #define REV_ID_MAJOR_AR7241 0x0100 341 #define REV_ID_MAJOR_AR7242 0x1100 342 #define REV_ID_MAJOR_AR9330 0x0110 343 #define REV_ID_MAJOR_AR9331 0x1110 344 #define REV_ID_MAJOR_AR9341 0x0120 345 #define REV_ID_MAJOR_AR9342 0x1120 346 #define REV_ID_MAJOR_AR9344 0x2120 347 348 #define AR71XX_REV_ID_MINOR_MASK 0x3 349 #define AR71XX_REV_ID_MINOR_AR7130 0x0 350 #define AR71XX_REV_ID_MINOR_AR7141 0x1 351 #define AR71XX_REV_ID_MINOR_AR7161 0x2 352 #define AR71XX_REV_ID_REVISION_MASK 0x3 353 #define AR71XX_REV_ID_REVISION_SHIFT 2 354 355 #define AR913X_REV_ID_MINOR_MASK 0x3 356 #define AR913X_REV_ID_MINOR_AR9130 0x0 357 #define AR913X_REV_ID_MINOR_AR9132 0x1 358 #define AR913X_REV_ID_REVISION_MASK 0x3 359 #define AR913X_REV_ID_REVISION_SHIFT 2 360 361 #define AR933X_REV_ID_REVISION_MASK 0x3 362 363 #define AR724X_REV_ID_REVISION_MASK 0x3 364 365 #define AR934X_REV_ID_REVISION_MASK 0xf 366 367 /* 368 * SPI block 369 */ 370 #define AR71XX_SPI_REG_FS 0x00 /* Function Select */ 371 #define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ 372 #define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ 373 #define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ 374 375 #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ 376 377 #define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ 378 #define AR71XX_SPI_CTRL_DIV_MASK 0x3f 379 380 #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ 381 #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ 382 #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) 383 #define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) 384 #define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) 385 #define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) 386 #define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ 387 AR71XX_SPI_IOC_CS2) 388 389 /* 390 * GPIO block 391 */ 392 #define AR71XX_GPIO_REG_OE 0x00 393 #define AR71XX_GPIO_REG_IN 0x04 394 #define AR71XX_GPIO_REG_OUT 0x08 395 #define AR71XX_GPIO_REG_SET 0x0c 396 #define AR71XX_GPIO_REG_CLEAR 0x10 397 #define AR71XX_GPIO_REG_INT_MODE 0x14 398 #define AR71XX_GPIO_REG_INT_TYPE 0x18 399 #define AR71XX_GPIO_REG_INT_POLARITY 0x1c 400 #define AR71XX_GPIO_REG_INT_PENDING 0x20 401 #define AR71XX_GPIO_REG_INT_ENABLE 0x24 402 #define AR71XX_GPIO_REG_FUNC 0x28 403 404 #define AR71XX_GPIO_COUNT 16 405 #define AR7240_GPIO_COUNT 18 406 #define AR7241_GPIO_COUNT 20 407 #define AR913X_GPIO_COUNT 22 408 #define AR933X_GPIO_COUNT 30 409 #define AR934X_GPIO_COUNT 23 410 411 /* 412 * SRIF block 413 */ 414 #define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 415 #define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 416 #define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 417 418 #define AR934X_SRIF_DDR_DPLL1_REG 0x240 419 #define AR934X_SRIF_DDR_DPLL2_REG 0x244 420 #define AR934X_SRIF_DDR_DPLL3_REG 0x248 421 422 #define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 423 #define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f 424 #define AR934X_SRIF_DPLL1_NINT_SHIFT 18 425 #define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff 426 #define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff 427 428 #define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) 429 #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 430 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 431 432 #endif /* __ASM_MACH_AR71XX_REGS_H */ 433