xref: /linux/arch/mips/include/asm/mach-ath25/ath25_platform.h (revision ca55b2fef3a9373fcfc30f82fd26bc7fccbda732)
1 #ifndef __ASM_MACH_ATH25_PLATFORM_H
2 #define __ASM_MACH_ATH25_PLATFORM_H
3 
4 #include <linux/etherdevice.h>
5 
6 /*
7  * This is board-specific data that is stored in a "fixed" location in flash.
8  * It is shared across operating systems, so it should not be changed lightly.
9  * The main reason we need it is in order to extract the ethernet MAC
10  * address(es).
11  */
12 struct ath25_boarddata {
13 	u32 magic;                   /* board data is valid */
14 #define ATH25_BD_MAGIC 0x35333131    /* "5311", for all 531x/231x platforms */
15 	u16 cksum;                   /* checksum (starting with BD_REV 2) */
16 	u16 rev;                     /* revision of this struct */
17 #define BD_REV 4
18 	char board_name[64];         /* Name of board */
19 	u16 major;                   /* Board major number */
20 	u16 minor;                   /* Board minor number */
21 	u32 flags;                   /* Board configuration */
22 #define BD_ENET0        0x00000001   /* ENET0 is stuffed */
23 #define BD_ENET1        0x00000002   /* ENET1 is stuffed */
24 #define BD_UART1        0x00000004   /* UART1 is stuffed */
25 #define BD_UART0        0x00000008   /* UART0 is stuffed (dma) */
26 #define BD_RSTFACTORY   0x00000010   /* Reset factory defaults stuffed */
27 #define BD_SYSLED       0x00000020   /* System LED stuffed */
28 #define BD_EXTUARTCLK   0x00000040   /* External UART clock */
29 #define BD_CPUFREQ      0x00000080   /* cpu freq is valid in nvram */
30 #define BD_SYSFREQ      0x00000100   /* sys freq is set in nvram */
31 #define BD_WLAN0        0x00000200   /* Enable WLAN0 */
32 #define BD_MEMCAP       0x00000400   /* CAP SDRAM @ mem_cap for testing */
33 #define BD_DISWATCHDOG  0x00000800   /* disable system watchdog */
34 #define BD_WLAN1        0x00001000   /* Enable WLAN1 (ar5212) */
35 #define BD_ISCASPER     0x00002000   /* FLAG for AR2312 */
36 #define BD_WLAN0_2G_EN  0x00004000   /* FLAG for radio0_2G */
37 #define BD_WLAN0_5G_EN  0x00008000   /* FLAG for radio0_2G */
38 #define BD_WLAN1_2G_EN  0x00020000   /* FLAG for radio0_2G */
39 #define BD_WLAN1_5G_EN  0x00040000   /* FLAG for radio0_2G */
40 	u16 reset_config_gpio;       /* Reset factory GPIO pin */
41 	u16 sys_led_gpio;            /* System LED GPIO pin */
42 
43 	u32 cpu_freq;                /* CPU core frequency in Hz */
44 	u32 sys_freq;                /* System frequency in Hz */
45 	u32 cnt_freq;                /* Calculated C0_COUNT frequency */
46 
47 	u8  wlan0_mac[ETH_ALEN];
48 	u8  enet0_mac[ETH_ALEN];
49 	u8  enet1_mac[ETH_ALEN];
50 
51 	u16 pci_id;                  /* Pseudo PCIID for common code */
52 	u16 mem_cap;                 /* cap bank1 in MB */
53 
54 	/* version 3 */
55 	u8  wlan1_mac[ETH_ALEN];     /* (ar5212) */
56 };
57 
58 #define BOARD_CONFIG_BUFSZ		0x1000
59 
60 /*
61  * Platform device information for the Wireless MAC
62  */
63 struct ar231x_board_config {
64 	u16 devid;
65 
66 	/* board config data */
67 	struct ath25_boarddata *config;
68 
69 	/* radio calibration data */
70 	const char *radio;
71 };
72 
73 #endif /* __ASM_MACH_ATH25_PLATFORM_H */
74