1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 7 * Authors: Sanjay Lal <sanjayl@kymasys.com> 8 */ 9 10 #ifndef __MIPS_KVM_HOST_H__ 11 #define __MIPS_KVM_HOST_H__ 12 13 #include <linux/mutex.h> 14 #include <linux/hrtimer.h> 15 #include <linux/interrupt.h> 16 #include <linux/types.h> 17 #include <linux/kvm.h> 18 #include <linux/kvm_types.h> 19 #include <linux/threads.h> 20 #include <linux/spinlock.h> 21 22 /* MIPS KVM register ids */ 23 #define MIPS_CP0_32(_R, _S) \ 24 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S))) 25 26 #define MIPS_CP0_64(_R, _S) \ 27 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) 28 29 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) 30 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0) 31 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0) 32 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) 33 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) 34 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) 35 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) 36 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) 37 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) 38 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) 39 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) 40 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) 41 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) 42 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) 43 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) 44 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) 45 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) 46 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) 47 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) 48 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) 49 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) 50 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) 51 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) 52 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) 53 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7) 54 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) 55 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) 56 57 58 #define KVM_MAX_VCPUS 1 59 #define KVM_USER_MEM_SLOTS 8 60 /* memory slots that does not exposed to userspace */ 61 #define KVM_PRIVATE_MEM_SLOTS 0 62 63 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 64 65 66 67 /* Special address that contains the comm page, used for reducing # of traps */ 68 #define KVM_GUEST_COMMPAGE_ADDR 0x0 69 70 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \ 71 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0)) 72 73 #define KVM_GUEST_KUSEG 0x00000000UL 74 #define KVM_GUEST_KSEG0 0x40000000UL 75 #define KVM_GUEST_KSEG23 0x60000000UL 76 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000) 77 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) 78 79 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) 80 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1) 81 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23) 82 83 /* 84 * Map an address to a certain kernel segment 85 */ 86 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) 87 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1) 88 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23) 89 90 #define KVM_INVALID_PAGE 0xdeadbeef 91 #define KVM_INVALID_INST 0xdeadbeef 92 #define KVM_INVALID_ADDR 0xdeadbeef 93 94 #define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL 95 96 #define GUEST_TICKS_PER_JIFFY (40000000/HZ) 97 #define MS_TO_NS(x) (x * 1E6L) 98 99 #define CAUSEB_DC 27 100 #define CAUSEF_DC (_ULCAST_(1) << 27) 101 102 extern atomic_t kvm_mips_instance; 103 extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn); 104 extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn); 105 extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn); 106 107 struct kvm_vm_stat { 108 u32 remote_tlb_flush; 109 }; 110 111 struct kvm_vcpu_stat { 112 u32 wait_exits; 113 u32 cache_exits; 114 u32 signal_exits; 115 u32 int_exits; 116 u32 cop_unusable_exits; 117 u32 tlbmod_exits; 118 u32 tlbmiss_ld_exits; 119 u32 tlbmiss_st_exits; 120 u32 addrerr_st_exits; 121 u32 addrerr_ld_exits; 122 u32 syscall_exits; 123 u32 resvd_inst_exits; 124 u32 break_inst_exits; 125 u32 trap_inst_exits; 126 u32 msa_fpe_exits; 127 u32 fpe_exits; 128 u32 msa_disabled_exits; 129 u32 flush_dcache_exits; 130 u32 halt_successful_poll; 131 u32 halt_attempted_poll; 132 u32 halt_wakeup; 133 }; 134 135 enum kvm_mips_exit_types { 136 WAIT_EXITS, 137 CACHE_EXITS, 138 SIGNAL_EXITS, 139 INT_EXITS, 140 COP_UNUSABLE_EXITS, 141 TLBMOD_EXITS, 142 TLBMISS_LD_EXITS, 143 TLBMISS_ST_EXITS, 144 ADDRERR_ST_EXITS, 145 ADDRERR_LD_EXITS, 146 SYSCALL_EXITS, 147 RESVD_INST_EXITS, 148 BREAK_INST_EXITS, 149 TRAP_INST_EXITS, 150 MSA_FPE_EXITS, 151 FPE_EXITS, 152 MSA_DISABLED_EXITS, 153 FLUSH_DCACHE_EXITS, 154 MAX_KVM_MIPS_EXIT_TYPES 155 }; 156 157 struct kvm_arch_memory_slot { 158 }; 159 160 struct kvm_arch { 161 /* Guest GVA->HPA page table */ 162 unsigned long *guest_pmap; 163 unsigned long guest_pmap_npages; 164 165 /* Wired host TLB used for the commpage */ 166 int commpage_tlb; 167 }; 168 169 #define N_MIPS_COPROC_REGS 32 170 #define N_MIPS_COPROC_SEL 8 171 172 struct mips_coproc { 173 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; 174 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS 175 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; 176 #endif 177 }; 178 179 /* 180 * Coprocessor 0 register names 181 */ 182 #define MIPS_CP0_TLB_INDEX 0 183 #define MIPS_CP0_TLB_RANDOM 1 184 #define MIPS_CP0_TLB_LOW 2 185 #define MIPS_CP0_TLB_LO0 2 186 #define MIPS_CP0_TLB_LO1 3 187 #define MIPS_CP0_TLB_CONTEXT 4 188 #define MIPS_CP0_TLB_PG_MASK 5 189 #define MIPS_CP0_TLB_WIRED 6 190 #define MIPS_CP0_HWRENA 7 191 #define MIPS_CP0_BAD_VADDR 8 192 #define MIPS_CP0_COUNT 9 193 #define MIPS_CP0_TLB_HI 10 194 #define MIPS_CP0_COMPARE 11 195 #define MIPS_CP0_STATUS 12 196 #define MIPS_CP0_CAUSE 13 197 #define MIPS_CP0_EXC_PC 14 198 #define MIPS_CP0_PRID 15 199 #define MIPS_CP0_CONFIG 16 200 #define MIPS_CP0_LLADDR 17 201 #define MIPS_CP0_WATCH_LO 18 202 #define MIPS_CP0_WATCH_HI 19 203 #define MIPS_CP0_TLB_XCONTEXT 20 204 #define MIPS_CP0_ECC 26 205 #define MIPS_CP0_CACHE_ERR 27 206 #define MIPS_CP0_TAG_LO 28 207 #define MIPS_CP0_TAG_HI 29 208 #define MIPS_CP0_ERROR_PC 30 209 #define MIPS_CP0_DEBUG 23 210 #define MIPS_CP0_DEPC 24 211 #define MIPS_CP0_PERFCNT 25 212 #define MIPS_CP0_ERRCTL 26 213 #define MIPS_CP0_DATA_LO 28 214 #define MIPS_CP0_DATA_HI 29 215 #define MIPS_CP0_DESAVE 31 216 217 #define MIPS_CP0_CONFIG_SEL 0 218 #define MIPS_CP0_CONFIG1_SEL 1 219 #define MIPS_CP0_CONFIG2_SEL 2 220 #define MIPS_CP0_CONFIG3_SEL 3 221 #define MIPS_CP0_CONFIG4_SEL 4 222 #define MIPS_CP0_CONFIG5_SEL 5 223 224 /* Config0 register bits */ 225 #define CP0C0_M 31 226 #define CP0C0_K23 28 227 #define CP0C0_KU 25 228 #define CP0C0_MDU 20 229 #define CP0C0_MM 17 230 #define CP0C0_BM 16 231 #define CP0C0_BE 15 232 #define CP0C0_AT 13 233 #define CP0C0_AR 10 234 #define CP0C0_MT 7 235 #define CP0C0_VI 3 236 #define CP0C0_K0 0 237 238 /* Config1 register bits */ 239 #define CP0C1_M 31 240 #define CP0C1_MMU 25 241 #define CP0C1_IS 22 242 #define CP0C1_IL 19 243 #define CP0C1_IA 16 244 #define CP0C1_DS 13 245 #define CP0C1_DL 10 246 #define CP0C1_DA 7 247 #define CP0C1_C2 6 248 #define CP0C1_MD 5 249 #define CP0C1_PC 4 250 #define CP0C1_WR 3 251 #define CP0C1_CA 2 252 #define CP0C1_EP 1 253 #define CP0C1_FP 0 254 255 /* Config2 Register bits */ 256 #define CP0C2_M 31 257 #define CP0C2_TU 28 258 #define CP0C2_TS 24 259 #define CP0C2_TL 20 260 #define CP0C2_TA 16 261 #define CP0C2_SU 12 262 #define CP0C2_SS 8 263 #define CP0C2_SL 4 264 #define CP0C2_SA 0 265 266 /* Config3 Register bits */ 267 #define CP0C3_M 31 268 #define CP0C3_ISA_ON_EXC 16 269 #define CP0C3_ULRI 13 270 #define CP0C3_DSPP 10 271 #define CP0C3_LPA 7 272 #define CP0C3_VEIC 6 273 #define CP0C3_VInt 5 274 #define CP0C3_SP 4 275 #define CP0C3_MT 2 276 #define CP0C3_SM 1 277 #define CP0C3_TL 0 278 279 /* MMU types, the first four entries have the same layout as the 280 CP0C0_MT field. */ 281 enum mips_mmu_types { 282 MMU_TYPE_NONE, 283 MMU_TYPE_R4000, 284 MMU_TYPE_RESERVED, 285 MMU_TYPE_FMT, 286 MMU_TYPE_R3000, 287 MMU_TYPE_R6000, 288 MMU_TYPE_R8000 289 }; 290 291 /* 292 * Trap codes 293 */ 294 #define T_INT 0 /* Interrupt pending */ 295 #define T_TLB_MOD 1 /* TLB modified fault */ 296 #define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */ 297 #define T_TLB_ST_MISS 3 /* TLB miss on a store */ 298 #define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */ 299 #define T_ADDR_ERR_ST 5 /* Address error on a store */ 300 #define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */ 301 #define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */ 302 #define T_SYSCALL 8 /* System call */ 303 #define T_BREAK 9 /* Breakpoint */ 304 #define T_RES_INST 10 /* Reserved instruction exception */ 305 #define T_COP_UNUSABLE 11 /* Coprocessor unusable */ 306 #define T_OVFLOW 12 /* Arithmetic overflow */ 307 308 /* 309 * Trap definitions added for r4000 port. 310 */ 311 #define T_TRAP 13 /* Trap instruction */ 312 #define T_VCEI 14 /* Virtual coherency exception */ 313 #define T_MSAFPE 14 /* MSA floating point exception */ 314 #define T_FPE 15 /* Floating point exception */ 315 #define T_MSADIS 21 /* MSA disabled exception */ 316 #define T_WATCH 23 /* Watch address reference */ 317 #define T_VCED 31 /* Virtual coherency data */ 318 319 /* Resume Flags */ 320 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */ 321 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */ 322 323 #define RESUME_GUEST 0 324 #define RESUME_GUEST_DR RESUME_FLAG_DR 325 #define RESUME_HOST RESUME_FLAG_HOST 326 327 enum emulation_result { 328 EMULATE_DONE, /* no further processing */ 329 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */ 330 EMULATE_FAIL, /* can't emulate this instruction */ 331 EMULATE_WAIT, /* WAIT instruction */ 332 EMULATE_PRIV_FAIL, 333 }; 334 335 #define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */ 336 #define MIPS3_PG_V 0x00000002 /* Valid */ 337 #define MIPS3_PG_NV 0x00000000 338 #define MIPS3_PG_D 0x00000004 /* Dirty */ 339 340 #define mips3_paddr_to_tlbpfn(x) \ 341 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME) 342 #define mips3_tlbpfn_to_paddr(x) \ 343 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT) 344 345 #define MIPS3_PG_SHIFT 6 346 #define MIPS3_PG_FRAME 0x3fffffc0 347 348 #define VPN2_MASK 0xffffe000 349 #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \ 350 ((x).tlb_lo1 & MIPS3_PG_G)) 351 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK) 352 #define TLB_ASID(x) ((x).tlb_hi & ASID_MASK) 353 #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \ 354 ? ((x).tlb_lo1 & MIPS3_PG_V) \ 355 : ((x).tlb_lo0 & MIPS3_PG_V)) 356 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \ 357 ((y) & VPN2_MASK & ~(x).tlb_mask)) 358 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \ 359 TLB_ASID(x) == ((y) & ASID_MASK)) 360 361 struct kvm_mips_tlb { 362 long tlb_mask; 363 long tlb_hi; 364 long tlb_lo0; 365 long tlb_lo1; 366 }; 367 368 #define KVM_MIPS_FPU_FPU 0x1 369 #define KVM_MIPS_FPU_MSA 0x2 370 371 #define KVM_MIPS_GUEST_TLB_SIZE 64 372 struct kvm_vcpu_arch { 373 void *host_ebase, *guest_ebase; 374 unsigned long host_stack; 375 unsigned long host_gp; 376 377 /* Host CP0 registers used when handling exits from guest */ 378 unsigned long host_cp0_badvaddr; 379 unsigned long host_cp0_cause; 380 unsigned long host_cp0_epc; 381 unsigned long host_cp0_entryhi; 382 uint32_t guest_inst; 383 384 /* GPRS */ 385 unsigned long gprs[32]; 386 unsigned long hi; 387 unsigned long lo; 388 unsigned long pc; 389 390 /* FPU State */ 391 struct mips_fpu_struct fpu; 392 /* Which FPU state is loaded (KVM_MIPS_FPU_*) */ 393 unsigned int fpu_inuse; 394 395 /* COP0 State */ 396 struct mips_coproc *cop0; 397 398 /* Host KSEG0 address of the EI/DI offset */ 399 void *kseg0_commpage; 400 401 u32 io_gpr; /* GPR used as IO source/target */ 402 403 struct hrtimer comparecount_timer; 404 /* Count timer control KVM register */ 405 uint32_t count_ctl; 406 /* Count bias from the raw time */ 407 uint32_t count_bias; 408 /* Frequency of timer in Hz */ 409 uint32_t count_hz; 410 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */ 411 s64 count_dyn_bias; 412 /* Resume time */ 413 ktime_t count_resume; 414 /* Period of timer tick in ns */ 415 u64 count_period; 416 417 /* Bitmask of exceptions that are pending */ 418 unsigned long pending_exceptions; 419 420 /* Bitmask of pending exceptions to be cleared */ 421 unsigned long pending_exceptions_clr; 422 423 unsigned long pending_load_cause; 424 425 /* Save/Restore the entryhi register when are are preempted/scheduled back in */ 426 unsigned long preempt_entryhi; 427 428 /* S/W Based TLB for guest */ 429 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE]; 430 431 /* Cached guest kernel/user ASIDs */ 432 uint32_t guest_user_asid[NR_CPUS]; 433 uint32_t guest_kernel_asid[NR_CPUS]; 434 struct mm_struct guest_kernel_mm, guest_user_mm; 435 436 int last_sched_cpu; 437 438 /* WAIT executed */ 439 int wait; 440 441 u8 fpu_enabled; 442 u8 msa_enabled; 443 }; 444 445 446 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0]) 447 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val) 448 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0]) 449 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0]) 450 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0]) 451 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val)) 452 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2]) 453 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val)) 454 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0]) 455 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val)) 456 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0]) 457 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val)) 458 #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0]) 459 #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val)) 460 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0]) 461 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val)) 462 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0]) 463 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val)) 464 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0]) 465 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val)) 466 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0]) 467 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val)) 468 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0]) 469 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val)) 470 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1]) 471 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val)) 472 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0]) 473 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val)) 474 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0]) 475 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val)) 476 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0]) 477 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val)) 478 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1]) 479 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val)) 480 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0]) 481 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1]) 482 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2]) 483 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3]) 484 #define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4]) 485 #define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5]) 486 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7]) 487 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val)) 488 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val)) 489 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val)) 490 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val)) 491 #define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val)) 492 #define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val)) 493 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val)) 494 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0]) 495 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val)) 496 497 /* 498 * Some of the guest registers may be modified asynchronously (e.g. from a 499 * hrtimer callback in hard irq context) and therefore need stronger atomicity 500 * guarantees than other registers. 501 */ 502 503 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg, 504 unsigned long val) 505 { 506 unsigned long temp; 507 do { 508 __asm__ __volatile__( 509 " .set mips3 \n" 510 " " __LL "%0, %1 \n" 511 " or %0, %2 \n" 512 " " __SC "%0, %1 \n" 513 " .set mips0 \n" 514 : "=&r" (temp), "+m" (*reg) 515 : "r" (val)); 516 } while (unlikely(!temp)); 517 } 518 519 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg, 520 unsigned long val) 521 { 522 unsigned long temp; 523 do { 524 __asm__ __volatile__( 525 " .set mips3 \n" 526 " " __LL "%0, %1 \n" 527 " and %0, %2 \n" 528 " " __SC "%0, %1 \n" 529 " .set mips0 \n" 530 : "=&r" (temp), "+m" (*reg) 531 : "r" (~val)); 532 } while (unlikely(!temp)); 533 } 534 535 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg, 536 unsigned long change, 537 unsigned long val) 538 { 539 unsigned long temp; 540 do { 541 __asm__ __volatile__( 542 " .set mips3 \n" 543 " " __LL "%0, %1 \n" 544 " and %0, %2 \n" 545 " or %0, %3 \n" 546 " " __SC "%0, %1 \n" 547 " .set mips0 \n" 548 : "=&r" (temp), "+m" (*reg) 549 : "r" (~change), "r" (val & change)); 550 } while (unlikely(!temp)); 551 } 552 553 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val)) 554 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val)) 555 556 /* Cause can be modified asynchronously from hardirq hrtimer callback */ 557 #define kvm_set_c0_guest_cause(cop0, val) \ 558 _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val) 559 #define kvm_clear_c0_guest_cause(cop0, val) \ 560 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val) 561 #define kvm_change_c0_guest_cause(cop0, change, val) \ 562 _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \ 563 change, val) 564 565 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val)) 566 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val)) 567 #define kvm_change_c0_guest_ebase(cop0, change, val) \ 568 { \ 569 kvm_clear_c0_guest_ebase(cop0, change); \ 570 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \ 571 } 572 573 /* Helpers */ 574 575 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu) 576 { 577 return (!__builtin_constant_p(cpu_has_fpu) || cpu_has_fpu) && 578 vcpu->fpu_enabled; 579 } 580 581 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu) 582 { 583 return kvm_mips_guest_can_have_fpu(vcpu) && 584 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP; 585 } 586 587 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu) 588 { 589 return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) && 590 vcpu->msa_enabled; 591 } 592 593 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu) 594 { 595 return kvm_mips_guest_can_have_msa(vcpu) && 596 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA; 597 } 598 599 struct kvm_mips_callbacks { 600 int (*handle_cop_unusable)(struct kvm_vcpu *vcpu); 601 int (*handle_tlb_mod)(struct kvm_vcpu *vcpu); 602 int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu); 603 int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu); 604 int (*handle_addr_err_st)(struct kvm_vcpu *vcpu); 605 int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu); 606 int (*handle_syscall)(struct kvm_vcpu *vcpu); 607 int (*handle_res_inst)(struct kvm_vcpu *vcpu); 608 int (*handle_break)(struct kvm_vcpu *vcpu); 609 int (*handle_trap)(struct kvm_vcpu *vcpu); 610 int (*handle_msa_fpe)(struct kvm_vcpu *vcpu); 611 int (*handle_fpe)(struct kvm_vcpu *vcpu); 612 int (*handle_msa_disabled)(struct kvm_vcpu *vcpu); 613 int (*vm_init)(struct kvm *kvm); 614 int (*vcpu_init)(struct kvm_vcpu *vcpu); 615 int (*vcpu_setup)(struct kvm_vcpu *vcpu); 616 gpa_t (*gva_to_gpa)(gva_t gva); 617 void (*queue_timer_int)(struct kvm_vcpu *vcpu); 618 void (*dequeue_timer_int)(struct kvm_vcpu *vcpu); 619 void (*queue_io_int)(struct kvm_vcpu *vcpu, 620 struct kvm_mips_interrupt *irq); 621 void (*dequeue_io_int)(struct kvm_vcpu *vcpu, 622 struct kvm_mips_interrupt *irq); 623 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority, 624 uint32_t cause); 625 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority, 626 uint32_t cause); 627 int (*get_one_reg)(struct kvm_vcpu *vcpu, 628 const struct kvm_one_reg *reg, s64 *v); 629 int (*set_one_reg)(struct kvm_vcpu *vcpu, 630 const struct kvm_one_reg *reg, s64 v); 631 int (*vcpu_get_regs)(struct kvm_vcpu *vcpu); 632 int (*vcpu_set_regs)(struct kvm_vcpu *vcpu); 633 }; 634 extern struct kvm_mips_callbacks *kvm_mips_callbacks; 635 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks); 636 637 /* Debug: dump vcpu state */ 638 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu); 639 640 /* Trampoline ASM routine to start running in "Guest" context */ 641 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu); 642 643 /* FPU/MSA context management */ 644 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu); 645 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu); 646 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu); 647 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu); 648 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu); 649 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu); 650 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu); 651 void kvm_own_fpu(struct kvm_vcpu *vcpu); 652 void kvm_own_msa(struct kvm_vcpu *vcpu); 653 void kvm_drop_fpu(struct kvm_vcpu *vcpu); 654 void kvm_lose_fpu(struct kvm_vcpu *vcpu); 655 656 /* TLB handling */ 657 uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu); 658 659 uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu); 660 661 uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu); 662 663 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr, 664 struct kvm_vcpu *vcpu); 665 666 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr, 667 struct kvm_vcpu *vcpu); 668 669 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu, 670 struct kvm_mips_tlb *tlb, 671 unsigned long *hpa0, 672 unsigned long *hpa1); 673 674 extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause, 675 uint32_t *opc, 676 struct kvm_run *run, 677 struct kvm_vcpu *vcpu); 678 679 extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause, 680 uint32_t *opc, 681 struct kvm_run *run, 682 struct kvm_vcpu *vcpu); 683 684 extern void kvm_mips_dump_host_tlbs(void); 685 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu); 686 extern void kvm_mips_flush_host_tlb(int skip_kseg0); 687 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi); 688 extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index); 689 690 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, 691 unsigned long entryhi); 692 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr); 693 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu, 694 unsigned long gva); 695 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu, 696 struct kvm_vcpu *vcpu); 697 extern void kvm_local_flush_tlb_all(void); 698 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu); 699 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 700 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu); 701 702 /* Emulation */ 703 uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu); 704 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause); 705 706 extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause, 707 uint32_t *opc, 708 struct kvm_run *run, 709 struct kvm_vcpu *vcpu); 710 711 extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause, 712 uint32_t *opc, 713 struct kvm_run *run, 714 struct kvm_vcpu *vcpu); 715 716 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause, 717 uint32_t *opc, 718 struct kvm_run *run, 719 struct kvm_vcpu *vcpu); 720 721 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause, 722 uint32_t *opc, 723 struct kvm_run *run, 724 struct kvm_vcpu *vcpu); 725 726 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause, 727 uint32_t *opc, 728 struct kvm_run *run, 729 struct kvm_vcpu *vcpu); 730 731 extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause, 732 uint32_t *opc, 733 struct kvm_run *run, 734 struct kvm_vcpu *vcpu); 735 736 extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause, 737 uint32_t *opc, 738 struct kvm_run *run, 739 struct kvm_vcpu *vcpu); 740 741 extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause, 742 uint32_t *opc, 743 struct kvm_run *run, 744 struct kvm_vcpu *vcpu); 745 746 extern enum emulation_result kvm_mips_handle_ri(unsigned long cause, 747 uint32_t *opc, 748 struct kvm_run *run, 749 struct kvm_vcpu *vcpu); 750 751 extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause, 752 uint32_t *opc, 753 struct kvm_run *run, 754 struct kvm_vcpu *vcpu); 755 756 extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause, 757 uint32_t *opc, 758 struct kvm_run *run, 759 struct kvm_vcpu *vcpu); 760 761 extern enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause, 762 uint32_t *opc, 763 struct kvm_run *run, 764 struct kvm_vcpu *vcpu); 765 766 extern enum emulation_result kvm_mips_emulate_msafpe_exc(unsigned long cause, 767 uint32_t *opc, 768 struct kvm_run *run, 769 struct kvm_vcpu *vcpu); 770 771 extern enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause, 772 uint32_t *opc, 773 struct kvm_run *run, 774 struct kvm_vcpu *vcpu); 775 776 extern enum emulation_result kvm_mips_emulate_msadis_exc(unsigned long cause, 777 uint32_t *opc, 778 struct kvm_run *run, 779 struct kvm_vcpu *vcpu); 780 781 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu, 782 struct kvm_run *run); 783 784 uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu); 785 void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count); 786 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare); 787 void kvm_mips_init_count(struct kvm_vcpu *vcpu); 788 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl); 789 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume); 790 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz); 791 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu); 792 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu); 793 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu); 794 795 enum emulation_result kvm_mips_check_privilege(unsigned long cause, 796 uint32_t *opc, 797 struct kvm_run *run, 798 struct kvm_vcpu *vcpu); 799 800 enum emulation_result kvm_mips_emulate_cache(uint32_t inst, 801 uint32_t *opc, 802 uint32_t cause, 803 struct kvm_run *run, 804 struct kvm_vcpu *vcpu); 805 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst, 806 uint32_t *opc, 807 uint32_t cause, 808 struct kvm_run *run, 809 struct kvm_vcpu *vcpu); 810 enum emulation_result kvm_mips_emulate_store(uint32_t inst, 811 uint32_t cause, 812 struct kvm_run *run, 813 struct kvm_vcpu *vcpu); 814 enum emulation_result kvm_mips_emulate_load(uint32_t inst, 815 uint32_t cause, 816 struct kvm_run *run, 817 struct kvm_vcpu *vcpu); 818 819 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu); 820 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu); 821 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu); 822 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu); 823 824 /* Dynamic binary translation */ 825 extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc, 826 struct kvm_vcpu *vcpu); 827 extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc, 828 struct kvm_vcpu *vcpu); 829 extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc, 830 struct kvm_vcpu *vcpu); 831 extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc, 832 struct kvm_vcpu *vcpu); 833 834 /* Misc */ 835 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu); 836 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm); 837 838 static inline void kvm_arch_hardware_disable(void) {} 839 static inline void kvm_arch_hardware_unsetup(void) {} 840 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 841 static inline void kvm_arch_free_memslot(struct kvm *kvm, 842 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {} 843 static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {} 844 static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {} 845 static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 846 struct kvm_memory_slot *slot) {} 847 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} 848 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 849 850 #endif /* __MIPS_KVM_HOST_H__ */ 851