1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 7 * Authors: Sanjay Lal <sanjayl@kymasys.com> 8 */ 9 10 #ifndef __MIPS_KVM_HOST_H__ 11 #define __MIPS_KVM_HOST_H__ 12 13 #include <linux/mutex.h> 14 #include <linux/hrtimer.h> 15 #include <linux/interrupt.h> 16 #include <linux/types.h> 17 #include <linux/kvm.h> 18 #include <linux/kvm_types.h> 19 #include <linux/threads.h> 20 #include <linux/spinlock.h> 21 22 /* MIPS KVM register ids */ 23 #define MIPS_CP0_32(_R, _S) \ 24 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S))) 25 26 #define MIPS_CP0_64(_R, _S) \ 27 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) 28 29 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) 30 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0) 31 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0) 32 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) 33 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) 34 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) 35 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) 36 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) 37 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) 38 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) 39 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) 40 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) 41 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) 42 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) 43 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) 44 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) 45 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) 46 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) 47 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) 48 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) 49 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) 50 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) 51 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) 52 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) 53 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7) 54 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) 55 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) 56 57 58 #define KVM_MAX_VCPUS 1 59 #define KVM_USER_MEM_SLOTS 8 60 /* memory slots that does not exposed to userspace */ 61 #define KVM_PRIVATE_MEM_SLOTS 0 62 63 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 64 #define KVM_HALT_POLL_NS_DEFAULT 500000 65 66 67 68 /* Special address that contains the comm page, used for reducing # of traps */ 69 #define KVM_GUEST_COMMPAGE_ADDR 0x0 70 71 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \ 72 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0)) 73 74 #define KVM_GUEST_KUSEG 0x00000000UL 75 #define KVM_GUEST_KSEG0 0x40000000UL 76 #define KVM_GUEST_KSEG23 0x60000000UL 77 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000) 78 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) 79 80 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) 81 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1) 82 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23) 83 84 /* 85 * Map an address to a certain kernel segment 86 */ 87 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) 88 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1) 89 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23) 90 91 #define KVM_INVALID_PAGE 0xdeadbeef 92 #define KVM_INVALID_INST 0xdeadbeef 93 #define KVM_INVALID_ADDR 0xdeadbeef 94 95 extern atomic_t kvm_mips_instance; 96 extern kvm_pfn_t (*kvm_mips_gfn_to_pfn)(struct kvm *kvm, gfn_t gfn); 97 extern void (*kvm_mips_release_pfn_clean)(kvm_pfn_t pfn); 98 extern bool (*kvm_mips_is_error_pfn)(kvm_pfn_t pfn); 99 100 struct kvm_vm_stat { 101 u32 remote_tlb_flush; 102 }; 103 104 struct kvm_vcpu_stat { 105 u32 wait_exits; 106 u32 cache_exits; 107 u32 signal_exits; 108 u32 int_exits; 109 u32 cop_unusable_exits; 110 u32 tlbmod_exits; 111 u32 tlbmiss_ld_exits; 112 u32 tlbmiss_st_exits; 113 u32 addrerr_st_exits; 114 u32 addrerr_ld_exits; 115 u32 syscall_exits; 116 u32 resvd_inst_exits; 117 u32 break_inst_exits; 118 u32 trap_inst_exits; 119 u32 msa_fpe_exits; 120 u32 fpe_exits; 121 u32 msa_disabled_exits; 122 u32 flush_dcache_exits; 123 u32 halt_successful_poll; 124 u32 halt_attempted_poll; 125 u32 halt_wakeup; 126 }; 127 128 enum kvm_mips_exit_types { 129 WAIT_EXITS, 130 CACHE_EXITS, 131 SIGNAL_EXITS, 132 INT_EXITS, 133 COP_UNUSABLE_EXITS, 134 TLBMOD_EXITS, 135 TLBMISS_LD_EXITS, 136 TLBMISS_ST_EXITS, 137 ADDRERR_ST_EXITS, 138 ADDRERR_LD_EXITS, 139 SYSCALL_EXITS, 140 RESVD_INST_EXITS, 141 BREAK_INST_EXITS, 142 TRAP_INST_EXITS, 143 MSA_FPE_EXITS, 144 FPE_EXITS, 145 MSA_DISABLED_EXITS, 146 FLUSH_DCACHE_EXITS, 147 MAX_KVM_MIPS_EXIT_TYPES 148 }; 149 150 struct kvm_arch_memory_slot { 151 }; 152 153 struct kvm_arch { 154 /* Guest GVA->HPA page table */ 155 unsigned long *guest_pmap; 156 unsigned long guest_pmap_npages; 157 158 /* Wired host TLB used for the commpage */ 159 int commpage_tlb; 160 }; 161 162 #define N_MIPS_COPROC_REGS 32 163 #define N_MIPS_COPROC_SEL 8 164 165 struct mips_coproc { 166 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; 167 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS 168 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; 169 #endif 170 }; 171 172 /* 173 * Coprocessor 0 register names 174 */ 175 #define MIPS_CP0_TLB_INDEX 0 176 #define MIPS_CP0_TLB_RANDOM 1 177 #define MIPS_CP0_TLB_LOW 2 178 #define MIPS_CP0_TLB_LO0 2 179 #define MIPS_CP0_TLB_LO1 3 180 #define MIPS_CP0_TLB_CONTEXT 4 181 #define MIPS_CP0_TLB_PG_MASK 5 182 #define MIPS_CP0_TLB_WIRED 6 183 #define MIPS_CP0_HWRENA 7 184 #define MIPS_CP0_BAD_VADDR 8 185 #define MIPS_CP0_COUNT 9 186 #define MIPS_CP0_TLB_HI 10 187 #define MIPS_CP0_COMPARE 11 188 #define MIPS_CP0_STATUS 12 189 #define MIPS_CP0_CAUSE 13 190 #define MIPS_CP0_EXC_PC 14 191 #define MIPS_CP0_PRID 15 192 #define MIPS_CP0_CONFIG 16 193 #define MIPS_CP0_LLADDR 17 194 #define MIPS_CP0_WATCH_LO 18 195 #define MIPS_CP0_WATCH_HI 19 196 #define MIPS_CP0_TLB_XCONTEXT 20 197 #define MIPS_CP0_ECC 26 198 #define MIPS_CP0_CACHE_ERR 27 199 #define MIPS_CP0_TAG_LO 28 200 #define MIPS_CP0_TAG_HI 29 201 #define MIPS_CP0_ERROR_PC 30 202 #define MIPS_CP0_DEBUG 23 203 #define MIPS_CP0_DEPC 24 204 #define MIPS_CP0_PERFCNT 25 205 #define MIPS_CP0_ERRCTL 26 206 #define MIPS_CP0_DATA_LO 28 207 #define MIPS_CP0_DATA_HI 29 208 #define MIPS_CP0_DESAVE 31 209 210 #define MIPS_CP0_CONFIG_SEL 0 211 #define MIPS_CP0_CONFIG1_SEL 1 212 #define MIPS_CP0_CONFIG2_SEL 2 213 #define MIPS_CP0_CONFIG3_SEL 3 214 #define MIPS_CP0_CONFIG4_SEL 4 215 #define MIPS_CP0_CONFIG5_SEL 5 216 217 /* Config0 register bits */ 218 #define CP0C0_M 31 219 #define CP0C0_K23 28 220 #define CP0C0_KU 25 221 #define CP0C0_MDU 20 222 #define CP0C0_MM 17 223 #define CP0C0_BM 16 224 #define CP0C0_BE 15 225 #define CP0C0_AT 13 226 #define CP0C0_AR 10 227 #define CP0C0_MT 7 228 #define CP0C0_VI 3 229 #define CP0C0_K0 0 230 231 /* Config1 register bits */ 232 #define CP0C1_M 31 233 #define CP0C1_MMU 25 234 #define CP0C1_IS 22 235 #define CP0C1_IL 19 236 #define CP0C1_IA 16 237 #define CP0C1_DS 13 238 #define CP0C1_DL 10 239 #define CP0C1_DA 7 240 #define CP0C1_C2 6 241 #define CP0C1_MD 5 242 #define CP0C1_PC 4 243 #define CP0C1_WR 3 244 #define CP0C1_CA 2 245 #define CP0C1_EP 1 246 #define CP0C1_FP 0 247 248 /* Config2 Register bits */ 249 #define CP0C2_M 31 250 #define CP0C2_TU 28 251 #define CP0C2_TS 24 252 #define CP0C2_TL 20 253 #define CP0C2_TA 16 254 #define CP0C2_SU 12 255 #define CP0C2_SS 8 256 #define CP0C2_SL 4 257 #define CP0C2_SA 0 258 259 /* Config3 Register bits */ 260 #define CP0C3_M 31 261 #define CP0C3_ISA_ON_EXC 16 262 #define CP0C3_ULRI 13 263 #define CP0C3_DSPP 10 264 #define CP0C3_LPA 7 265 #define CP0C3_VEIC 6 266 #define CP0C3_VInt 5 267 #define CP0C3_SP 4 268 #define CP0C3_MT 2 269 #define CP0C3_SM 1 270 #define CP0C3_TL 0 271 272 /* MMU types, the first four entries have the same layout as the 273 CP0C0_MT field. */ 274 enum mips_mmu_types { 275 MMU_TYPE_NONE, 276 MMU_TYPE_R4000, 277 MMU_TYPE_RESERVED, 278 MMU_TYPE_FMT, 279 MMU_TYPE_R3000, 280 MMU_TYPE_R6000, 281 MMU_TYPE_R8000 282 }; 283 284 /* Resume Flags */ 285 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */ 286 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */ 287 288 #define RESUME_GUEST 0 289 #define RESUME_GUEST_DR RESUME_FLAG_DR 290 #define RESUME_HOST RESUME_FLAG_HOST 291 292 enum emulation_result { 293 EMULATE_DONE, /* no further processing */ 294 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */ 295 EMULATE_FAIL, /* can't emulate this instruction */ 296 EMULATE_WAIT, /* WAIT instruction */ 297 EMULATE_PRIV_FAIL, 298 }; 299 300 #define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */ 301 #define MIPS3_PG_V 0x00000002 /* Valid */ 302 #define MIPS3_PG_NV 0x00000000 303 #define MIPS3_PG_D 0x00000004 /* Dirty */ 304 305 #define mips3_paddr_to_tlbpfn(x) \ 306 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME) 307 #define mips3_tlbpfn_to_paddr(x) \ 308 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT) 309 310 #define MIPS3_PG_SHIFT 6 311 #define MIPS3_PG_FRAME 0x3fffffc0 312 313 #define VPN2_MASK 0xffffe000 314 #define KVM_ENTRYHI_ASID MIPS_ENTRYHI_ASID 315 #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \ 316 ((x).tlb_lo1 & MIPS3_PG_G)) 317 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK) 318 #define TLB_ASID(x) ((x).tlb_hi & KVM_ENTRYHI_ASID) 319 #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \ 320 ? ((x).tlb_lo1 & MIPS3_PG_V) \ 321 : ((x).tlb_lo0 & MIPS3_PG_V)) 322 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \ 323 ((y) & VPN2_MASK & ~(x).tlb_mask)) 324 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \ 325 TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID)) 326 327 struct kvm_mips_tlb { 328 long tlb_mask; 329 long tlb_hi; 330 long tlb_lo0; 331 long tlb_lo1; 332 }; 333 334 #define KVM_MIPS_FPU_FPU 0x1 335 #define KVM_MIPS_FPU_MSA 0x2 336 337 #define KVM_MIPS_GUEST_TLB_SIZE 64 338 struct kvm_vcpu_arch { 339 void *host_ebase, *guest_ebase; 340 unsigned long host_stack; 341 unsigned long host_gp; 342 343 /* Host CP0 registers used when handling exits from guest */ 344 unsigned long host_cp0_badvaddr; 345 unsigned long host_cp0_cause; 346 unsigned long host_cp0_epc; 347 unsigned long host_cp0_entryhi; 348 uint32_t guest_inst; 349 350 /* GPRS */ 351 unsigned long gprs[32]; 352 unsigned long hi; 353 unsigned long lo; 354 unsigned long pc; 355 356 /* FPU State */ 357 struct mips_fpu_struct fpu; 358 /* Which FPU state is loaded (KVM_MIPS_FPU_*) */ 359 unsigned int fpu_inuse; 360 361 /* COP0 State */ 362 struct mips_coproc *cop0; 363 364 /* Host KSEG0 address of the EI/DI offset */ 365 void *kseg0_commpage; 366 367 u32 io_gpr; /* GPR used as IO source/target */ 368 369 struct hrtimer comparecount_timer; 370 /* Count timer control KVM register */ 371 uint32_t count_ctl; 372 /* Count bias from the raw time */ 373 uint32_t count_bias; 374 /* Frequency of timer in Hz */ 375 uint32_t count_hz; 376 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */ 377 s64 count_dyn_bias; 378 /* Resume time */ 379 ktime_t count_resume; 380 /* Period of timer tick in ns */ 381 u64 count_period; 382 383 /* Bitmask of exceptions that are pending */ 384 unsigned long pending_exceptions; 385 386 /* Bitmask of pending exceptions to be cleared */ 387 unsigned long pending_exceptions_clr; 388 389 unsigned long pending_load_cause; 390 391 /* Save/Restore the entryhi register when are are preempted/scheduled back in */ 392 unsigned long preempt_entryhi; 393 394 /* S/W Based TLB for guest */ 395 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE]; 396 397 /* Cached guest kernel/user ASIDs */ 398 uint32_t guest_user_asid[NR_CPUS]; 399 uint32_t guest_kernel_asid[NR_CPUS]; 400 struct mm_struct guest_kernel_mm, guest_user_mm; 401 402 int last_sched_cpu; 403 404 /* WAIT executed */ 405 int wait; 406 407 u8 fpu_enabled; 408 u8 msa_enabled; 409 }; 410 411 412 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0]) 413 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val) 414 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0]) 415 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0]) 416 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0]) 417 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val)) 418 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2]) 419 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val)) 420 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0]) 421 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val)) 422 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0]) 423 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val)) 424 #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0]) 425 #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val)) 426 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0]) 427 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val)) 428 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0]) 429 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val)) 430 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0]) 431 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val)) 432 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0]) 433 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val)) 434 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0]) 435 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val)) 436 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1]) 437 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val)) 438 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0]) 439 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val)) 440 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0]) 441 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val)) 442 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0]) 443 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val)) 444 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1]) 445 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val)) 446 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0]) 447 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1]) 448 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2]) 449 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3]) 450 #define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4]) 451 #define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5]) 452 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7]) 453 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val)) 454 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val)) 455 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val)) 456 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val)) 457 #define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val)) 458 #define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val)) 459 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val)) 460 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0]) 461 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val)) 462 463 /* 464 * Some of the guest registers may be modified asynchronously (e.g. from a 465 * hrtimer callback in hard irq context) and therefore need stronger atomicity 466 * guarantees than other registers. 467 */ 468 469 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg, 470 unsigned long val) 471 { 472 unsigned long temp; 473 do { 474 __asm__ __volatile__( 475 " .set mips3 \n" 476 " " __LL "%0, %1 \n" 477 " or %0, %2 \n" 478 " " __SC "%0, %1 \n" 479 " .set mips0 \n" 480 : "=&r" (temp), "+m" (*reg) 481 : "r" (val)); 482 } while (unlikely(!temp)); 483 } 484 485 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg, 486 unsigned long val) 487 { 488 unsigned long temp; 489 do { 490 __asm__ __volatile__( 491 " .set mips3 \n" 492 " " __LL "%0, %1 \n" 493 " and %0, %2 \n" 494 " " __SC "%0, %1 \n" 495 " .set mips0 \n" 496 : "=&r" (temp), "+m" (*reg) 497 : "r" (~val)); 498 } while (unlikely(!temp)); 499 } 500 501 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg, 502 unsigned long change, 503 unsigned long val) 504 { 505 unsigned long temp; 506 do { 507 __asm__ __volatile__( 508 " .set mips3 \n" 509 " " __LL "%0, %1 \n" 510 " and %0, %2 \n" 511 " or %0, %3 \n" 512 " " __SC "%0, %1 \n" 513 " .set mips0 \n" 514 : "=&r" (temp), "+m" (*reg) 515 : "r" (~change), "r" (val & change)); 516 } while (unlikely(!temp)); 517 } 518 519 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val)) 520 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val)) 521 522 /* Cause can be modified asynchronously from hardirq hrtimer callback */ 523 #define kvm_set_c0_guest_cause(cop0, val) \ 524 _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val) 525 #define kvm_clear_c0_guest_cause(cop0, val) \ 526 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val) 527 #define kvm_change_c0_guest_cause(cop0, change, val) \ 528 _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \ 529 change, val) 530 531 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val)) 532 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val)) 533 #define kvm_change_c0_guest_ebase(cop0, change, val) \ 534 { \ 535 kvm_clear_c0_guest_ebase(cop0, change); \ 536 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \ 537 } 538 539 /* Helpers */ 540 541 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu) 542 { 543 return (!__builtin_constant_p(cpu_has_fpu) || cpu_has_fpu) && 544 vcpu->fpu_enabled; 545 } 546 547 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu) 548 { 549 return kvm_mips_guest_can_have_fpu(vcpu) && 550 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP; 551 } 552 553 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu) 554 { 555 return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) && 556 vcpu->msa_enabled; 557 } 558 559 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu) 560 { 561 return kvm_mips_guest_can_have_msa(vcpu) && 562 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA; 563 } 564 565 struct kvm_mips_callbacks { 566 int (*handle_cop_unusable)(struct kvm_vcpu *vcpu); 567 int (*handle_tlb_mod)(struct kvm_vcpu *vcpu); 568 int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu); 569 int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu); 570 int (*handle_addr_err_st)(struct kvm_vcpu *vcpu); 571 int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu); 572 int (*handle_syscall)(struct kvm_vcpu *vcpu); 573 int (*handle_res_inst)(struct kvm_vcpu *vcpu); 574 int (*handle_break)(struct kvm_vcpu *vcpu); 575 int (*handle_trap)(struct kvm_vcpu *vcpu); 576 int (*handle_msa_fpe)(struct kvm_vcpu *vcpu); 577 int (*handle_fpe)(struct kvm_vcpu *vcpu); 578 int (*handle_msa_disabled)(struct kvm_vcpu *vcpu); 579 int (*vm_init)(struct kvm *kvm); 580 int (*vcpu_init)(struct kvm_vcpu *vcpu); 581 int (*vcpu_setup)(struct kvm_vcpu *vcpu); 582 gpa_t (*gva_to_gpa)(gva_t gva); 583 void (*queue_timer_int)(struct kvm_vcpu *vcpu); 584 void (*dequeue_timer_int)(struct kvm_vcpu *vcpu); 585 void (*queue_io_int)(struct kvm_vcpu *vcpu, 586 struct kvm_mips_interrupt *irq); 587 void (*dequeue_io_int)(struct kvm_vcpu *vcpu, 588 struct kvm_mips_interrupt *irq); 589 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority, 590 uint32_t cause); 591 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority, 592 uint32_t cause); 593 int (*get_one_reg)(struct kvm_vcpu *vcpu, 594 const struct kvm_one_reg *reg, s64 *v); 595 int (*set_one_reg)(struct kvm_vcpu *vcpu, 596 const struct kvm_one_reg *reg, s64 v); 597 int (*vcpu_get_regs)(struct kvm_vcpu *vcpu); 598 int (*vcpu_set_regs)(struct kvm_vcpu *vcpu); 599 }; 600 extern struct kvm_mips_callbacks *kvm_mips_callbacks; 601 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks); 602 603 /* Debug: dump vcpu state */ 604 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu); 605 606 /* Trampoline ASM routine to start running in "Guest" context */ 607 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu); 608 609 /* FPU/MSA context management */ 610 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu); 611 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu); 612 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu); 613 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu); 614 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu); 615 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu); 616 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu); 617 void kvm_own_fpu(struct kvm_vcpu *vcpu); 618 void kvm_own_msa(struct kvm_vcpu *vcpu); 619 void kvm_drop_fpu(struct kvm_vcpu *vcpu); 620 void kvm_lose_fpu(struct kvm_vcpu *vcpu); 621 622 /* TLB handling */ 623 uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu); 624 625 uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu); 626 627 uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu); 628 629 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr, 630 struct kvm_vcpu *vcpu); 631 632 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr, 633 struct kvm_vcpu *vcpu); 634 635 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu, 636 struct kvm_mips_tlb *tlb, 637 unsigned long *hpa0, 638 unsigned long *hpa1); 639 640 extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause, 641 uint32_t *opc, 642 struct kvm_run *run, 643 struct kvm_vcpu *vcpu); 644 645 extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause, 646 uint32_t *opc, 647 struct kvm_run *run, 648 struct kvm_vcpu *vcpu); 649 650 extern void kvm_mips_dump_host_tlbs(void); 651 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu); 652 extern void kvm_mips_flush_host_tlb(int skip_kseg0); 653 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi); 654 655 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, 656 unsigned long entryhi); 657 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr); 658 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu, 659 unsigned long gva); 660 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu, 661 struct kvm_vcpu *vcpu); 662 extern void kvm_local_flush_tlb_all(void); 663 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu); 664 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 665 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu); 666 667 /* Emulation */ 668 uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu); 669 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause); 670 671 extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause, 672 uint32_t *opc, 673 struct kvm_run *run, 674 struct kvm_vcpu *vcpu); 675 676 extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause, 677 uint32_t *opc, 678 struct kvm_run *run, 679 struct kvm_vcpu *vcpu); 680 681 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause, 682 uint32_t *opc, 683 struct kvm_run *run, 684 struct kvm_vcpu *vcpu); 685 686 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause, 687 uint32_t *opc, 688 struct kvm_run *run, 689 struct kvm_vcpu *vcpu); 690 691 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause, 692 uint32_t *opc, 693 struct kvm_run *run, 694 struct kvm_vcpu *vcpu); 695 696 extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause, 697 uint32_t *opc, 698 struct kvm_run *run, 699 struct kvm_vcpu *vcpu); 700 701 extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause, 702 uint32_t *opc, 703 struct kvm_run *run, 704 struct kvm_vcpu *vcpu); 705 706 extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause, 707 uint32_t *opc, 708 struct kvm_run *run, 709 struct kvm_vcpu *vcpu); 710 711 extern enum emulation_result kvm_mips_handle_ri(unsigned long cause, 712 uint32_t *opc, 713 struct kvm_run *run, 714 struct kvm_vcpu *vcpu); 715 716 extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause, 717 uint32_t *opc, 718 struct kvm_run *run, 719 struct kvm_vcpu *vcpu); 720 721 extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause, 722 uint32_t *opc, 723 struct kvm_run *run, 724 struct kvm_vcpu *vcpu); 725 726 extern enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause, 727 uint32_t *opc, 728 struct kvm_run *run, 729 struct kvm_vcpu *vcpu); 730 731 extern enum emulation_result kvm_mips_emulate_msafpe_exc(unsigned long cause, 732 uint32_t *opc, 733 struct kvm_run *run, 734 struct kvm_vcpu *vcpu); 735 736 extern enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause, 737 uint32_t *opc, 738 struct kvm_run *run, 739 struct kvm_vcpu *vcpu); 740 741 extern enum emulation_result kvm_mips_emulate_msadis_exc(unsigned long cause, 742 uint32_t *opc, 743 struct kvm_run *run, 744 struct kvm_vcpu *vcpu); 745 746 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu, 747 struct kvm_run *run); 748 749 uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu); 750 void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count); 751 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare); 752 void kvm_mips_init_count(struct kvm_vcpu *vcpu); 753 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl); 754 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume); 755 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz); 756 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu); 757 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu); 758 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu); 759 760 enum emulation_result kvm_mips_check_privilege(unsigned long cause, 761 uint32_t *opc, 762 struct kvm_run *run, 763 struct kvm_vcpu *vcpu); 764 765 enum emulation_result kvm_mips_emulate_cache(uint32_t inst, 766 uint32_t *opc, 767 uint32_t cause, 768 struct kvm_run *run, 769 struct kvm_vcpu *vcpu); 770 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst, 771 uint32_t *opc, 772 uint32_t cause, 773 struct kvm_run *run, 774 struct kvm_vcpu *vcpu); 775 enum emulation_result kvm_mips_emulate_store(uint32_t inst, 776 uint32_t cause, 777 struct kvm_run *run, 778 struct kvm_vcpu *vcpu); 779 enum emulation_result kvm_mips_emulate_load(uint32_t inst, 780 uint32_t cause, 781 struct kvm_run *run, 782 struct kvm_vcpu *vcpu); 783 784 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu); 785 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu); 786 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu); 787 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu); 788 789 /* Dynamic binary translation */ 790 extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc, 791 struct kvm_vcpu *vcpu); 792 extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc, 793 struct kvm_vcpu *vcpu); 794 extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc, 795 struct kvm_vcpu *vcpu); 796 extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc, 797 struct kvm_vcpu *vcpu); 798 799 /* Misc */ 800 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu); 801 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm); 802 803 static inline void kvm_arch_hardware_disable(void) {} 804 static inline void kvm_arch_hardware_unsetup(void) {} 805 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 806 static inline void kvm_arch_free_memslot(struct kvm *kvm, 807 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {} 808 static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {} 809 static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {} 810 static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 811 struct kvm_memory_slot *slot) {} 812 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} 813 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 814 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {} 815 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {} 816 817 #endif /* __MIPS_KVM_HOST_H__ */ 818