1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995 Waldorf GmbH 7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 10 * Author: Maciej W. Rozycki <macro@mips.com> 11 */ 12 #ifndef _ASM_IO_H 13 #define _ASM_IO_H 14 15 #define ARCH_HAS_IOREMAP_WC 16 17 #include <linux/compiler.h> 18 #include <linux/kernel.h> 19 #include <linux/types.h> 20 #include <linux/irqflags.h> 21 22 #include <asm/addrspace.h> 23 #include <asm/barrier.h> 24 #include <asm/bug.h> 25 #include <asm/byteorder.h> 26 #include <asm/cpu.h> 27 #include <asm/cpu-features.h> 28 #include <asm-generic/iomap.h> 29 #include <asm/page.h> 30 #include <asm/pgtable-bits.h> 31 #include <asm/processor.h> 32 #include <asm/string.h> 33 34 #include <ioremap.h> 35 #include <mangle-port.h> 36 37 /* 38 * Raw operations are never swapped in software. OTOH values that raw 39 * operations are working on may or may not have been swapped by the bus 40 * hardware. An example use would be for flash memory that's used for 41 * execute in place. 42 */ 43 # define __raw_ioswabb(a, x) (x) 44 # define __raw_ioswabw(a, x) (x) 45 # define __raw_ioswabl(a, x) (x) 46 # define __raw_ioswabq(a, x) (x) 47 # define ____raw_ioswabq(a, x) (x) 48 49 # define __relaxed_ioswabb ioswabb 50 # define __relaxed_ioswabw ioswabw 51 # define __relaxed_ioswabl ioswabl 52 # define __relaxed_ioswabq ioswabq 53 54 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ 55 56 #define IO_SPACE_LIMIT 0xffff 57 58 /* 59 * On MIPS I/O ports are memory mapped, so we access them using normal 60 * load/store instructions. mips_io_port_base is the virtual address to 61 * which all ports are being mapped. For sake of efficiency some code 62 * assumes that this is an address that can be loaded with a single lui 63 * instruction, so the lower 16 bits must be zero. Should be true on 64 * on any sane architecture; generic code does not use this assumption. 65 */ 66 extern unsigned long mips_io_port_base; 67 68 static inline void set_io_port_base(unsigned long base) 69 { 70 mips_io_port_base = base; 71 } 72 73 /* 74 * Provide the necessary definitions for generic iomap. We make use of 75 * mips_io_port_base for iomap(), but we don't reserve any low addresses for 76 * use with I/O ports. 77 */ 78 79 #define HAVE_ARCH_PIO_SIZE 80 #define PIO_OFFSET mips_io_port_base 81 #define PIO_MASK IO_SPACE_LIMIT 82 #define PIO_RESERVED 0x0UL 83 84 /* 85 * Enforce in-order execution of data I/O. In the MIPS architecture 86 * these are equivalent to corresponding platform-specific memory 87 * barriers defined in <asm/barrier.h>. API pinched from PowerPC, 88 * with sync additionally defined. 89 */ 90 #define iobarrier_rw() mb() 91 #define iobarrier_r() rmb() 92 #define iobarrier_w() wmb() 93 #define iobarrier_sync() iob() 94 95 /* 96 * virt_to_phys - map virtual addresses to physical 97 * @address: address to remap 98 * 99 * The returned physical address is the physical (CPU) mapping for 100 * the memory address given. It is only valid to use this function on 101 * addresses directly mapped or allocated via kmalloc. 102 * 103 * This function does not give bus mappings for DMA transfers. In 104 * almost all conceivable cases a device driver should not be using 105 * this function 106 */ 107 static inline unsigned long virt_to_phys(volatile const void *address) 108 { 109 return __pa(address); 110 } 111 112 /* 113 * phys_to_virt - map physical address to virtual 114 * @address: address to remap 115 * 116 * The returned virtual address is a current CPU mapping for 117 * the memory address given. It is only valid to use this function on 118 * addresses that have a kernel mapping 119 * 120 * This function does not handle bus mappings for DMA transfers. In 121 * almost all conceivable cases a device driver should not be using 122 * this function 123 */ 124 static inline void * phys_to_virt(unsigned long address) 125 { 126 return (void *)(address + PAGE_OFFSET - PHYS_OFFSET); 127 } 128 129 /* 130 * ISA I/O bus memory addresses are 1:1 with the physical address. 131 */ 132 static inline unsigned long isa_virt_to_bus(volatile void *address) 133 { 134 return virt_to_phys(address); 135 } 136 137 static inline void *isa_bus_to_virt(unsigned long address) 138 { 139 return phys_to_virt(address); 140 } 141 142 /* 143 * However PCI ones are not necessarily 1:1 and therefore these interfaces 144 * are forbidden in portable PCI drivers. 145 * 146 * Allow them for x86 for legacy drivers, though. 147 */ 148 #define virt_to_bus virt_to_phys 149 #define bus_to_virt phys_to_virt 150 151 /* 152 * Change "struct page" to physical address. 153 */ 154 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) 155 156 extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags); 157 extern void __iounmap(const volatile void __iomem *addr); 158 159 static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size, 160 unsigned long flags) 161 { 162 void __iomem *addr = plat_ioremap(offset, size, flags); 163 164 if (addr) 165 return addr; 166 167 #define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL)) 168 169 if (cpu_has_64bit_addresses) { 170 u64 base = UNCAC_BASE; 171 172 /* 173 * R10000 supports a 2 bit uncached attribute therefore 174 * UNCAC_BASE may not equal IO_BASE. 175 */ 176 if (flags == _CACHE_UNCACHED) 177 base = (u64) IO_BASE; 178 return (void __iomem *) (unsigned long) (base + offset); 179 } else if (__builtin_constant_p(offset) && 180 __builtin_constant_p(size) && __builtin_constant_p(flags)) { 181 phys_addr_t phys_addr, last_addr; 182 183 phys_addr = fixup_bigphys_addr(offset, size); 184 185 /* Don't allow wraparound or zero size. */ 186 last_addr = phys_addr + size - 1; 187 if (!size || last_addr < phys_addr) 188 return NULL; 189 190 /* 191 * Map uncached objects in the low 512MB of address 192 * space using KSEG1. 193 */ 194 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) && 195 flags == _CACHE_UNCACHED) 196 return (void __iomem *) 197 (unsigned long)CKSEG1ADDR(phys_addr); 198 } 199 200 return __ioremap(offset, size, flags); 201 202 #undef __IS_LOW512 203 } 204 205 /* 206 * ioremap_prot - map bus memory into CPU space 207 * @offset: bus address of the memory 208 * @size: size of the resource to map 209 210 * ioremap_prot gives the caller control over cache coherency attributes (CCA) 211 */ 212 static inline void __iomem *ioremap_prot(phys_addr_t offset, 213 unsigned long size, unsigned long prot_val) { 214 return __ioremap_mode(offset, size, prot_val & _CACHE_MASK); 215 } 216 217 /* 218 * ioremap - map bus memory into CPU space 219 * @offset: bus address of the memory 220 * @size: size of the resource to map 221 * 222 * ioremap performs a platform specific sequence of operations to 223 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 224 * writew/writel functions and the other mmio helpers. The returned 225 * address is not guaranteed to be usable directly as a virtual 226 * address. 227 */ 228 #define ioremap(offset, size) \ 229 __ioremap_mode((offset), (size), _CACHE_UNCACHED) 230 231 /* 232 * ioremap_nocache - map bus memory into CPU space 233 * @offset: bus address of the memory 234 * @size: size of the resource to map 235 * 236 * ioremap_nocache performs a platform specific sequence of operations to 237 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 238 * writew/writel functions and the other mmio helpers. The returned 239 * address is not guaranteed to be usable directly as a virtual 240 * address. 241 * 242 * This version of ioremap ensures that the memory is marked uncachable 243 * on the CPU as well as honouring existing caching rules from things like 244 * the PCI bus. Note that there are other caches and buffers on many 245 * busses. In particular driver authors should read up on PCI writes 246 * 247 * It's useful if some control registers are in such an area and 248 * write combining or read caching is not desirable: 249 */ 250 #define ioremap_nocache(offset, size) \ 251 __ioremap_mode((offset), (size), _CACHE_UNCACHED) 252 #define ioremap_uc ioremap_nocache 253 254 /* 255 * ioremap_cachable - map bus memory into CPU space 256 * @offset: bus address of the memory 257 * @size: size of the resource to map 258 * 259 * ioremap_nocache performs a platform specific sequence of operations to 260 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 261 * writew/writel functions and the other mmio helpers. The returned 262 * address is not guaranteed to be usable directly as a virtual 263 * address. 264 * 265 * This version of ioremap ensures that the memory is marked cachable by 266 * the CPU. Also enables full write-combining. Useful for some 267 * memory-like regions on I/O busses. 268 */ 269 #define ioremap_cachable(offset, size) \ 270 __ioremap_mode((offset), (size), _page_cachable_default) 271 #define ioremap_cache ioremap_cachable 272 273 /* 274 * ioremap_wc - map bus memory into CPU space 275 * @offset: bus address of the memory 276 * @size: size of the resource to map 277 * 278 * ioremap_wc performs a platform specific sequence of operations to 279 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 280 * writew/writel functions and the other mmio helpers. The returned 281 * address is not guaranteed to be usable directly as a virtual 282 * address. 283 * 284 * This version of ioremap ensures that the memory is marked uncachable 285 * but accelerated by means of write-combining feature. It is specifically 286 * useful for PCIe prefetchable windows, which may vastly improve a 287 * communications performance. If it was determined on boot stage, what 288 * CPU CCA doesn't support UCA, the method shall fall-back to the 289 * _CACHE_UNCACHED option (see cpu_probe() method). 290 */ 291 #define ioremap_wc(offset, size) \ 292 __ioremap_mode((offset), (size), boot_cpu_data.writecombine) 293 294 static inline void iounmap(const volatile void __iomem *addr) 295 { 296 if (plat_iounmap(addr)) 297 return; 298 299 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) 300 301 if (cpu_has_64bit_addresses || 302 (__builtin_constant_p(addr) && __IS_KSEG1(addr))) 303 return; 304 305 __iounmap(addr); 306 307 #undef __IS_KSEG1 308 } 309 310 #if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON3) 311 #define war_io_reorder_wmb() wmb() 312 #else 313 #define war_io_reorder_wmb() barrier() 314 #endif 315 316 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq) \ 317 \ 318 static inline void pfx##write##bwlq(type val, \ 319 volatile void __iomem *mem) \ 320 { \ 321 volatile type *__mem; \ 322 type __val; \ 323 \ 324 if (barrier) \ 325 iobarrier_rw(); \ 326 else \ 327 war_io_reorder_wmb(); \ 328 \ 329 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 330 \ 331 __val = pfx##ioswab##bwlq(__mem, val); \ 332 \ 333 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 334 *__mem = __val; \ 335 else if (cpu_has_64bits) { \ 336 unsigned long __flags; \ 337 type __tmp; \ 338 \ 339 if (irq) \ 340 local_irq_save(__flags); \ 341 __asm__ __volatile__( \ 342 ".set push" "\t\t# __writeq""\n\t" \ 343 ".set arch=r4000" "\n\t" \ 344 "dsll32 %L0, %L0, 0" "\n\t" \ 345 "dsrl32 %L0, %L0, 0" "\n\t" \ 346 "dsll32 %M0, %M0, 0" "\n\t" \ 347 "or %L0, %L0, %M0" "\n\t" \ 348 "sd %L0, %2" "\n\t" \ 349 ".set pop" "\n" \ 350 : "=r" (__tmp) \ 351 : "0" (__val), "m" (*__mem)); \ 352 if (irq) \ 353 local_irq_restore(__flags); \ 354 } else \ 355 BUG(); \ 356 } \ 357 \ 358 static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ 359 { \ 360 volatile type *__mem; \ 361 type __val; \ 362 \ 363 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 364 \ 365 if (barrier) \ 366 iobarrier_rw(); \ 367 \ 368 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 369 __val = *__mem; \ 370 else if (cpu_has_64bits) { \ 371 unsigned long __flags; \ 372 \ 373 if (irq) \ 374 local_irq_save(__flags); \ 375 __asm__ __volatile__( \ 376 ".set push" "\t\t# __readq" "\n\t" \ 377 ".set arch=r4000" "\n\t" \ 378 "ld %L0, %1" "\n\t" \ 379 "dsra32 %M0, %L0, 0" "\n\t" \ 380 "sll %L0, %L0, 0" "\n\t" \ 381 ".set pop" "\n" \ 382 : "=r" (__val) \ 383 : "m" (*__mem)); \ 384 if (irq) \ 385 local_irq_restore(__flags); \ 386 } else { \ 387 __val = 0; \ 388 BUG(); \ 389 } \ 390 \ 391 /* prevent prefetching of coherent DMA data prematurely */ \ 392 if (!relax) \ 393 rmb(); \ 394 return pfx##ioswab##bwlq(__mem, __val); \ 395 } 396 397 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p) \ 398 \ 399 static inline void pfx##out##bwlq##p(type val, unsigned long port) \ 400 { \ 401 volatile type *__addr; \ 402 type __val; \ 403 \ 404 if (barrier) \ 405 iobarrier_rw(); \ 406 else \ 407 war_io_reorder_wmb(); \ 408 \ 409 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 410 \ 411 __val = pfx##ioswab##bwlq(__addr, val); \ 412 \ 413 /* Really, we want this to be atomic */ \ 414 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 415 \ 416 *__addr = __val; \ 417 } \ 418 \ 419 static inline type pfx##in##bwlq##p(unsigned long port) \ 420 { \ 421 volatile type *__addr; \ 422 type __val; \ 423 \ 424 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 425 \ 426 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 427 \ 428 if (barrier) \ 429 iobarrier_rw(); \ 430 \ 431 __val = *__addr; \ 432 \ 433 /* prevent prefetching of coherent DMA data prematurely */ \ 434 if (!relax) \ 435 rmb(); \ 436 return pfx##ioswab##bwlq(__addr, __val); \ 437 } 438 439 #define __BUILD_MEMORY_PFX(bus, bwlq, type, relax) \ 440 \ 441 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1) 442 443 #define BUILDIO_MEM(bwlq, type) \ 444 \ 445 __BUILD_MEMORY_PFX(__raw_, bwlq, type, 0) \ 446 __BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1) \ 447 __BUILD_MEMORY_PFX(__mem_, bwlq, type, 0) \ 448 __BUILD_MEMORY_PFX(, bwlq, type, 0) 449 450 BUILDIO_MEM(b, u8) 451 BUILDIO_MEM(w, u16) 452 BUILDIO_MEM(l, u32) 453 #ifdef CONFIG_64BIT 454 BUILDIO_MEM(q, u64) 455 #else 456 __BUILD_MEMORY_PFX(__raw_, q, u64, 0) 457 __BUILD_MEMORY_PFX(__mem_, q, u64, 0) 458 #endif 459 460 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ 461 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \ 462 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p) 463 464 #define BUILDIO_IOPORT(bwlq, type) \ 465 __BUILD_IOPORT_PFX(, bwlq, type) \ 466 __BUILD_IOPORT_PFX(__mem_, bwlq, type) 467 468 BUILDIO_IOPORT(b, u8) 469 BUILDIO_IOPORT(w, u16) 470 BUILDIO_IOPORT(l, u32) 471 #ifdef CONFIG_64BIT 472 BUILDIO_IOPORT(q, u64) 473 #endif 474 475 #define __BUILDIO(bwlq, type) \ 476 \ 477 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0) 478 479 __BUILDIO(q, u64) 480 481 #define readb_relaxed __relaxed_readb 482 #define readw_relaxed __relaxed_readw 483 #define readl_relaxed __relaxed_readl 484 #ifdef CONFIG_64BIT 485 #define readq_relaxed __relaxed_readq 486 #endif 487 488 #define writeb_relaxed __relaxed_writeb 489 #define writew_relaxed __relaxed_writew 490 #define writel_relaxed __relaxed_writel 491 #ifdef CONFIG_64BIT 492 #define writeq_relaxed __relaxed_writeq 493 #endif 494 495 #define readb_be(addr) \ 496 __raw_readb((__force unsigned *)(addr)) 497 #define readw_be(addr) \ 498 be16_to_cpu(__raw_readw((__force unsigned *)(addr))) 499 #define readl_be(addr) \ 500 be32_to_cpu(__raw_readl((__force unsigned *)(addr))) 501 #define readq_be(addr) \ 502 be64_to_cpu(__raw_readq((__force unsigned *)(addr))) 503 504 #define writeb_be(val, addr) \ 505 __raw_writeb((val), (__force unsigned *)(addr)) 506 #define writew_be(val, addr) \ 507 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr)) 508 #define writel_be(val, addr) \ 509 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr)) 510 #define writeq_be(val, addr) \ 511 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr)) 512 513 /* 514 * Some code tests for these symbols 515 */ 516 #ifdef CONFIG_64BIT 517 #define readq readq 518 #define writeq writeq 519 #endif 520 521 #define __BUILD_MEMORY_STRING(bwlq, type) \ 522 \ 523 static inline void writes##bwlq(volatile void __iomem *mem, \ 524 const void *addr, unsigned int count) \ 525 { \ 526 const volatile type *__addr = addr; \ 527 \ 528 while (count--) { \ 529 __mem_write##bwlq(*__addr, mem); \ 530 __addr++; \ 531 } \ 532 } \ 533 \ 534 static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ 535 unsigned int count) \ 536 { \ 537 volatile type *__addr = addr; \ 538 \ 539 while (count--) { \ 540 *__addr = __mem_read##bwlq(mem); \ 541 __addr++; \ 542 } \ 543 } 544 545 #define __BUILD_IOPORT_STRING(bwlq, type) \ 546 \ 547 static inline void outs##bwlq(unsigned long port, const void *addr, \ 548 unsigned int count) \ 549 { \ 550 const volatile type *__addr = addr; \ 551 \ 552 while (count--) { \ 553 __mem_out##bwlq(*__addr, port); \ 554 __addr++; \ 555 } \ 556 } \ 557 \ 558 static inline void ins##bwlq(unsigned long port, void *addr, \ 559 unsigned int count) \ 560 { \ 561 volatile type *__addr = addr; \ 562 \ 563 while (count--) { \ 564 *__addr = __mem_in##bwlq(port); \ 565 __addr++; \ 566 } \ 567 } 568 569 #define BUILDSTRING(bwlq, type) \ 570 \ 571 __BUILD_MEMORY_STRING(bwlq, type) \ 572 __BUILD_IOPORT_STRING(bwlq, type) 573 574 BUILDSTRING(b, u8) 575 BUILDSTRING(w, u16) 576 BUILDSTRING(l, u32) 577 #ifdef CONFIG_64BIT 578 BUILDSTRING(q, u64) 579 #endif 580 581 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) 582 { 583 memset((void __force *) addr, val, count); 584 } 585 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) 586 { 587 memcpy(dst, (void __force *) src, count); 588 } 589 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) 590 { 591 memcpy((void __force *) dst, src, count); 592 } 593 594 /* 595 * The caches on some architectures aren't dma-coherent and have need to 596 * handle this in software. There are three types of operations that 597 * can be applied to dma buffers. 598 * 599 * - dma_cache_wback_inv(start, size) makes caches and coherent by 600 * writing the content of the caches back to memory, if necessary. 601 * The function also invalidates the affected part of the caches as 602 * necessary before DMA transfers from outside to memory. 603 * - dma_cache_wback(start, size) makes caches and coherent by 604 * writing the content of the caches back to memory, if necessary. 605 * The function also invalidates the affected part of the caches as 606 * necessary before DMA transfers from outside to memory. 607 * - dma_cache_inv(start, size) invalidates the affected parts of the 608 * caches. Dirty lines of the caches may be written back or simply 609 * be discarded. This operation is necessary before dma operations 610 * to the memory. 611 * 612 * This API used to be exported; it now is for arch code internal use only. 613 */ 614 #ifdef CONFIG_DMA_NONCOHERENT 615 616 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); 617 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); 618 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); 619 620 #define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size) 621 #define dma_cache_wback(start, size) _dma_cache_wback(start, size) 622 #define dma_cache_inv(start, size) _dma_cache_inv(start, size) 623 624 #else /* Sane hardware */ 625 626 #define dma_cache_wback_inv(start,size) \ 627 do { (void) (start); (void) (size); } while (0) 628 #define dma_cache_wback(start,size) \ 629 do { (void) (start); (void) (size); } while (0) 630 #define dma_cache_inv(start,size) \ 631 do { (void) (start); (void) (size); } while (0) 632 633 #endif /* CONFIG_DMA_NONCOHERENT */ 634 635 /* 636 * Read a 32-bit register that requires a 64-bit read cycle on the bus. 637 * Avoid interrupt mucking, just adjust the address for 4-byte access. 638 * Assume the addresses are 8-byte aligned. 639 */ 640 #ifdef __MIPSEB__ 641 #define __CSR_32_ADJUST 4 642 #else 643 #define __CSR_32_ADJUST 0 644 #endif 645 646 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) 647 #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) 648 649 /* 650 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 651 * access 652 */ 653 #define xlate_dev_mem_ptr(p) __va(p) 654 655 /* 656 * Convert a virtual cached pointer to an uncached pointer 657 */ 658 #define xlate_dev_kmem_ptr(p) p 659 660 void __ioread64_copy(void *to, const void __iomem *from, size_t count); 661 662 #endif /* _ASM_IO_H */ 663