1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995 Waldorf GmbH 7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 10 * Author: Maciej W. Rozycki <macro@mips.com> 11 */ 12 #ifndef _ASM_IO_H 13 #define _ASM_IO_H 14 15 #define ARCH_HAS_IOREMAP_WC 16 17 #include <linux/compiler.h> 18 #include <linux/kernel.h> 19 #include <linux/types.h> 20 #include <linux/irqflags.h> 21 22 #include <asm/addrspace.h> 23 #include <asm/barrier.h> 24 #include <asm/bug.h> 25 #include <asm/byteorder.h> 26 #include <asm/cpu.h> 27 #include <asm/cpu-features.h> 28 #include <asm-generic/iomap.h> 29 #include <asm/page.h> 30 #include <asm/pgtable-bits.h> 31 #include <asm/processor.h> 32 #include <asm/string.h> 33 34 #include <ioremap.h> 35 #include <mangle-port.h> 36 37 /* 38 * Raw operations are never swapped in software. OTOH values that raw 39 * operations are working on may or may not have been swapped by the bus 40 * hardware. An example use would be for flash memory that's used for 41 * execute in place. 42 */ 43 # define __raw_ioswabb(a, x) (x) 44 # define __raw_ioswabw(a, x) (x) 45 # define __raw_ioswabl(a, x) (x) 46 # define __raw_ioswabq(a, x) (x) 47 # define ____raw_ioswabq(a, x) (x) 48 49 # define __relaxed_ioswabb ioswabb 50 # define __relaxed_ioswabw ioswabw 51 # define __relaxed_ioswabl ioswabl 52 # define __relaxed_ioswabq ioswabq 53 54 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ 55 56 #define IO_SPACE_LIMIT 0xffff 57 58 /* 59 * On MIPS I/O ports are memory mapped, so we access them using normal 60 * load/store instructions. mips_io_port_base is the virtual address to 61 * which all ports are being mapped. For sake of efficiency some code 62 * assumes that this is an address that can be loaded with a single lui 63 * instruction, so the lower 16 bits must be zero. Should be true on 64 * on any sane architecture; generic code does not use this assumption. 65 */ 66 extern const unsigned long mips_io_port_base; 67 68 /* 69 * Gcc will generate code to load the value of mips_io_port_base after each 70 * function call which may be fairly wasteful in some cases. So we don't 71 * play quite by the book. We tell gcc mips_io_port_base is a long variable 72 * which solves the code generation issue. Now we need to violate the 73 * aliasing rules a little to make initialization possible and finally we 74 * will need the barrier() to fight side effects of the aliasing chat. 75 * This trickery will eventually collapse under gcc's optimizer. Oh well. 76 */ 77 static inline void set_io_port_base(unsigned long base) 78 { 79 * (unsigned long *) &mips_io_port_base = base; 80 barrier(); 81 } 82 83 /* 84 * Provide the necessary definitions for generic iomap. We make use of 85 * mips_io_port_base for iomap(), but we don't reserve any low addresses for 86 * use with I/O ports. 87 */ 88 89 #define HAVE_ARCH_PIO_SIZE 90 #define PIO_OFFSET mips_io_port_base 91 #define PIO_MASK IO_SPACE_LIMIT 92 #define PIO_RESERVED 0x0UL 93 94 /* 95 * Enforce in-order execution of data I/O. In the MIPS architecture 96 * these are equivalent to corresponding platform-specific memory 97 * barriers defined in <asm/barrier.h>. API pinched from PowerPC, 98 * with sync additionally defined. 99 */ 100 #define iobarrier_rw() mb() 101 #define iobarrier_r() rmb() 102 #define iobarrier_w() wmb() 103 #define iobarrier_sync() iob() 104 105 /* 106 * virt_to_phys - map virtual addresses to physical 107 * @address: address to remap 108 * 109 * The returned physical address is the physical (CPU) mapping for 110 * the memory address given. It is only valid to use this function on 111 * addresses directly mapped or allocated via kmalloc. 112 * 113 * This function does not give bus mappings for DMA transfers. In 114 * almost all conceivable cases a device driver should not be using 115 * this function 116 */ 117 static inline unsigned long virt_to_phys(volatile const void *address) 118 { 119 return __pa(address); 120 } 121 122 /* 123 * phys_to_virt - map physical address to virtual 124 * @address: address to remap 125 * 126 * The returned virtual address is a current CPU mapping for 127 * the memory address given. It is only valid to use this function on 128 * addresses that have a kernel mapping 129 * 130 * This function does not handle bus mappings for DMA transfers. In 131 * almost all conceivable cases a device driver should not be using 132 * this function 133 */ 134 static inline void * phys_to_virt(unsigned long address) 135 { 136 return (void *)(address + PAGE_OFFSET - PHYS_OFFSET); 137 } 138 139 /* 140 * ISA I/O bus memory addresses are 1:1 with the physical address. 141 */ 142 static inline unsigned long isa_virt_to_bus(volatile void *address) 143 { 144 return virt_to_phys(address); 145 } 146 147 static inline void *isa_bus_to_virt(unsigned long address) 148 { 149 return phys_to_virt(address); 150 } 151 152 #define isa_page_to_bus page_to_phys 153 154 /* 155 * However PCI ones are not necessarily 1:1 and therefore these interfaces 156 * are forbidden in portable PCI drivers. 157 * 158 * Allow them for x86 for legacy drivers, though. 159 */ 160 #define virt_to_bus virt_to_phys 161 #define bus_to_virt phys_to_virt 162 163 /* 164 * Change "struct page" to physical address. 165 */ 166 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) 167 168 extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags); 169 extern void __iounmap(const volatile void __iomem *addr); 170 171 static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size, 172 unsigned long flags) 173 { 174 void __iomem *addr = plat_ioremap(offset, size, flags); 175 176 if (addr) 177 return addr; 178 179 #define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL)) 180 181 if (cpu_has_64bit_addresses) { 182 u64 base = UNCAC_BASE; 183 184 /* 185 * R10000 supports a 2 bit uncached attribute therefore 186 * UNCAC_BASE may not equal IO_BASE. 187 */ 188 if (flags == _CACHE_UNCACHED) 189 base = (u64) IO_BASE; 190 return (void __iomem *) (unsigned long) (base + offset); 191 } else if (__builtin_constant_p(offset) && 192 __builtin_constant_p(size) && __builtin_constant_p(flags)) { 193 phys_addr_t phys_addr, last_addr; 194 195 phys_addr = fixup_bigphys_addr(offset, size); 196 197 /* Don't allow wraparound or zero size. */ 198 last_addr = phys_addr + size - 1; 199 if (!size || last_addr < phys_addr) 200 return NULL; 201 202 /* 203 * Map uncached objects in the low 512MB of address 204 * space using KSEG1. 205 */ 206 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) && 207 flags == _CACHE_UNCACHED) 208 return (void __iomem *) 209 (unsigned long)CKSEG1ADDR(phys_addr); 210 } 211 212 return __ioremap(offset, size, flags); 213 214 #undef __IS_LOW512 215 } 216 217 /* 218 * ioremap_prot - map bus memory into CPU space 219 * @offset: bus address of the memory 220 * @size: size of the resource to map 221 222 * ioremap_prot gives the caller control over cache coherency attributes (CCA) 223 */ 224 static inline void __iomem *ioremap_prot(phys_addr_t offset, 225 unsigned long size, unsigned long prot_val) { 226 return __ioremap_mode(offset, size, prot_val & _CACHE_MASK); 227 } 228 229 /* 230 * ioremap - map bus memory into CPU space 231 * @offset: bus address of the memory 232 * @size: size of the resource to map 233 * 234 * ioremap performs a platform specific sequence of operations to 235 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 236 * writew/writel functions and the other mmio helpers. The returned 237 * address is not guaranteed to be usable directly as a virtual 238 * address. 239 */ 240 #define ioremap(offset, size) \ 241 __ioremap_mode((offset), (size), _CACHE_UNCACHED) 242 243 /* 244 * ioremap_nocache - map bus memory into CPU space 245 * @offset: bus address of the memory 246 * @size: size of the resource to map 247 * 248 * ioremap_nocache performs a platform specific sequence of operations to 249 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 250 * writew/writel functions and the other mmio helpers. The returned 251 * address is not guaranteed to be usable directly as a virtual 252 * address. 253 * 254 * This version of ioremap ensures that the memory is marked uncachable 255 * on the CPU as well as honouring existing caching rules from things like 256 * the PCI bus. Note that there are other caches and buffers on many 257 * busses. In particular driver authors should read up on PCI writes 258 * 259 * It's useful if some control registers are in such an area and 260 * write combining or read caching is not desirable: 261 */ 262 #define ioremap_nocache(offset, size) \ 263 __ioremap_mode((offset), (size), _CACHE_UNCACHED) 264 #define ioremap_uc ioremap_nocache 265 266 /* 267 * ioremap_cachable - map bus memory into CPU space 268 * @offset: bus address of the memory 269 * @size: size of the resource to map 270 * 271 * ioremap_nocache performs a platform specific sequence of operations to 272 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 273 * writew/writel functions and the other mmio helpers. The returned 274 * address is not guaranteed to be usable directly as a virtual 275 * address. 276 * 277 * This version of ioremap ensures that the memory is marked cachable by 278 * the CPU. Also enables full write-combining. Useful for some 279 * memory-like regions on I/O busses. 280 */ 281 #define ioremap_cachable(offset, size) \ 282 __ioremap_mode((offset), (size), _page_cachable_default) 283 #define ioremap_cache ioremap_cachable 284 285 /* 286 * ioremap_wc - map bus memory into CPU space 287 * @offset: bus address of the memory 288 * @size: size of the resource to map 289 * 290 * ioremap_wc performs a platform specific sequence of operations to 291 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 292 * writew/writel functions and the other mmio helpers. The returned 293 * address is not guaranteed to be usable directly as a virtual 294 * address. 295 * 296 * This version of ioremap ensures that the memory is marked uncachable 297 * but accelerated by means of write-combining feature. It is specifically 298 * useful for PCIe prefetchable windows, which may vastly improve a 299 * communications performance. If it was determined on boot stage, what 300 * CPU CCA doesn't support UCA, the method shall fall-back to the 301 * _CACHE_UNCACHED option (see cpu_probe() method). 302 */ 303 #define ioremap_wc(offset, size) \ 304 __ioremap_mode((offset), (size), boot_cpu_data.writecombine) 305 306 static inline void iounmap(const volatile void __iomem *addr) 307 { 308 if (plat_iounmap(addr)) 309 return; 310 311 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) 312 313 if (cpu_has_64bit_addresses || 314 (__builtin_constant_p(addr) && __IS_KSEG1(addr))) 315 return; 316 317 __iounmap(addr); 318 319 #undef __IS_KSEG1 320 } 321 322 #if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON3) 323 #define war_io_reorder_wmb() wmb() 324 #else 325 #define war_io_reorder_wmb() barrier() 326 #endif 327 328 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq) \ 329 \ 330 static inline void pfx##write##bwlq(type val, \ 331 volatile void __iomem *mem) \ 332 { \ 333 volatile type *__mem; \ 334 type __val; \ 335 \ 336 if (barrier) \ 337 iobarrier_rw(); \ 338 else \ 339 war_io_reorder_wmb(); \ 340 \ 341 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 342 \ 343 __val = pfx##ioswab##bwlq(__mem, val); \ 344 \ 345 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 346 *__mem = __val; \ 347 else if (cpu_has_64bits) { \ 348 unsigned long __flags; \ 349 type __tmp; \ 350 \ 351 if (irq) \ 352 local_irq_save(__flags); \ 353 __asm__ __volatile__( \ 354 ".set push" "\t\t# __writeq""\n\t" \ 355 ".set arch=r4000" "\n\t" \ 356 "dsll32 %L0, %L0, 0" "\n\t" \ 357 "dsrl32 %L0, %L0, 0" "\n\t" \ 358 "dsll32 %M0, %M0, 0" "\n\t" \ 359 "or %L0, %L0, %M0" "\n\t" \ 360 "sd %L0, %2" "\n\t" \ 361 ".set pop" "\n" \ 362 : "=r" (__tmp) \ 363 : "0" (__val), "m" (*__mem)); \ 364 if (irq) \ 365 local_irq_restore(__flags); \ 366 } else \ 367 BUG(); \ 368 } \ 369 \ 370 static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ 371 { \ 372 volatile type *__mem; \ 373 type __val; \ 374 \ 375 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 376 \ 377 if (barrier) \ 378 iobarrier_rw(); \ 379 \ 380 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 381 __val = *__mem; \ 382 else if (cpu_has_64bits) { \ 383 unsigned long __flags; \ 384 \ 385 if (irq) \ 386 local_irq_save(__flags); \ 387 __asm__ __volatile__( \ 388 ".set push" "\t\t# __readq" "\n\t" \ 389 ".set arch=r4000" "\n\t" \ 390 "ld %L0, %1" "\n\t" \ 391 "dsra32 %M0, %L0, 0" "\n\t" \ 392 "sll %L0, %L0, 0" "\n\t" \ 393 ".set pop" "\n" \ 394 : "=r" (__val) \ 395 : "m" (*__mem)); \ 396 if (irq) \ 397 local_irq_restore(__flags); \ 398 } else { \ 399 __val = 0; \ 400 BUG(); \ 401 } \ 402 \ 403 /* prevent prefetching of coherent DMA data prematurely */ \ 404 if (!relax) \ 405 rmb(); \ 406 return pfx##ioswab##bwlq(__mem, __val); \ 407 } 408 409 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p) \ 410 \ 411 static inline void pfx##out##bwlq##p(type val, unsigned long port) \ 412 { \ 413 volatile type *__addr; \ 414 type __val; \ 415 \ 416 if (barrier) \ 417 iobarrier_rw(); \ 418 else \ 419 war_io_reorder_wmb(); \ 420 \ 421 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 422 \ 423 __val = pfx##ioswab##bwlq(__addr, val); \ 424 \ 425 /* Really, we want this to be atomic */ \ 426 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 427 \ 428 *__addr = __val; \ 429 } \ 430 \ 431 static inline type pfx##in##bwlq##p(unsigned long port) \ 432 { \ 433 volatile type *__addr; \ 434 type __val; \ 435 \ 436 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 437 \ 438 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 439 \ 440 if (barrier) \ 441 iobarrier_rw(); \ 442 \ 443 __val = *__addr; \ 444 \ 445 /* prevent prefetching of coherent DMA data prematurely */ \ 446 if (!relax) \ 447 rmb(); \ 448 return pfx##ioswab##bwlq(__addr, __val); \ 449 } 450 451 #define __BUILD_MEMORY_PFX(bus, bwlq, type, relax) \ 452 \ 453 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1) 454 455 #define BUILDIO_MEM(bwlq, type) \ 456 \ 457 __BUILD_MEMORY_PFX(__raw_, bwlq, type, 0) \ 458 __BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1) \ 459 __BUILD_MEMORY_PFX(__mem_, bwlq, type, 0) \ 460 __BUILD_MEMORY_PFX(, bwlq, type, 0) 461 462 BUILDIO_MEM(b, u8) 463 BUILDIO_MEM(w, u16) 464 BUILDIO_MEM(l, u32) 465 BUILDIO_MEM(q, u64) 466 467 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ 468 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \ 469 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p) 470 471 #define BUILDIO_IOPORT(bwlq, type) \ 472 __BUILD_IOPORT_PFX(, bwlq, type) \ 473 __BUILD_IOPORT_PFX(__mem_, bwlq, type) 474 475 BUILDIO_IOPORT(b, u8) 476 BUILDIO_IOPORT(w, u16) 477 BUILDIO_IOPORT(l, u32) 478 #ifdef CONFIG_64BIT 479 BUILDIO_IOPORT(q, u64) 480 #endif 481 482 #define __BUILDIO(bwlq, type) \ 483 \ 484 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0) 485 486 __BUILDIO(q, u64) 487 488 #define readb_relaxed __relaxed_readb 489 #define readw_relaxed __relaxed_readw 490 #define readl_relaxed __relaxed_readl 491 #define readq_relaxed __relaxed_readq 492 493 #define writeb_relaxed __relaxed_writeb 494 #define writew_relaxed __relaxed_writew 495 #define writel_relaxed __relaxed_writel 496 #define writeq_relaxed __relaxed_writeq 497 498 #define readb_be(addr) \ 499 __raw_readb((__force unsigned *)(addr)) 500 #define readw_be(addr) \ 501 be16_to_cpu(__raw_readw((__force unsigned *)(addr))) 502 #define readl_be(addr) \ 503 be32_to_cpu(__raw_readl((__force unsigned *)(addr))) 504 #define readq_be(addr) \ 505 be64_to_cpu(__raw_readq((__force unsigned *)(addr))) 506 507 #define writeb_be(val, addr) \ 508 __raw_writeb((val), (__force unsigned *)(addr)) 509 #define writew_be(val, addr) \ 510 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr)) 511 #define writel_be(val, addr) \ 512 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr)) 513 #define writeq_be(val, addr) \ 514 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr)) 515 516 /* 517 * Some code tests for these symbols 518 */ 519 #define readq readq 520 #define writeq writeq 521 522 #define __BUILD_MEMORY_STRING(bwlq, type) \ 523 \ 524 static inline void writes##bwlq(volatile void __iomem *mem, \ 525 const void *addr, unsigned int count) \ 526 { \ 527 const volatile type *__addr = addr; \ 528 \ 529 while (count--) { \ 530 __mem_write##bwlq(*__addr, mem); \ 531 __addr++; \ 532 } \ 533 } \ 534 \ 535 static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ 536 unsigned int count) \ 537 { \ 538 volatile type *__addr = addr; \ 539 \ 540 while (count--) { \ 541 *__addr = __mem_read##bwlq(mem); \ 542 __addr++; \ 543 } \ 544 } 545 546 #define __BUILD_IOPORT_STRING(bwlq, type) \ 547 \ 548 static inline void outs##bwlq(unsigned long port, const void *addr, \ 549 unsigned int count) \ 550 { \ 551 const volatile type *__addr = addr; \ 552 \ 553 while (count--) { \ 554 __mem_out##bwlq(*__addr, port); \ 555 __addr++; \ 556 } \ 557 } \ 558 \ 559 static inline void ins##bwlq(unsigned long port, void *addr, \ 560 unsigned int count) \ 561 { \ 562 volatile type *__addr = addr; \ 563 \ 564 while (count--) { \ 565 *__addr = __mem_in##bwlq(port); \ 566 __addr++; \ 567 } \ 568 } 569 570 #define BUILDSTRING(bwlq, type) \ 571 \ 572 __BUILD_MEMORY_STRING(bwlq, type) \ 573 __BUILD_IOPORT_STRING(bwlq, type) 574 575 BUILDSTRING(b, u8) 576 BUILDSTRING(w, u16) 577 BUILDSTRING(l, u32) 578 #ifdef CONFIG_64BIT 579 BUILDSTRING(q, u64) 580 #endif 581 582 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) 583 { 584 memset((void __force *) addr, val, count); 585 } 586 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) 587 { 588 memcpy(dst, (void __force *) src, count); 589 } 590 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) 591 { 592 memcpy((void __force *) dst, src, count); 593 } 594 595 /* 596 * The caches on some architectures aren't dma-coherent and have need to 597 * handle this in software. There are three types of operations that 598 * can be applied to dma buffers. 599 * 600 * - dma_cache_wback_inv(start, size) makes caches and coherent by 601 * writing the content of the caches back to memory, if necessary. 602 * The function also invalidates the affected part of the caches as 603 * necessary before DMA transfers from outside to memory. 604 * - dma_cache_wback(start, size) makes caches and coherent by 605 * writing the content of the caches back to memory, if necessary. 606 * The function also invalidates the affected part of the caches as 607 * necessary before DMA transfers from outside to memory. 608 * - dma_cache_inv(start, size) invalidates the affected parts of the 609 * caches. Dirty lines of the caches may be written back or simply 610 * be discarded. This operation is necessary before dma operations 611 * to the memory. 612 * 613 * This API used to be exported; it now is for arch code internal use only. 614 */ 615 #ifdef CONFIG_DMA_NONCOHERENT 616 617 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); 618 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); 619 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); 620 621 #define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size) 622 #define dma_cache_wback(start, size) _dma_cache_wback(start, size) 623 #define dma_cache_inv(start, size) _dma_cache_inv(start, size) 624 625 #else /* Sane hardware */ 626 627 #define dma_cache_wback_inv(start,size) \ 628 do { (void) (start); (void) (size); } while (0) 629 #define dma_cache_wback(start,size) \ 630 do { (void) (start); (void) (size); } while (0) 631 #define dma_cache_inv(start,size) \ 632 do { (void) (start); (void) (size); } while (0) 633 634 #endif /* CONFIG_DMA_NONCOHERENT */ 635 636 /* 637 * Read a 32-bit register that requires a 64-bit read cycle on the bus. 638 * Avoid interrupt mucking, just adjust the address for 4-byte access. 639 * Assume the addresses are 8-byte aligned. 640 */ 641 #ifdef __MIPSEB__ 642 #define __CSR_32_ADJUST 4 643 #else 644 #define __CSR_32_ADJUST 0 645 #endif 646 647 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) 648 #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) 649 650 /* 651 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 652 * access 653 */ 654 #define xlate_dev_mem_ptr(p) __va(p) 655 656 /* 657 * Convert a virtual cached pointer to an uncached pointer 658 */ 659 #define xlate_dev_kmem_ptr(p) p 660 661 void __ioread64_copy(void *to, const void __iomem *from, size_t count); 662 663 #endif /* _ASM_IO_H */ 664