1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * cpu.h: Values of the PRId register used to match up 4 * various MIPS cpu types. 5 * 6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 7 * Copyright (C) 2004, 2013 Maciej W. Rozycki 8 */ 9 #ifndef _ASM_CPU_H 10 #define _ASM_CPU_H 11 12 /* 13 As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0 14 register 15, select 0) is defined in this (backwards compatible) way: 15 16 +----------------+----------------+----------------+----------------+ 17 | Company Options| Company ID | Processor ID | Revision | 18 +----------------+----------------+----------------+----------------+ 19 31 24 23 16 15 8 7 20 21 I don't have docs for all the previous processors, but my impression is 22 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 23 spec. 24 */ 25 26 #define PRID_OPT_MASK 0xff000000 27 28 /* 29 * Assigned Company values for bits 23:16 of the PRId register. 30 */ 31 32 #define PRID_COMP_MASK 0xff0000 33 34 #define PRID_COMP_LEGACY 0x000000 35 #define PRID_COMP_MIPS 0x010000 36 #define PRID_COMP_BROADCOM 0x020000 37 #define PRID_COMP_ALCHEMY 0x030000 38 #define PRID_COMP_SIBYTE 0x040000 39 #define PRID_COMP_SANDCRAFT 0x050000 40 #define PRID_COMP_NXP 0x060000 41 #define PRID_COMP_TOSHIBA 0x070000 42 #define PRID_COMP_LSI 0x080000 43 #define PRID_COMP_LEXRA 0x0b0000 44 #define PRID_COMP_NETLOGIC 0x0c0000 45 #define PRID_COMP_CAVIUM 0x0d0000 46 #define PRID_COMP_LOONGSON 0x140000 47 #define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4740, JZ4750 */ 48 #define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775 */ 49 #define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */ 50 51 /* 52 * Assigned Processor ID (implementation) values for bits 15:8 of the PRId 53 * register. In order to detect a certain CPU type exactly eventually 54 * additional registers may need to be examined. 55 */ 56 57 #define PRID_IMP_MASK 0xff00 58 59 /* 60 * These are valid when 23:16 == PRID_COMP_LEGACY 61 */ 62 63 #define PRID_IMP_R2000 0x0100 64 #define PRID_IMP_AU1_REV1 0x0100 65 #define PRID_IMP_AU1_REV2 0x0200 66 #define PRID_IMP_R3000 0x0200 /* Same as R2000A */ 67 #define PRID_IMP_R6000 0x0300 /* Same as R3000A */ 68 #define PRID_IMP_R4000 0x0400 69 #define PRID_IMP_R6000A 0x0600 70 #define PRID_IMP_R10000 0x0900 71 #define PRID_IMP_R4300 0x0b00 72 #define PRID_IMP_VR41XX 0x0c00 73 #define PRID_IMP_R12000 0x0e00 74 #define PRID_IMP_R14000 0x0f00 /* R14K && R16K */ 75 #define PRID_IMP_R8000 0x1000 76 #define PRID_IMP_PR4450 0x1200 77 #define PRID_IMP_R4600 0x2000 78 #define PRID_IMP_R4700 0x2100 79 #define PRID_IMP_TX39 0x2200 80 #define PRID_IMP_R4640 0x2200 81 #define PRID_IMP_R4650 0x2200 /* Same as R4640 */ 82 #define PRID_IMP_R5000 0x2300 83 #define PRID_IMP_TX49 0x2d00 84 #define PRID_IMP_SONIC 0x2400 85 #define PRID_IMP_MAGIC 0x2500 86 #define PRID_IMP_RM7000 0x2700 87 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ 88 #define PRID_IMP_RM9000 0x3400 89 #define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */ 90 #define PRID_IMP_R5432 0x5400 91 #define PRID_IMP_R5500 0x5500 92 #define PRID_IMP_LOONGSON_64 0x6300 /* Loongson-2/3 */ 93 94 #define PRID_IMP_UNKNOWN 0xff00 95 96 /* 97 * These are the PRID's for when 23:16 == PRID_COMP_MIPS 98 */ 99 100 #define PRID_IMP_QEMU_GENERIC 0x0000 101 #define PRID_IMP_4KC 0x8000 102 #define PRID_IMP_5KC 0x8100 103 #define PRID_IMP_20KC 0x8200 104 #define PRID_IMP_4KEC 0x8400 105 #define PRID_IMP_4KSC 0x8600 106 #define PRID_IMP_25KF 0x8800 107 #define PRID_IMP_5KE 0x8900 108 #define PRID_IMP_4KECR2 0x9000 109 #define PRID_IMP_4KEMPR2 0x9100 110 #define PRID_IMP_4KSD 0x9200 111 #define PRID_IMP_24K 0x9300 112 #define PRID_IMP_34K 0x9500 113 #define PRID_IMP_24KE 0x9600 114 #define PRID_IMP_74K 0x9700 115 #define PRID_IMP_1004K 0x9900 116 #define PRID_IMP_1074K 0x9a00 117 #define PRID_IMP_M14KC 0x9c00 118 #define PRID_IMP_M14KEC 0x9e00 119 #define PRID_IMP_INTERAPTIV_UP 0xa000 120 #define PRID_IMP_INTERAPTIV_MP 0xa100 121 #define PRID_IMP_PROAPTIV_UP 0xa200 122 #define PRID_IMP_PROAPTIV_MP 0xa300 123 #define PRID_IMP_P6600 0xa400 124 #define PRID_IMP_M5150 0xa700 125 #define PRID_IMP_P5600 0xa800 126 #define PRID_IMP_I6400 0xa900 127 #define PRID_IMP_M6250 0xab00 128 #define PRID_IMP_I6500 0xb000 129 130 /* 131 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 132 */ 133 134 #define PRID_IMP_SB1 0x0100 135 #define PRID_IMP_SB1A 0x1100 136 137 /* 138 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT 139 */ 140 141 #define PRID_IMP_SR71000 0x0400 142 143 /* 144 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM 145 */ 146 147 #define PRID_IMP_BMIPS32_REV4 0x4000 148 #define PRID_IMP_BMIPS32_REV8 0x8000 149 #define PRID_IMP_BMIPS3300 0x9000 150 #define PRID_IMP_BMIPS3300_ALT 0x9100 151 #define PRID_IMP_BMIPS3300_BUG 0x0000 152 #define PRID_IMP_BMIPS43XX 0xa000 153 #define PRID_IMP_BMIPS5000 0x5a00 154 #define PRID_IMP_BMIPS5200 0x5b00 155 156 #define PRID_REV_BMIPS4380_LO 0x0040 157 #define PRID_REV_BMIPS4380_HI 0x006f 158 159 /* 160 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM 161 */ 162 163 #define PRID_IMP_CAVIUM_CN38XX 0x0000 164 #define PRID_IMP_CAVIUM_CN31XX 0x0100 165 #define PRID_IMP_CAVIUM_CN30XX 0x0200 166 #define PRID_IMP_CAVIUM_CN58XX 0x0300 167 #define PRID_IMP_CAVIUM_CN56XX 0x0400 168 #define PRID_IMP_CAVIUM_CN50XX 0x0600 169 #define PRID_IMP_CAVIUM_CN52XX 0x0700 170 #define PRID_IMP_CAVIUM_CN63XX 0x9000 171 #define PRID_IMP_CAVIUM_CN68XX 0x9100 172 #define PRID_IMP_CAVIUM_CN66XX 0x9200 173 #define PRID_IMP_CAVIUM_CN61XX 0x9300 174 #define PRID_IMP_CAVIUM_CNF71XX 0x9400 175 #define PRID_IMP_CAVIUM_CN78XX 0x9500 176 #define PRID_IMP_CAVIUM_CN70XX 0x9600 177 #define PRID_IMP_CAVIUM_CN73XX 0x9700 178 #define PRID_IMP_CAVIUM_CNF75XX 0x9800 179 180 /* 181 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_* 182 */ 183 184 #define PRID_IMP_JZRISC 0x0200 185 186 /* 187 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC 188 */ 189 #define PRID_IMP_NETLOGIC_XLR732 0x0000 190 #define PRID_IMP_NETLOGIC_XLR716 0x0200 191 #define PRID_IMP_NETLOGIC_XLR532 0x0900 192 #define PRID_IMP_NETLOGIC_XLR308 0x0600 193 #define PRID_IMP_NETLOGIC_XLR532C 0x0800 194 #define PRID_IMP_NETLOGIC_XLR516C 0x0a00 195 #define PRID_IMP_NETLOGIC_XLR508C 0x0b00 196 #define PRID_IMP_NETLOGIC_XLR308C 0x0f00 197 #define PRID_IMP_NETLOGIC_XLS608 0x8000 198 #define PRID_IMP_NETLOGIC_XLS408 0x8800 199 #define PRID_IMP_NETLOGIC_XLS404 0x8c00 200 #define PRID_IMP_NETLOGIC_XLS208 0x8e00 201 #define PRID_IMP_NETLOGIC_XLS204 0x8f00 202 #define PRID_IMP_NETLOGIC_XLS108 0xce00 203 #define PRID_IMP_NETLOGIC_XLS104 0xcf00 204 #define PRID_IMP_NETLOGIC_XLS616B 0x4000 205 #define PRID_IMP_NETLOGIC_XLS608B 0x4a00 206 #define PRID_IMP_NETLOGIC_XLS416B 0x4400 207 #define PRID_IMP_NETLOGIC_XLS412B 0x4c00 208 #define PRID_IMP_NETLOGIC_XLS408B 0x4e00 209 #define PRID_IMP_NETLOGIC_XLS404B 0x4f00 210 #define PRID_IMP_NETLOGIC_AU13XX 0x8000 211 212 #define PRID_IMP_NETLOGIC_XLP8XX 0x1000 213 #define PRID_IMP_NETLOGIC_XLP3XX 0x1100 214 #define PRID_IMP_NETLOGIC_XLP2XX 0x1200 215 #define PRID_IMP_NETLOGIC_XLP9XX 0x1500 216 #define PRID_IMP_NETLOGIC_XLP5XX 0x1300 217 218 /* 219 * Particular Revision values for bits 7:0 of the PRId register. 220 */ 221 222 #define PRID_REV_MASK 0x00ff 223 224 /* 225 * Definitions for 7:0 on legacy processors 226 */ 227 228 #define PRID_REV_TX4927 0x0022 229 #define PRID_REV_TX4937 0x0030 230 #define PRID_REV_R4400 0x0040 231 #define PRID_REV_R3000A 0x0030 232 #define PRID_REV_R3000 0x0020 233 #define PRID_REV_R2000A 0x0010 234 #define PRID_REV_TX3912 0x0010 235 #define PRID_REV_TX3922 0x0030 236 #define PRID_REV_TX3927 0x0040 237 #define PRID_REV_VR4111 0x0050 238 #define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ 239 #define PRID_REV_VR4121 0x0060 240 #define PRID_REV_VR4122 0x0070 241 #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 242 #define PRID_REV_VR4130 0x0080 243 #define PRID_REV_34K_V1_0_2 0x0022 244 #define PRID_REV_LOONGSON1B 0x0020 245 #define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */ 246 #define PRID_REV_LOONGSON2E 0x0002 247 #define PRID_REV_LOONGSON2F 0x0003 248 #define PRID_REV_LOONGSON3A_R1 0x0005 249 #define PRID_REV_LOONGSON3B_R1 0x0006 250 #define PRID_REV_LOONGSON3B_R2 0x0007 251 #define PRID_REV_LOONGSON3A_R2_0 0x0008 252 #define PRID_REV_LOONGSON3A_R3_0 0x0009 253 #define PRID_REV_LOONGSON3A_R2_1 0x000c 254 #define PRID_REV_LOONGSON3A_R3_1 0x000d 255 256 /* 257 * Older processors used to encode processor version and revision in two 258 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores 259 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as 260 * the patch number. *ARGH* 261 */ 262 #define PRID_REV_ENCODE_44(ver, rev) \ 263 ((ver) << 4 | (rev)) 264 #define PRID_REV_ENCODE_332(ver, rev, patch) \ 265 ((ver) << 5 | (rev) << 2 | (patch)) 266 267 /* 268 * FPU implementation/revision register (CP1 control register 0). 269 * 270 * +---------------------------------+----------------+----------------+ 271 * | 0 | Implementation | Revision | 272 * +---------------------------------+----------------+----------------+ 273 * 31 16 15 8 7 0 274 */ 275 276 #define FPIR_IMP_MASK 0xff00 277 278 #define FPIR_IMP_NONE 0x0000 279 280 #if !defined(__ASSEMBLY__) 281 282 enum cpu_type_enum { 283 CPU_UNKNOWN, 284 285 /* 286 * R2000 class processors 287 */ 288 CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, 289 CPU_R3081, CPU_R3081E, 290 291 /* 292 * R4000 class processors 293 */ 294 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, 295 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, 296 CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000, 297 CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, 298 CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, 299 CPU_SR71000, CPU_TX49XX, 300 301 /* 302 * R8000 class processors 303 */ 304 CPU_R8000, 305 306 /* 307 * TX3900 class processors 308 */ 309 CPU_TX3912, CPU_TX3922, CPU_TX3927, 310 311 /* 312 * MIPS32 class processors 313 */ 314 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 315 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 316 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, 317 CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, 318 CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250, 319 320 /* 321 * MIPS64 class processors 322 */ 323 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 324 CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, 325 CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500, 326 327 CPU_QEMU_GENERIC, 328 329 CPU_LAST 330 }; 331 332 #endif /* !__ASSEMBLY */ 333 334 /* 335 * ISA Level encodings 336 * 337 */ 338 #define MIPS_CPU_ISA_II 0x00000001 339 #define MIPS_CPU_ISA_III 0x00000002 340 #define MIPS_CPU_ISA_IV 0x00000004 341 #define MIPS_CPU_ISA_V 0x00000008 342 #define MIPS_CPU_ISA_M32R1 0x00000010 343 #define MIPS_CPU_ISA_M32R2 0x00000020 344 #define MIPS_CPU_ISA_M64R1 0x00000040 345 #define MIPS_CPU_ISA_M64R2 0x00000080 346 #define MIPS_CPU_ISA_M32R6 0x00000100 347 #define MIPS_CPU_ISA_M64R6 0x00000200 348 349 #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \ 350 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6) 351 #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ 352 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \ 353 MIPS_CPU_ISA_M64R6) 354 355 /* 356 * Private version of BIT_ULL() to escape include file recursion hell. 357 * We soon will have to switch to another mechanism that will work with 358 * more than 64 bits anyway. 359 */ 360 #define MBIT_ULL(bit) (1ULL << (bit)) 361 362 /* 363 * CPU Option encodings 364 */ 365 #define MIPS_CPU_TLB MBIT_ULL( 0) /* CPU has TLB */ 366 #define MIPS_CPU_4KEX MBIT_ULL( 1) /* "R4K" exception model */ 367 #define MIPS_CPU_3K_CACHE MBIT_ULL( 2) /* R3000-style caches */ 368 #define MIPS_CPU_4K_CACHE MBIT_ULL( 3) /* R4000-style caches */ 369 #define MIPS_CPU_TX39_CACHE MBIT_ULL( 4) /* TX3900-style caches */ 370 #define MIPS_CPU_FPU MBIT_ULL( 5) /* CPU has FPU */ 371 #define MIPS_CPU_32FPR MBIT_ULL( 6) /* 32 dbl. prec. FP registers */ 372 #define MIPS_CPU_COUNTER MBIT_ULL( 7) /* Cycle count/compare */ 373 #define MIPS_CPU_WATCH MBIT_ULL( 8) /* watchpoint registers */ 374 #define MIPS_CPU_DIVEC MBIT_ULL( 9) /* dedicated interrupt vector */ 375 #define MIPS_CPU_VCE MBIT_ULL(10) /* virt. coherence conflict possible */ 376 #define MIPS_CPU_CACHE_CDEX_P MBIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */ 377 #define MIPS_CPU_CACHE_CDEX_S MBIT_ULL(12) /* ... same for seconary cache ... */ 378 #define MIPS_CPU_MCHECK MBIT_ULL(13) /* Machine check exception */ 379 #define MIPS_CPU_EJTAG MBIT_ULL(14) /* EJTAG exception */ 380 #define MIPS_CPU_NOFPUEX MBIT_ULL(15) /* no FPU exception */ 381 #define MIPS_CPU_LLSC MBIT_ULL(16) /* CPU has ll/sc instructions */ 382 #define MIPS_CPU_INCLUSIVE_CACHES MBIT_ULL(17) /* P-cache subset enforced */ 383 #define MIPS_CPU_PREFETCH MBIT_ULL(18) /* CPU has usable prefetch */ 384 #define MIPS_CPU_VINT MBIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */ 385 #define MIPS_CPU_VEIC MBIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */ 386 #define MIPS_CPU_ULRI MBIT_ULL(21) /* CPU has ULRI feature */ 387 #define MIPS_CPU_PCI MBIT_ULL(22) /* CPU has Perf Ctr Int indicator */ 388 #define MIPS_CPU_RIXI MBIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */ 389 #define MIPS_CPU_MICROMIPS MBIT_ULL(24) /* CPU has microMIPS capability */ 390 #define MIPS_CPU_TLBINV MBIT_ULL(25) /* CPU supports TLBINV/F */ 391 #define MIPS_CPU_SEGMENTS MBIT_ULL(26) /* CPU supports Segmentation Control registers */ 392 #define MIPS_CPU_EVA MBIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */ 393 #define MIPS_CPU_HTW MBIT_ULL(28) /* CPU support Hardware Page Table Walker */ 394 #define MIPS_CPU_RIXIEX MBIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */ 395 #define MIPS_CPU_MAAR MBIT_ULL(30) /* MAAR(I) registers are present */ 396 #define MIPS_CPU_FRE MBIT_ULL(31) /* FRE & UFE bits implemented */ 397 #define MIPS_CPU_RW_LLB MBIT_ULL(32) /* LLADDR/LLB writes are allowed */ 398 #define MIPS_CPU_LPA MBIT_ULL(33) /* CPU supports Large Physical Addressing */ 399 #define MIPS_CPU_CDMM MBIT_ULL(34) /* CPU has Common Device Memory Map */ 400 #define MIPS_CPU_BP_GHIST MBIT_ULL(35) /* R12K+ Branch Prediction Global History */ 401 #define MIPS_CPU_SP MBIT_ULL(36) /* Small (1KB) page support */ 402 #define MIPS_CPU_FTLB MBIT_ULL(37) /* CPU has Fixed-page-size TLB */ 403 #define MIPS_CPU_NAN_LEGACY MBIT_ULL(38) /* Legacy NaN implemented */ 404 #define MIPS_CPU_NAN_2008 MBIT_ULL(39) /* 2008 NaN implemented */ 405 #define MIPS_CPU_VP MBIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */ 406 #define MIPS_CPU_LDPTE MBIT_ULL(41) /* CPU has ldpte/lddir instructions */ 407 #define MIPS_CPU_MVH MBIT_ULL(42) /* CPU supports MFHC0/MTHC0 */ 408 #define MIPS_CPU_EBASE_WG MBIT_ULL(43) /* CPU has EBase.WG */ 409 #define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */ 410 #define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */ 411 #define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */ 412 #define MIPS_CPU_PERF MBIT_ULL(47) /* CPU has MIPS performance counters */ 413 #define MIPS_CPU_GUESTCTL0EXT MBIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */ 414 #define MIPS_CPU_GUESTCTL1 MBIT_ULL(49) /* CPU has VZ GuestCtl1 register */ 415 #define MIPS_CPU_GUESTCTL2 MBIT_ULL(50) /* CPU has VZ GuestCtl2 register */ 416 #define MIPS_CPU_GUESTID MBIT_ULL(51) /* CPU uses VZ ASE GuestID feature */ 417 #define MIPS_CPU_DRG MBIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */ 418 #define MIPS_CPU_UFR MBIT_ULL(53) /* CPU supports User mode FR switching */ 419 #define MIPS_CPU_SHARED_FTLB_RAM \ 420 MBIT_ULL(54) /* CPU shares FTLB RAM with another */ 421 #define MIPS_CPU_SHARED_FTLB_ENTRIES \ 422 MBIT_ULL(55) /* CPU shares FTLB entries with another */ 423 #define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \ 424 MBIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */ 425 #define MIPS_CPU_MMID MBIT_ULL(57) /* CPU supports MemoryMapIDs */ 426 427 /* 428 * CPU ASE encodings 429 */ 430 #define MIPS_ASE_MIPS16 0x00000001 /* code compression */ 431 #define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ 432 #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ 433 #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ 434 #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ 435 #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ 436 #define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ 437 #define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */ 438 #define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */ 439 #define MIPS_ASE_DSP3 0x00000200 /* Signal Processing ASE Rev 3*/ 440 #define MIPS_ASE_MIPS16E2 0x00000400 /* MIPS16e2 */ 441 442 #endif /* _ASM_CPU_H */ 443