1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 Waldorf GMBH 7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle 8 * Copyright (C) 1996 Paul M. Antoine 9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 10 * Copyright (C) 2004 Maciej W. Rozycki 11 */ 12 #ifndef __ASM_CPU_INFO_H 13 #define __ASM_CPU_INFO_H 14 15 #include <linux/types.h> 16 17 #include <asm/cache.h> 18 19 /* 20 * Descriptor for a cache 21 */ 22 struct cache_desc { 23 unsigned int waysize; /* Bytes per way */ 24 unsigned short sets; /* Number of lines per set */ 25 unsigned char ways; /* Number of ways */ 26 unsigned char linesz; /* Size of line in bytes */ 27 unsigned char waybit; /* Bits to select in a cache set */ 28 unsigned char flags; /* Flags describing cache properties */ 29 }; 30 31 struct guest_info { 32 unsigned long ases; 33 unsigned long ases_dyn; 34 unsigned long long options; 35 unsigned long long options_dyn; 36 int tlbsize; 37 u8 conf; 38 u8 kscratch_mask; 39 }; 40 41 /* 42 * Flag definitions 43 */ 44 #define MIPS_CACHE_NOT_PRESENT 0x00000001 45 #define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */ 46 #define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */ 47 #define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */ 48 #define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */ 49 #define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */ 50 51 struct cpuinfo_mips { 52 unsigned long asid_cache; 53 #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE 54 unsigned long asid_mask; 55 #endif 56 57 /* 58 * Capability and feature descriptor structure for MIPS CPU 59 */ 60 unsigned long ases; 61 unsigned long long options; 62 unsigned int udelay_val; 63 unsigned int processor_id; 64 unsigned int fpu_id; 65 unsigned int fpu_csr31; 66 unsigned int fpu_msk31; 67 unsigned int msa_id; 68 unsigned int cputype; 69 int isa_level; 70 int tlbsize; 71 int tlbsizevtlb; 72 int tlbsizeftlbsets; 73 int tlbsizeftlbways; 74 struct cache_desc icache; /* Primary I-cache */ 75 struct cache_desc dcache; /* Primary D or combined I/D cache */ 76 struct cache_desc vcache; /* Victim cache, between pcache and scache */ 77 struct cache_desc scache; /* Secondary cache */ 78 struct cache_desc tcache; /* Tertiary/split secondary cache */ 79 int srsets; /* Shadow register sets */ 80 int package;/* physical package number */ 81 int core; /* physical core number */ 82 #ifdef CONFIG_64BIT 83 int vmbits; /* Virtual memory size in bits */ 84 #endif 85 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6) 86 /* 87 * There is not necessarily a 1:1 mapping of VPE num to CPU number 88 * in particular on multi-core systems. 89 */ 90 int vpe_id; /* Virtual Processor number */ 91 #endif 92 void *data; /* Additional data */ 93 unsigned int watch_reg_count; /* Number that exist */ 94 unsigned int watch_reg_use_cnt; /* Usable by ptrace */ 95 #define NUM_WATCH_REGS 4 96 u16 watch_reg_masks[NUM_WATCH_REGS]; 97 unsigned int kscratch_mask; /* Usable KScratch mask. */ 98 /* 99 * Cache Coherency attribute for write-combine memory writes. 100 * (shifted by _CACHE_SHIFT) 101 */ 102 unsigned int writecombine; 103 /* 104 * Simple counter to prevent enabling HTW in nested 105 * htw_start/htw_stop calls 106 */ 107 unsigned int htw_seq; 108 109 /* VZ & Guest features */ 110 struct guest_info guest; 111 unsigned int gtoffset_mask; 112 unsigned int guestid_mask; 113 unsigned int guestid_cache; 114 } __attribute__((aligned(SMP_CACHE_BYTES))); 115 116 extern struct cpuinfo_mips cpu_data[]; 117 #define current_cpu_data cpu_data[smp_processor_id()] 118 #define raw_current_cpu_data cpu_data[raw_smp_processor_id()] 119 #define boot_cpu_data cpu_data[0] 120 121 extern void cpu_probe(void); 122 extern void cpu_report(void); 123 124 extern const char *__cpu_name[]; 125 #define cpu_name_string() __cpu_name[raw_smp_processor_id()] 126 127 struct seq_file; 128 struct notifier_block; 129 130 extern int register_proc_cpuinfo_notifier(struct notifier_block *nb); 131 extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v); 132 133 #define proc_cpuinfo_notifier(fn, pri) \ 134 ({ \ 135 static struct notifier_block fn##_nb = { \ 136 .notifier_call = fn, \ 137 .priority = pri \ 138 }; \ 139 \ 140 register_proc_cpuinfo_notifier(&fn##_nb); \ 141 }) 142 143 struct proc_cpuinfo_notifier_args { 144 struct seq_file *m; 145 unsigned long n; 146 }; 147 148 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6) 149 # define cpu_vpe_id(cpuinfo) ((cpuinfo)->vpe_id) 150 #else 151 # define cpu_vpe_id(cpuinfo) ({ (void)cpuinfo; 0; }) 152 #endif 153 154 static inline unsigned long cpu_asid_inc(void) 155 { 156 return 1 << CONFIG_MIPS_ASID_SHIFT; 157 } 158 159 static inline unsigned long cpu_asid_mask(struct cpuinfo_mips *cpuinfo) 160 { 161 #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE 162 return cpuinfo->asid_mask; 163 #endif 164 return ((1 << CONFIG_MIPS_ASID_BITS) - 1) << CONFIG_MIPS_ASID_SHIFT; 165 } 166 167 static inline void set_cpu_asid_mask(struct cpuinfo_mips *cpuinfo, 168 unsigned long asid_mask) 169 { 170 #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE 171 cpuinfo->asid_mask = asid_mask; 172 #endif 173 } 174 175 #endif /* __ASM_CPU_INFO_H */ 176