1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 2004 Ralf Baechle 7 * Copyright (C) 2004 Maciej W. Rozycki 8 */ 9 #ifndef __ASM_CPU_FEATURES_H 10 #define __ASM_CPU_FEATURES_H 11 12 #include <asm/cpu.h> 13 #include <asm/cpu-info.h> 14 #include <cpu-feature-overrides.h> 15 16 /* 17 * SMP assumption: Options of CPU 0 are a superset of all processors. 18 * This is true for all known MIPS systems. 19 */ 20 #ifndef cpu_has_tlb 21 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) 22 #endif 23 #ifndef cpu_has_ftlb 24 #define cpu_has_ftlb (cpu_data[0].options & MIPS_CPU_FTLB) 25 #endif 26 #ifndef cpu_has_tlbinv 27 #define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV) 28 #endif 29 #ifndef cpu_has_segments 30 #define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS) 31 #endif 32 #ifndef cpu_has_eva 33 #define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA) 34 #endif 35 #ifndef cpu_has_htw 36 #define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW) 37 #endif 38 #ifndef cpu_has_ldpte 39 #define cpu_has_ldpte (cpu_data[0].options & MIPS_CPU_LDPTE) 40 #endif 41 #ifndef cpu_has_rixiex 42 #define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX) 43 #endif 44 #ifndef cpu_has_maar 45 #define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR) 46 #endif 47 #ifndef cpu_has_rw_llb 48 #define cpu_has_rw_llb (cpu_data[0].options & MIPS_CPU_RW_LLB) 49 #endif 50 51 /* 52 * For the moment we don't consider R6000 and R8000 so we can assume that 53 * anything that doesn't support R4000-style exceptions and interrupts is 54 * R3000-like. Users should still treat these two macro definitions as 55 * opaque. 56 */ 57 #ifndef cpu_has_3kex 58 #define cpu_has_3kex (!cpu_has_4kex) 59 #endif 60 #ifndef cpu_has_4kex 61 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) 62 #endif 63 #ifndef cpu_has_3k_cache 64 #define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE) 65 #endif 66 #define cpu_has_6k_cache 0 67 #define cpu_has_8k_cache 0 68 #ifndef cpu_has_4k_cache 69 #define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE) 70 #endif 71 #ifndef cpu_has_tx39_cache 72 #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) 73 #endif 74 #ifndef cpu_has_octeon_cache 75 #define cpu_has_octeon_cache 0 76 #endif 77 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ 78 #ifndef cpu_has_fpu 79 #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 80 #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 81 #else 82 #define raw_cpu_has_fpu cpu_has_fpu 83 #endif 84 #ifndef cpu_has_32fpr 85 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) 86 #endif 87 #ifndef cpu_has_counter 88 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) 89 #endif 90 #ifndef cpu_has_watch 91 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) 92 #endif 93 #ifndef cpu_has_divec 94 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) 95 #endif 96 #ifndef cpu_has_vce 97 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) 98 #endif 99 #ifndef cpu_has_cache_cdex_p 100 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P) 101 #endif 102 #ifndef cpu_has_cache_cdex_s 103 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S) 104 #endif 105 #ifndef cpu_has_prefetch 106 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH) 107 #endif 108 #ifndef cpu_has_mcheck 109 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) 110 #endif 111 #ifndef cpu_has_ejtag 112 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) 113 #endif 114 #ifndef cpu_has_llsc 115 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) 116 #endif 117 #ifndef cpu_has_bp_ghist 118 #define cpu_has_bp_ghist (cpu_data[0].options & MIPS_CPU_BP_GHIST) 119 #endif 120 #ifndef kernel_uses_llsc 121 #define kernel_uses_llsc cpu_has_llsc 122 #endif 123 #ifndef cpu_has_guestctl0ext 124 #define cpu_has_guestctl0ext (cpu_data[0].options & MIPS_CPU_GUESTCTL0EXT) 125 #endif 126 #ifndef cpu_has_guestctl1 127 #define cpu_has_guestctl1 (cpu_data[0].options & MIPS_CPU_GUESTCTL1) 128 #endif 129 #ifndef cpu_has_guestctl2 130 #define cpu_has_guestctl2 (cpu_data[0].options & MIPS_CPU_GUESTCTL2) 131 #endif 132 #ifndef cpu_has_guestid 133 #define cpu_has_guestid (cpu_data[0].options & MIPS_CPU_GUESTID) 134 #endif 135 #ifndef cpu_has_drg 136 #define cpu_has_drg (cpu_data[0].options & MIPS_CPU_DRG) 137 #endif 138 #ifndef cpu_has_mips16 139 #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) 140 #endif 141 #ifndef cpu_has_mdmx 142 #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) 143 #endif 144 #ifndef cpu_has_mips3d 145 #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) 146 #endif 147 #ifndef cpu_has_smartmips 148 #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) 149 #endif 150 151 #ifndef cpu_has_rixi 152 #define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) 153 #endif 154 155 #ifndef cpu_has_mmips 156 # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS 157 # define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) 158 # else 159 # define cpu_has_mmips 0 160 # endif 161 #endif 162 163 #ifndef cpu_has_lpa 164 #define cpu_has_lpa (cpu_data[0].options & MIPS_CPU_LPA) 165 #endif 166 #ifndef cpu_has_mvh 167 #define cpu_has_mvh (cpu_data[0].options & MIPS_CPU_MVH) 168 #endif 169 #ifndef cpu_has_xpa 170 #define cpu_has_xpa (cpu_has_lpa && cpu_has_mvh) 171 #endif 172 #ifndef cpu_has_vtag_icache 173 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 174 #endif 175 #ifndef cpu_has_dc_aliases 176 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) 177 #endif 178 #ifndef cpu_has_ic_fills_f_dc 179 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 180 #endif 181 #ifndef cpu_has_pindexed_dcache 182 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 183 #endif 184 #ifndef cpu_has_local_ebase 185 #define cpu_has_local_ebase 1 186 #endif 187 188 /* 189 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 190 * such as the R10000 have I-Caches that snoop local stores; the embedded ones 191 * don't. For maintaining I-cache coherency this means we need to flush the 192 * D-cache all the way back to whever the I-cache does refills from, so the 193 * I-cache has a chance to see the new data at all. Then we have to flush the 194 * I-cache also. 195 * Note we may have been rescheduled and may no longer be running on the CPU 196 * that did the store so we can't optimize this into only doing the flush on 197 * the local CPU. 198 */ 199 #ifndef cpu_icache_snoops_remote_store 200 #ifdef CONFIG_SMP 201 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) 202 #else 203 #define cpu_icache_snoops_remote_store 1 204 #endif 205 #endif 206 207 #ifndef cpu_has_mips_1 208 # define cpu_has_mips_1 (!cpu_has_mips_r6) 209 #endif 210 #ifndef cpu_has_mips_2 211 # define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) 212 #endif 213 #ifndef cpu_has_mips_3 214 # define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III) 215 #endif 216 #ifndef cpu_has_mips_4 217 # define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV) 218 #endif 219 #ifndef cpu_has_mips_5 220 # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) 221 #endif 222 #ifndef cpu_has_mips32r1 223 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) 224 #endif 225 #ifndef cpu_has_mips32r2 226 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 227 #endif 228 #ifndef cpu_has_mips32r6 229 # define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6) 230 #endif 231 #ifndef cpu_has_mips64r1 232 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 233 #endif 234 #ifndef cpu_has_mips64r2 235 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 236 #endif 237 #ifndef cpu_has_mips64r6 238 # define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6) 239 #endif 240 241 /* 242 * Shortcuts ... 243 */ 244 #define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5) 245 #define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5) 246 #define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5) 247 248 #define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r) 249 #define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r) 250 #define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r) 251 #define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r) 252 253 #define cpu_has_mips_3_4_5_64_r2_r6 \ 254 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6) 255 #define cpu_has_mips_4_5_64_r2_r6 \ 256 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \ 257 cpu_has_mips_r2 | cpu_has_mips_r6) 258 259 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6) 260 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6) 261 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 262 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 263 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6) 264 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 265 cpu_has_mips32r6 | cpu_has_mips64r1 | \ 266 cpu_has_mips64r2 | cpu_has_mips64r6) 267 268 /* MIPSR2 and MIPSR6 have a lot of similarities */ 269 #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6) 270 271 /* 272 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor 273 * 274 * Returns non-zero value if the current processor implementation requires 275 * an IHB instruction to deal with an instruction hazard as per MIPS R2 276 * architecture specification, zero otherwise. 277 */ 278 #ifndef cpu_has_mips_r2_exec_hazard 279 #define cpu_has_mips_r2_exec_hazard \ 280 ({ \ 281 int __res; \ 282 \ 283 switch (current_cpu_type()) { \ 284 case CPU_M14KC: \ 285 case CPU_74K: \ 286 case CPU_1074K: \ 287 case CPU_PROAPTIV: \ 288 case CPU_P5600: \ 289 case CPU_M5150: \ 290 case CPU_QEMU_GENERIC: \ 291 case CPU_CAVIUM_OCTEON: \ 292 case CPU_CAVIUM_OCTEON_PLUS: \ 293 case CPU_CAVIUM_OCTEON2: \ 294 case CPU_CAVIUM_OCTEON3: \ 295 __res = 0; \ 296 break; \ 297 \ 298 default: \ 299 __res = 1; \ 300 } \ 301 \ 302 __res; \ 303 }) 304 #endif 305 306 /* 307 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 308 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and 309 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 310 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 311 */ 312 #ifndef cpu_has_clo_clz 313 #define cpu_has_clo_clz cpu_has_mips_r 314 #endif 315 316 /* 317 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH. 318 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD. 319 * This indicates the availability of WSBH and in case of 64 bit CPUs also 320 * DSBH and DSHD. 321 */ 322 #ifndef cpu_has_wsbh 323 #define cpu_has_wsbh cpu_has_mips_r2 324 #endif 325 326 #ifndef cpu_has_dsp 327 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 328 #endif 329 330 #ifndef cpu_has_dsp2 331 #define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P) 332 #endif 333 334 #ifndef cpu_has_dsp3 335 #define cpu_has_dsp3 (cpu_data[0].ases & MIPS_ASE_DSP3) 336 #endif 337 338 #ifndef cpu_has_mipsmt 339 #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) 340 #endif 341 342 #ifndef cpu_has_vp 343 #define cpu_has_vp (cpu_data[0].options & MIPS_CPU_VP) 344 #endif 345 346 #ifndef cpu_has_userlocal 347 #define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI) 348 #endif 349 350 #ifdef CONFIG_32BIT 351 # ifndef cpu_has_nofpuex 352 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) 353 # endif 354 # ifndef cpu_has_64bits 355 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 356 # endif 357 # ifndef cpu_has_64bit_zero_reg 358 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 359 # endif 360 # ifndef cpu_has_64bit_gp_regs 361 # define cpu_has_64bit_gp_regs 0 362 # endif 363 # ifndef cpu_has_64bit_addresses 364 # define cpu_has_64bit_addresses 0 365 # endif 366 # ifndef cpu_vmbits 367 # define cpu_vmbits 31 368 # endif 369 #endif 370 371 #ifdef CONFIG_64BIT 372 # ifndef cpu_has_nofpuex 373 # define cpu_has_nofpuex 0 374 # endif 375 # ifndef cpu_has_64bits 376 # define cpu_has_64bits 1 377 # endif 378 # ifndef cpu_has_64bit_zero_reg 379 # define cpu_has_64bit_zero_reg 1 380 # endif 381 # ifndef cpu_has_64bit_gp_regs 382 # define cpu_has_64bit_gp_regs 1 383 # endif 384 # ifndef cpu_has_64bit_addresses 385 # define cpu_has_64bit_addresses 1 386 # endif 387 # ifndef cpu_vmbits 388 # define cpu_vmbits cpu_data[0].vmbits 389 # define __NEED_VMBITS_PROBE 390 # endif 391 #endif 392 393 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 394 # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) 395 #elif !defined(cpu_has_vint) 396 # define cpu_has_vint 0 397 #endif 398 399 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 400 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) 401 #elif !defined(cpu_has_veic) 402 # define cpu_has_veic 0 403 #endif 404 405 #ifndef cpu_has_inclusive_pcaches 406 #define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES) 407 #endif 408 409 #ifndef cpu_dcache_line_size 410 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz 411 #endif 412 #ifndef cpu_icache_line_size 413 #define cpu_icache_line_size() cpu_data[0].icache.linesz 414 #endif 415 #ifndef cpu_scache_line_size 416 #define cpu_scache_line_size() cpu_data[0].scache.linesz 417 #endif 418 419 #ifndef cpu_hwrena_impl_bits 420 #define cpu_hwrena_impl_bits 0 421 #endif 422 423 #ifndef cpu_has_perf_cntr_intr_bit 424 #define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI) 425 #endif 426 427 #ifndef cpu_has_vz 428 #define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ) 429 #endif 430 431 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa) 432 # define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA) 433 #elif !defined(cpu_has_msa) 434 # define cpu_has_msa 0 435 #endif 436 437 #ifndef cpu_has_fre 438 # define cpu_has_fre (cpu_data[0].options & MIPS_CPU_FRE) 439 #endif 440 441 #ifndef cpu_has_cdmm 442 # define cpu_has_cdmm (cpu_data[0].options & MIPS_CPU_CDMM) 443 #endif 444 445 #ifndef cpu_has_small_pages 446 # define cpu_has_small_pages (cpu_data[0].options & MIPS_CPU_SP) 447 #endif 448 449 #ifndef cpu_has_nan_legacy 450 #define cpu_has_nan_legacy (cpu_data[0].options & MIPS_CPU_NAN_LEGACY) 451 #endif 452 #ifndef cpu_has_nan_2008 453 #define cpu_has_nan_2008 (cpu_data[0].options & MIPS_CPU_NAN_2008) 454 #endif 455 456 #ifndef cpu_has_ebase_wg 457 # define cpu_has_ebase_wg (cpu_data[0].options & MIPS_CPU_EBASE_WG) 458 #endif 459 460 #ifndef cpu_has_badinstr 461 # define cpu_has_badinstr (cpu_data[0].options & MIPS_CPU_BADINSTR) 462 #endif 463 464 #ifndef cpu_has_badinstrp 465 # define cpu_has_badinstrp (cpu_data[0].options & MIPS_CPU_BADINSTRP) 466 #endif 467 468 #ifndef cpu_has_contextconfig 469 # define cpu_has_contextconfig (cpu_data[0].options & MIPS_CPU_CTXTC) 470 #endif 471 472 #ifndef cpu_has_perf 473 # define cpu_has_perf (cpu_data[0].options & MIPS_CPU_PERF) 474 #endif 475 476 /* 477 * Guest capabilities 478 */ 479 #ifndef cpu_guest_has_conf1 480 #define cpu_guest_has_conf1 (cpu_data[0].guest.conf & (1 << 1)) 481 #endif 482 #ifndef cpu_guest_has_conf2 483 #define cpu_guest_has_conf2 (cpu_data[0].guest.conf & (1 << 2)) 484 #endif 485 #ifndef cpu_guest_has_conf3 486 #define cpu_guest_has_conf3 (cpu_data[0].guest.conf & (1 << 3)) 487 #endif 488 #ifndef cpu_guest_has_conf4 489 #define cpu_guest_has_conf4 (cpu_data[0].guest.conf & (1 << 4)) 490 #endif 491 #ifndef cpu_guest_has_conf5 492 #define cpu_guest_has_conf5 (cpu_data[0].guest.conf & (1 << 5)) 493 #endif 494 #ifndef cpu_guest_has_conf6 495 #define cpu_guest_has_conf6 (cpu_data[0].guest.conf & (1 << 6)) 496 #endif 497 #ifndef cpu_guest_has_conf7 498 #define cpu_guest_has_conf7 (cpu_data[0].guest.conf & (1 << 7)) 499 #endif 500 #ifndef cpu_guest_has_fpu 501 #define cpu_guest_has_fpu (cpu_data[0].guest.options & MIPS_CPU_FPU) 502 #endif 503 #ifndef cpu_guest_has_watch 504 #define cpu_guest_has_watch (cpu_data[0].guest.options & MIPS_CPU_WATCH) 505 #endif 506 #ifndef cpu_guest_has_contextconfig 507 #define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC) 508 #endif 509 #ifndef cpu_guest_has_segments 510 #define cpu_guest_has_segments (cpu_data[0].guest.options & MIPS_CPU_SEGMENTS) 511 #endif 512 #ifndef cpu_guest_has_badinstr 513 #define cpu_guest_has_badinstr (cpu_data[0].guest.options & MIPS_CPU_BADINSTR) 514 #endif 515 #ifndef cpu_guest_has_badinstrp 516 #define cpu_guest_has_badinstrp (cpu_data[0].guest.options & MIPS_CPU_BADINSTRP) 517 #endif 518 #ifndef cpu_guest_has_htw 519 #define cpu_guest_has_htw (cpu_data[0].guest.options & MIPS_CPU_HTW) 520 #endif 521 #ifndef cpu_guest_has_msa 522 #define cpu_guest_has_msa (cpu_data[0].guest.ases & MIPS_ASE_MSA) 523 #endif 524 #ifndef cpu_guest_has_kscr 525 #define cpu_guest_has_kscr(n) (cpu_data[0].guest.kscratch_mask & (1u << (n))) 526 #endif 527 #ifndef cpu_guest_has_rw_llb 528 #define cpu_guest_has_rw_llb (cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB)) 529 #endif 530 #ifndef cpu_guest_has_perf 531 #define cpu_guest_has_perf (cpu_data[0].guest.options & MIPS_CPU_PERF) 532 #endif 533 #ifndef cpu_guest_has_maar 534 #define cpu_guest_has_maar (cpu_data[0].guest.options & MIPS_CPU_MAAR) 535 #endif 536 537 /* 538 * Guest dynamic capabilities 539 */ 540 #ifndef cpu_guest_has_dyn_fpu 541 #define cpu_guest_has_dyn_fpu (cpu_data[0].guest.options_dyn & MIPS_CPU_FPU) 542 #endif 543 #ifndef cpu_guest_has_dyn_watch 544 #define cpu_guest_has_dyn_watch (cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH) 545 #endif 546 #ifndef cpu_guest_has_dyn_contextconfig 547 #define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC) 548 #endif 549 #ifndef cpu_guest_has_dyn_perf 550 #define cpu_guest_has_dyn_perf (cpu_data[0].guest.options_dyn & MIPS_CPU_PERF) 551 #endif 552 #ifndef cpu_guest_has_dyn_msa 553 #define cpu_guest_has_dyn_msa (cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA) 554 #endif 555 #ifndef cpu_guest_has_dyn_maar 556 #define cpu_guest_has_dyn_maar (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR) 557 #endif 558 559 #endif /* __ASM_CPU_FEATURES_H */ 560