1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 2004 Ralf Baechle 7 * Copyright (C) 2004 Maciej W. Rozycki 8 */ 9 #ifndef __ASM_CPU_FEATURES_H 10 #define __ASM_CPU_FEATURES_H 11 12 #include <asm/cpu.h> 13 #include <asm/cpu-info.h> 14 #include <asm/isa-rev.h> 15 #include <cpu-feature-overrides.h> 16 17 #define __ase(ase) (cpu_data[0].ases & (ase)) 18 #define __opt(opt) (cpu_data[0].options & (opt)) 19 20 /* 21 * Check if MIPS_ISA_REV is >= isa *and* an option or ASE is detected during 22 * boot (typically by cpu_probe()). 23 * 24 * Note that these should only be used in cases where a kernel built for an 25 * older ISA *cannot* run on a CPU which supports the feature in question. For 26 * example this may be used for features introduced with MIPSr6, since a kernel 27 * built for an older ISA cannot run on a MIPSr6 CPU. This should not be used 28 * for MIPSr2 features however, since a MIPSr1 or earlier kernel might run on a 29 * MIPSr2 CPU. 30 */ 31 #define __isa_ge_and_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) && __ase(ase)) 32 #define __isa_ge_and_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) && __opt(opt)) 33 34 /* 35 * Check if MIPS_ISA_REV is >= isa *or* an option or ASE is detected during 36 * boot (typically by cpu_probe()). 37 * 38 * These are for use with features that are optional up until a particular ISA 39 * revision & then become required. 40 */ 41 #define __isa_ge_or_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) || __ase(ase)) 42 #define __isa_ge_or_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) || __opt(opt)) 43 44 /* 45 * Check if MIPS_ISA_REV is < isa *and* an option or ASE is detected during 46 * boot (typically by cpu_probe()). 47 * 48 * These are for use with features that are optional up until a particular ISA 49 * revision & are then removed - ie. no longer present in any CPU implementing 50 * the given ISA revision. 51 */ 52 #define __isa_lt_and_ase(isa, ase) ((MIPS_ISA_REV < (isa)) && __ase(ase)) 53 #define __isa_lt_and_opt(isa, opt) ((MIPS_ISA_REV < (isa)) && __opt(opt)) 54 55 /* 56 * SMP assumption: Options of CPU 0 are a superset of all processors. 57 * This is true for all known MIPS systems. 58 */ 59 #ifndef cpu_has_tlb 60 #define cpu_has_tlb __opt(MIPS_CPU_TLB) 61 #endif 62 #ifndef cpu_has_ftlb 63 #define cpu_has_ftlb __opt(MIPS_CPU_FTLB) 64 #endif 65 #ifndef cpu_has_tlbinv 66 #define cpu_has_tlbinv __opt(MIPS_CPU_TLBINV) 67 #endif 68 #ifndef cpu_has_segments 69 #define cpu_has_segments __opt(MIPS_CPU_SEGMENTS) 70 #endif 71 #ifndef cpu_has_eva 72 #define cpu_has_eva __opt(MIPS_CPU_EVA) 73 #endif 74 #ifndef cpu_has_htw 75 #define cpu_has_htw __opt(MIPS_CPU_HTW) 76 #endif 77 #ifndef cpu_has_ldpte 78 #define cpu_has_ldpte __opt(MIPS_CPU_LDPTE) 79 #endif 80 #ifndef cpu_has_rixiex 81 #define cpu_has_rixiex __isa_ge_or_opt(6, MIPS_CPU_RIXIEX) 82 #endif 83 #ifndef cpu_has_maar 84 #define cpu_has_maar __opt(MIPS_CPU_MAAR) 85 #endif 86 #ifndef cpu_has_rw_llb 87 #define cpu_has_rw_llb __isa_ge_or_opt(6, MIPS_CPU_RW_LLB) 88 #endif 89 90 /* 91 * For the moment we don't consider R6000 and R8000 so we can assume that 92 * anything that doesn't support R4000-style exceptions and interrupts is 93 * R3000-like. Users should still treat these two macro definitions as 94 * opaque. 95 */ 96 #ifndef cpu_has_3kex 97 #define cpu_has_3kex (!cpu_has_4kex) 98 #endif 99 #ifndef cpu_has_4kex 100 #define cpu_has_4kex __isa_ge_or_opt(1, MIPS_CPU_4KEX) 101 #endif 102 #ifndef cpu_has_3k_cache 103 #define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE) 104 #endif 105 #define cpu_has_6k_cache 0 106 #define cpu_has_8k_cache 0 107 #ifndef cpu_has_4k_cache 108 #define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE) 109 #endif 110 #ifndef cpu_has_tx39_cache 111 #define cpu_has_tx39_cache __opt(MIPS_CPU_TX39_CACHE) 112 #endif 113 #ifndef cpu_has_octeon_cache 114 #define cpu_has_octeon_cache 0 115 #endif 116 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ 117 #ifndef cpu_has_fpu 118 # ifdef CONFIG_MIPS_FP_SUPPORT 119 # define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 120 # define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 121 # else 122 # define cpu_has_fpu 0 123 # define raw_cpu_has_fpu 0 124 # endif 125 #else 126 # define raw_cpu_has_fpu cpu_has_fpu 127 #endif 128 #ifndef cpu_has_32fpr 129 #define cpu_has_32fpr __isa_ge_or_opt(1, MIPS_CPU_32FPR) 130 #endif 131 #ifndef cpu_has_counter 132 #define cpu_has_counter __opt(MIPS_CPU_COUNTER) 133 #endif 134 #ifndef cpu_has_watch 135 #define cpu_has_watch __opt(MIPS_CPU_WATCH) 136 #endif 137 #ifndef cpu_has_divec 138 #define cpu_has_divec __isa_ge_or_opt(1, MIPS_CPU_DIVEC) 139 #endif 140 #ifndef cpu_has_vce 141 #define cpu_has_vce __opt(MIPS_CPU_VCE) 142 #endif 143 #ifndef cpu_has_cache_cdex_p 144 #define cpu_has_cache_cdex_p __opt(MIPS_CPU_CACHE_CDEX_P) 145 #endif 146 #ifndef cpu_has_cache_cdex_s 147 #define cpu_has_cache_cdex_s __opt(MIPS_CPU_CACHE_CDEX_S) 148 #endif 149 #ifndef cpu_has_prefetch 150 #define cpu_has_prefetch __isa_ge_or_opt(1, MIPS_CPU_PREFETCH) 151 #endif 152 #ifndef cpu_has_mcheck 153 #define cpu_has_mcheck __isa_ge_or_opt(1, MIPS_CPU_MCHECK) 154 #endif 155 #ifndef cpu_has_ejtag 156 #define cpu_has_ejtag __opt(MIPS_CPU_EJTAG) 157 #endif 158 #ifndef cpu_has_llsc 159 #define cpu_has_llsc __isa_ge_or_opt(1, MIPS_CPU_LLSC) 160 #endif 161 #ifndef cpu_has_bp_ghist 162 #define cpu_has_bp_ghist __opt(MIPS_CPU_BP_GHIST) 163 #endif 164 #ifndef kernel_uses_llsc 165 #define kernel_uses_llsc cpu_has_llsc 166 #endif 167 #ifndef cpu_has_guestctl0ext 168 #define cpu_has_guestctl0ext __opt(MIPS_CPU_GUESTCTL0EXT) 169 #endif 170 #ifndef cpu_has_guestctl1 171 #define cpu_has_guestctl1 __opt(MIPS_CPU_GUESTCTL1) 172 #endif 173 #ifndef cpu_has_guestctl2 174 #define cpu_has_guestctl2 __opt(MIPS_CPU_GUESTCTL2) 175 #endif 176 #ifndef cpu_has_guestid 177 #define cpu_has_guestid __opt(MIPS_CPU_GUESTID) 178 #endif 179 #ifndef cpu_has_drg 180 #define cpu_has_drg __opt(MIPS_CPU_DRG) 181 #endif 182 #ifndef cpu_has_mips16 183 #define cpu_has_mips16 __isa_lt_and_ase(6, MIPS_ASE_MIPS16) 184 #endif 185 #ifndef cpu_has_mips16e2 186 #define cpu_has_mips16e2 __isa_lt_and_ase(6, MIPS_ASE_MIPS16E2) 187 #endif 188 #ifndef cpu_has_mdmx 189 #define cpu_has_mdmx __isa_lt_and_ase(6, MIPS_ASE_MDMX) 190 #endif 191 #ifndef cpu_has_mips3d 192 #define cpu_has_mips3d __isa_lt_and_ase(6, MIPS_ASE_MIPS3D) 193 #endif 194 #ifndef cpu_has_smartmips 195 #define cpu_has_smartmips __isa_lt_and_ase(6, MIPS_ASE_SMARTMIPS) 196 #endif 197 198 #ifndef cpu_has_rixi 199 #define cpu_has_rixi __isa_ge_or_opt(6, MIPS_CPU_RIXI) 200 #endif 201 202 #ifndef cpu_has_mmips 203 # if defined(__mips_micromips) 204 # define cpu_has_mmips 1 205 # elif defined(CONFIG_SYS_SUPPORTS_MICROMIPS) 206 # define cpu_has_mmips __opt(MIPS_CPU_MICROMIPS) 207 # else 208 # define cpu_has_mmips 0 209 # endif 210 #endif 211 212 #ifndef cpu_has_lpa 213 #define cpu_has_lpa __opt(MIPS_CPU_LPA) 214 #endif 215 #ifndef cpu_has_mvh 216 #define cpu_has_mvh __opt(MIPS_CPU_MVH) 217 #endif 218 #ifndef cpu_has_xpa 219 #define cpu_has_xpa (cpu_has_lpa && cpu_has_mvh) 220 #endif 221 #ifndef cpu_has_vtag_icache 222 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 223 #endif 224 #ifndef cpu_has_dc_aliases 225 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) 226 #endif 227 #ifndef cpu_has_ic_fills_f_dc 228 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 229 #endif 230 #ifndef cpu_has_pindexed_dcache 231 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 232 #endif 233 #ifndef cpu_has_local_ebase 234 #define cpu_has_local_ebase 1 235 #endif 236 237 /* 238 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 239 * such as the R10000 have I-Caches that snoop local stores; the embedded ones 240 * don't. For maintaining I-cache coherency this means we need to flush the 241 * D-cache all the way back to whever the I-cache does refills from, so the 242 * I-cache has a chance to see the new data at all. Then we have to flush the 243 * I-cache also. 244 * Note we may have been rescheduled and may no longer be running on the CPU 245 * that did the store so we can't optimize this into only doing the flush on 246 * the local CPU. 247 */ 248 #ifndef cpu_icache_snoops_remote_store 249 #ifdef CONFIG_SMP 250 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) 251 #else 252 #define cpu_icache_snoops_remote_store 1 253 #endif 254 #endif 255 256 /* __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r */ 257 #if !((defined(cpu_has_mips32r1) && cpu_has_mips32r1) || \ 258 (defined(cpu_has_mips32r2) && cpu_has_mips32r2) || \ 259 (defined(cpu_has_mips32r6) && cpu_has_mips32r6) || \ 260 (defined(cpu_has_mips64r1) && cpu_has_mips64r1) || \ 261 (defined(cpu_has_mips64r2) && cpu_has_mips64r2) || \ 262 (defined(cpu_has_mips64r6) && cpu_has_mips64r6)) 263 #define CPU_NO_EFFICIENT_FFS 1 264 #endif 265 266 #ifndef cpu_has_mips_1 267 # define cpu_has_mips_1 (!cpu_has_mips_r6) 268 #endif 269 #ifndef cpu_has_mips_2 270 # define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) 271 #endif 272 #ifndef cpu_has_mips_3 273 # define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III) 274 #endif 275 #ifndef cpu_has_mips_4 276 # define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV) 277 #endif 278 #ifndef cpu_has_mips_5 279 # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) 280 #endif 281 #ifndef cpu_has_mips32r1 282 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) 283 #endif 284 #ifndef cpu_has_mips32r2 285 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 286 #endif 287 #ifndef cpu_has_mips32r6 288 # define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6) 289 #endif 290 #ifndef cpu_has_mips64r1 291 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 292 #endif 293 #ifndef cpu_has_mips64r2 294 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 295 #endif 296 #ifndef cpu_has_mips64r6 297 # define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6) 298 #endif 299 300 /* 301 * Shortcuts ... 302 */ 303 #define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5) 304 #define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5) 305 #define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5) 306 307 #define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r) 308 #define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r) 309 #define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r) 310 #define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r) 311 312 #define cpu_has_mips_3_4_5_64_r2_r6 \ 313 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6) 314 #define cpu_has_mips_4_5_64_r2_r6 \ 315 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \ 316 cpu_has_mips_r2 | cpu_has_mips_r6) 317 318 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6) 319 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6) 320 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 321 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 322 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6) 323 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 324 cpu_has_mips32r6 | cpu_has_mips64r1 | \ 325 cpu_has_mips64r2 | cpu_has_mips64r6) 326 327 /* MIPSR2 and MIPSR6 have a lot of similarities */ 328 #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6) 329 330 /* 331 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor 332 * 333 * Returns non-zero value if the current processor implementation requires 334 * an IHB instruction to deal with an instruction hazard as per MIPS R2 335 * architecture specification, zero otherwise. 336 */ 337 #ifndef cpu_has_mips_r2_exec_hazard 338 #define cpu_has_mips_r2_exec_hazard \ 339 ({ \ 340 int __res; \ 341 \ 342 switch (current_cpu_type()) { \ 343 case CPU_M14KC: \ 344 case CPU_74K: \ 345 case CPU_1074K: \ 346 case CPU_PROAPTIV: \ 347 case CPU_P5600: \ 348 case CPU_M5150: \ 349 case CPU_QEMU_GENERIC: \ 350 case CPU_CAVIUM_OCTEON: \ 351 case CPU_CAVIUM_OCTEON_PLUS: \ 352 case CPU_CAVIUM_OCTEON2: \ 353 case CPU_CAVIUM_OCTEON3: \ 354 __res = 0; \ 355 break; \ 356 \ 357 default: \ 358 __res = 1; \ 359 } \ 360 \ 361 __res; \ 362 }) 363 #endif 364 365 /* 366 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 367 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and 368 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 369 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 370 */ 371 #ifndef cpu_has_clo_clz 372 #define cpu_has_clo_clz cpu_has_mips_r 373 #endif 374 375 /* 376 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH. 377 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD. 378 * This indicates the availability of WSBH and in case of 64 bit CPUs also 379 * DSBH and DSHD. 380 */ 381 #ifndef cpu_has_wsbh 382 #define cpu_has_wsbh cpu_has_mips_r2 383 #endif 384 385 #ifndef cpu_has_dsp 386 #define cpu_has_dsp __ase(MIPS_ASE_DSP) 387 #endif 388 389 #ifndef cpu_has_dsp2 390 #define cpu_has_dsp2 __ase(MIPS_ASE_DSP2P) 391 #endif 392 393 #ifndef cpu_has_dsp3 394 #define cpu_has_dsp3 __ase(MIPS_ASE_DSP3) 395 #endif 396 397 #ifndef cpu_has_mipsmt 398 #define cpu_has_mipsmt __isa_lt_and_ase(6, MIPS_ASE_MIPSMT) 399 #endif 400 401 #ifndef cpu_has_vp 402 #define cpu_has_vp __isa_ge_and_opt(6, MIPS_CPU_VP) 403 #endif 404 405 #ifndef cpu_has_userlocal 406 #define cpu_has_userlocal __isa_ge_or_opt(6, MIPS_CPU_ULRI) 407 #endif 408 409 #ifdef CONFIG_32BIT 410 # ifndef cpu_has_nofpuex 411 # define cpu_has_nofpuex __isa_lt_and_opt(1, MIPS_CPU_NOFPUEX) 412 # endif 413 # ifndef cpu_has_64bits 414 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 415 # endif 416 # ifndef cpu_has_64bit_zero_reg 417 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 418 # endif 419 # ifndef cpu_has_64bit_gp_regs 420 # define cpu_has_64bit_gp_regs 0 421 # endif 422 # ifndef cpu_has_64bit_addresses 423 # define cpu_has_64bit_addresses 0 424 # endif 425 # ifndef cpu_vmbits 426 # define cpu_vmbits 31 427 # endif 428 #endif 429 430 #ifdef CONFIG_64BIT 431 # ifndef cpu_has_nofpuex 432 # define cpu_has_nofpuex 0 433 # endif 434 # ifndef cpu_has_64bits 435 # define cpu_has_64bits 1 436 # endif 437 # ifndef cpu_has_64bit_zero_reg 438 # define cpu_has_64bit_zero_reg 1 439 # endif 440 # ifndef cpu_has_64bit_gp_regs 441 # define cpu_has_64bit_gp_regs 1 442 # endif 443 # ifndef cpu_has_64bit_addresses 444 # define cpu_has_64bit_addresses 1 445 # endif 446 # ifndef cpu_vmbits 447 # define cpu_vmbits cpu_data[0].vmbits 448 # define __NEED_VMBITS_PROBE 449 # endif 450 #endif 451 452 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 453 # define cpu_has_vint __opt(MIPS_CPU_VINT) 454 #elif !defined(cpu_has_vint) 455 # define cpu_has_vint 0 456 #endif 457 458 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 459 # define cpu_has_veic __opt(MIPS_CPU_VEIC) 460 #elif !defined(cpu_has_veic) 461 # define cpu_has_veic 0 462 #endif 463 464 #ifndef cpu_has_inclusive_pcaches 465 #define cpu_has_inclusive_pcaches __opt(MIPS_CPU_INCLUSIVE_CACHES) 466 #endif 467 468 #ifndef cpu_dcache_line_size 469 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz 470 #endif 471 #ifndef cpu_icache_line_size 472 #define cpu_icache_line_size() cpu_data[0].icache.linesz 473 #endif 474 #ifndef cpu_scache_line_size 475 #define cpu_scache_line_size() cpu_data[0].scache.linesz 476 #endif 477 #ifndef cpu_tcache_line_size 478 #define cpu_tcache_line_size() cpu_data[0].tcache.linesz 479 #endif 480 481 #ifndef cpu_hwrena_impl_bits 482 #define cpu_hwrena_impl_bits 0 483 #endif 484 485 #ifndef cpu_has_perf_cntr_intr_bit 486 #define cpu_has_perf_cntr_intr_bit __opt(MIPS_CPU_PCI) 487 #endif 488 489 #ifndef cpu_has_vz 490 #define cpu_has_vz __ase(MIPS_ASE_VZ) 491 #endif 492 493 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa) 494 # define cpu_has_msa __ase(MIPS_ASE_MSA) 495 #elif !defined(cpu_has_msa) 496 # define cpu_has_msa 0 497 #endif 498 499 #ifndef cpu_has_ufr 500 # define cpu_has_ufr __opt(MIPS_CPU_UFR) 501 #endif 502 503 #ifndef cpu_has_fre 504 # define cpu_has_fre __opt(MIPS_CPU_FRE) 505 #endif 506 507 #ifndef cpu_has_cdmm 508 # define cpu_has_cdmm __opt(MIPS_CPU_CDMM) 509 #endif 510 511 #ifndef cpu_has_small_pages 512 # define cpu_has_small_pages __opt(MIPS_CPU_SP) 513 #endif 514 515 #ifndef cpu_has_nan_legacy 516 #define cpu_has_nan_legacy __isa_lt_and_opt(6, MIPS_CPU_NAN_LEGACY) 517 #endif 518 #ifndef cpu_has_nan_2008 519 #define cpu_has_nan_2008 __isa_ge_or_opt(6, MIPS_CPU_NAN_2008) 520 #endif 521 522 #ifndef cpu_has_ebase_wg 523 # define cpu_has_ebase_wg __opt(MIPS_CPU_EBASE_WG) 524 #endif 525 526 #ifndef cpu_has_badinstr 527 # define cpu_has_badinstr __isa_ge_or_opt(6, MIPS_CPU_BADINSTR) 528 #endif 529 530 #ifndef cpu_has_badinstrp 531 # define cpu_has_badinstrp __isa_ge_or_opt(6, MIPS_CPU_BADINSTRP) 532 #endif 533 534 #ifndef cpu_has_contextconfig 535 # define cpu_has_contextconfig __opt(MIPS_CPU_CTXTC) 536 #endif 537 538 #ifndef cpu_has_perf 539 # define cpu_has_perf __opt(MIPS_CPU_PERF) 540 #endif 541 542 #ifdef CONFIG_SMP 543 /* 544 * Some systems share FTLB RAMs between threads within a core (siblings in 545 * kernel parlance). This means that FTLB entries may become invalid at almost 546 * any point when an entry is evicted due to a sibling thread writing an entry 547 * to the shared FTLB RAM. 548 * 549 * This is only relevant to SMP systems, and the only systems that exhibit this 550 * property implement MIPSr6 or higher so we constrain support for this to 551 * kernels that will run on such systems. 552 */ 553 # ifndef cpu_has_shared_ftlb_ram 554 # define cpu_has_shared_ftlb_ram \ 555 __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_RAM) 556 # endif 557 558 /* 559 * Some systems take this a step further & share FTLB entries between siblings. 560 * This is implemented as TLB writes happening as usual, but if an entry 561 * written by a sibling exists in the shared FTLB for a translation which would 562 * otherwise cause a TLB refill exception then the CPU will use the entry 563 * written by its sibling rather than triggering a refill & writing a matching 564 * TLB entry for itself. 565 * 566 * This is naturally only valid if a TLB entry is known to be suitable for use 567 * on all siblings in a CPU, and so it only takes effect when MMIDs are in use 568 * rather than ASIDs or when a TLB entry is marked global. 569 */ 570 # ifndef cpu_has_shared_ftlb_entries 571 # define cpu_has_shared_ftlb_entries \ 572 __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_ENTRIES) 573 # endif 574 #endif /* SMP */ 575 576 #ifndef cpu_has_shared_ftlb_ram 577 # define cpu_has_shared_ftlb_ram 0 578 #endif 579 #ifndef cpu_has_shared_ftlb_entries 580 # define cpu_has_shared_ftlb_entries 0 581 #endif 582 583 #ifdef CONFIG_MIPS_MT_SMP 584 # define cpu_has_mipsmt_pertccounters \ 585 __isa_lt_and_opt(6, MIPS_CPU_MT_PER_TC_PERF_COUNTERS) 586 #else 587 # define cpu_has_mipsmt_pertccounters 0 588 #endif /* CONFIG_MIPS_MT_SMP */ 589 590 /* 591 * Guest capabilities 592 */ 593 #ifndef cpu_guest_has_conf1 594 #define cpu_guest_has_conf1 (cpu_data[0].guest.conf & (1 << 1)) 595 #endif 596 #ifndef cpu_guest_has_conf2 597 #define cpu_guest_has_conf2 (cpu_data[0].guest.conf & (1 << 2)) 598 #endif 599 #ifndef cpu_guest_has_conf3 600 #define cpu_guest_has_conf3 (cpu_data[0].guest.conf & (1 << 3)) 601 #endif 602 #ifndef cpu_guest_has_conf4 603 #define cpu_guest_has_conf4 (cpu_data[0].guest.conf & (1 << 4)) 604 #endif 605 #ifndef cpu_guest_has_conf5 606 #define cpu_guest_has_conf5 (cpu_data[0].guest.conf & (1 << 5)) 607 #endif 608 #ifndef cpu_guest_has_conf6 609 #define cpu_guest_has_conf6 (cpu_data[0].guest.conf & (1 << 6)) 610 #endif 611 #ifndef cpu_guest_has_conf7 612 #define cpu_guest_has_conf7 (cpu_data[0].guest.conf & (1 << 7)) 613 #endif 614 #ifndef cpu_guest_has_fpu 615 #define cpu_guest_has_fpu (cpu_data[0].guest.options & MIPS_CPU_FPU) 616 #endif 617 #ifndef cpu_guest_has_watch 618 #define cpu_guest_has_watch (cpu_data[0].guest.options & MIPS_CPU_WATCH) 619 #endif 620 #ifndef cpu_guest_has_contextconfig 621 #define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC) 622 #endif 623 #ifndef cpu_guest_has_segments 624 #define cpu_guest_has_segments (cpu_data[0].guest.options & MIPS_CPU_SEGMENTS) 625 #endif 626 #ifndef cpu_guest_has_badinstr 627 #define cpu_guest_has_badinstr (cpu_data[0].guest.options & MIPS_CPU_BADINSTR) 628 #endif 629 #ifndef cpu_guest_has_badinstrp 630 #define cpu_guest_has_badinstrp (cpu_data[0].guest.options & MIPS_CPU_BADINSTRP) 631 #endif 632 #ifndef cpu_guest_has_htw 633 #define cpu_guest_has_htw (cpu_data[0].guest.options & MIPS_CPU_HTW) 634 #endif 635 #ifndef cpu_guest_has_mvh 636 #define cpu_guest_has_mvh (cpu_data[0].guest.options & MIPS_CPU_MVH) 637 #endif 638 #ifndef cpu_guest_has_msa 639 #define cpu_guest_has_msa (cpu_data[0].guest.ases & MIPS_ASE_MSA) 640 #endif 641 #ifndef cpu_guest_has_kscr 642 #define cpu_guest_has_kscr(n) (cpu_data[0].guest.kscratch_mask & (1u << (n))) 643 #endif 644 #ifndef cpu_guest_has_rw_llb 645 #define cpu_guest_has_rw_llb (cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB)) 646 #endif 647 #ifndef cpu_guest_has_perf 648 #define cpu_guest_has_perf (cpu_data[0].guest.options & MIPS_CPU_PERF) 649 #endif 650 #ifndef cpu_guest_has_maar 651 #define cpu_guest_has_maar (cpu_data[0].guest.options & MIPS_CPU_MAAR) 652 #endif 653 #ifndef cpu_guest_has_userlocal 654 #define cpu_guest_has_userlocal (cpu_data[0].guest.options & MIPS_CPU_ULRI) 655 #endif 656 657 /* 658 * Guest dynamic capabilities 659 */ 660 #ifndef cpu_guest_has_dyn_fpu 661 #define cpu_guest_has_dyn_fpu (cpu_data[0].guest.options_dyn & MIPS_CPU_FPU) 662 #endif 663 #ifndef cpu_guest_has_dyn_watch 664 #define cpu_guest_has_dyn_watch (cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH) 665 #endif 666 #ifndef cpu_guest_has_dyn_contextconfig 667 #define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC) 668 #endif 669 #ifndef cpu_guest_has_dyn_perf 670 #define cpu_guest_has_dyn_perf (cpu_data[0].guest.options_dyn & MIPS_CPU_PERF) 671 #endif 672 #ifndef cpu_guest_has_dyn_msa 673 #define cpu_guest_has_dyn_msa (cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA) 674 #endif 675 #ifndef cpu_guest_has_dyn_maar 676 #define cpu_guest_has_dyn_maar (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR) 677 #endif 678 679 #endif /* __ASM_CPU_FEATURES_H */ 680