1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org) 7 */ 8 #ifndef __ASM_CMPXCHG_H 9 #define __ASM_CMPXCHG_H 10 11 #include <linux/bug.h> 12 #include <linux/irqflags.h> 13 #include <asm/compiler.h> 14 #include <asm/llsc.h> 15 #include <asm/sync.h> 16 #include <asm/war.h> 17 18 /* 19 * These functions doesn't exist, so if they are called you'll either: 20 * 21 * - Get an error at compile-time due to __compiletime_error, if supported by 22 * your compiler. 23 * 24 * or: 25 * 26 * - Get an error at link-time due to the call to the missing function. 27 */ 28 extern unsigned long __cmpxchg_called_with_bad_pointer(void) 29 __compiletime_error("Bad argument size for cmpxchg"); 30 extern unsigned long __cmpxchg64_unsupported(void) 31 __compiletime_error("cmpxchg64 not available; cpu_has_64bits may be false"); 32 extern unsigned long __xchg_called_with_bad_pointer(void) 33 __compiletime_error("Bad argument size for xchg"); 34 35 #define __xchg_asm(ld, st, m, val) \ 36 ({ \ 37 __typeof(*(m)) __ret; \ 38 \ 39 if (kernel_uses_llsc) { \ 40 __asm__ __volatile__( \ 41 " .set push \n" \ 42 " .set noat \n" \ 43 " .set push \n" \ 44 " .set " MIPS_ISA_ARCH_LEVEL " \n" \ 45 " " __SYNC(full, loongson3_war) " \n" \ 46 "1: " ld " %0, %2 # __xchg_asm \n" \ 47 " .set pop \n" \ 48 " move $1, %z3 \n" \ 49 " .set " MIPS_ISA_ARCH_LEVEL " \n" \ 50 " " st " $1, %1 \n" \ 51 "\t" __SC_BEQZ "$1, 1b \n" \ 52 " .set pop \n" \ 53 : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \ 54 : GCC_OFF_SMALL_ASM() (*m), "Jr" (val) \ 55 : __LLSC_CLOBBER); \ 56 } else { \ 57 unsigned long __flags; \ 58 \ 59 raw_local_irq_save(__flags); \ 60 __ret = *m; \ 61 *m = val; \ 62 raw_local_irq_restore(__flags); \ 63 } \ 64 \ 65 __ret; \ 66 }) 67 68 extern unsigned long __xchg_small(volatile void *ptr, unsigned long val, 69 unsigned int size); 70 71 static inline unsigned long __xchg(volatile void *ptr, unsigned long x, 72 int size) 73 { 74 switch (size) { 75 case 1: 76 case 2: 77 return __xchg_small(ptr, x, size); 78 79 case 4: 80 return __xchg_asm("ll", "sc", (volatile u32 *)ptr, x); 81 82 case 8: 83 if (!IS_ENABLED(CONFIG_64BIT)) 84 return __xchg_called_with_bad_pointer(); 85 86 return __xchg_asm("lld", "scd", (volatile u64 *)ptr, x); 87 88 default: 89 return __xchg_called_with_bad_pointer(); 90 } 91 } 92 93 #define xchg(ptr, x) \ 94 ({ \ 95 __typeof__(*(ptr)) __res; \ 96 \ 97 /* \ 98 * In the Loongson3 workaround case __xchg_asm() already \ 99 * contains a completion barrier prior to the LL, so we don't \ 100 * need to emit an extra one here. \ 101 */ \ 102 if (!__SYNC_loongson3_war) \ 103 smp_mb__before_llsc(); \ 104 \ 105 __res = (__typeof__(*(ptr))) \ 106 __xchg((ptr), (unsigned long)(x), sizeof(*(ptr))); \ 107 \ 108 smp_llsc_mb(); \ 109 \ 110 __res; \ 111 }) 112 113 #define __cmpxchg_asm(ld, st, m, old, new) \ 114 ({ \ 115 __typeof(*(m)) __ret; \ 116 \ 117 if (kernel_uses_llsc) { \ 118 __asm__ __volatile__( \ 119 " .set push \n" \ 120 " .set noat \n" \ 121 " .set push \n" \ 122 " .set "MIPS_ISA_ARCH_LEVEL" \n" \ 123 " " __SYNC(full, loongson3_war) " \n" \ 124 "1: " ld " %0, %2 # __cmpxchg_asm \n" \ 125 " bne %0, %z3, 2f \n" \ 126 " .set pop \n" \ 127 " move $1, %z4 \n" \ 128 " .set "MIPS_ISA_ARCH_LEVEL" \n" \ 129 " " st " $1, %1 \n" \ 130 "\t" __SC_BEQZ "$1, 1b \n" \ 131 " .set pop \n" \ 132 "2: " __SYNC(full, loongson3_war) " \n" \ 133 : "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \ 134 : GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \ 135 : __LLSC_CLOBBER); \ 136 } else { \ 137 unsigned long __flags; \ 138 \ 139 raw_local_irq_save(__flags); \ 140 __ret = *m; \ 141 if (__ret == old) \ 142 *m = new; \ 143 raw_local_irq_restore(__flags); \ 144 } \ 145 \ 146 __ret; \ 147 }) 148 149 extern unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old, 150 unsigned long new, unsigned int size); 151 152 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, 153 unsigned long new, unsigned int size) 154 { 155 switch (size) { 156 case 1: 157 case 2: 158 return __cmpxchg_small(ptr, old, new, size); 159 160 case 4: 161 return __cmpxchg_asm("ll", "sc", (volatile u32 *)ptr, 162 (u32)old, new); 163 164 case 8: 165 /* lld/scd are only available for MIPS64 */ 166 if (!IS_ENABLED(CONFIG_64BIT)) 167 return __cmpxchg_called_with_bad_pointer(); 168 169 return __cmpxchg_asm("lld", "scd", (volatile u64 *)ptr, 170 (u64)old, new); 171 172 default: 173 return __cmpxchg_called_with_bad_pointer(); 174 } 175 } 176 177 #define cmpxchg_local(ptr, old, new) \ 178 ((__typeof__(*(ptr))) \ 179 __cmpxchg((ptr), \ 180 (unsigned long)(__typeof__(*(ptr)))(old), \ 181 (unsigned long)(__typeof__(*(ptr)))(new), \ 182 sizeof(*(ptr)))) 183 184 #define cmpxchg(ptr, old, new) \ 185 ({ \ 186 __typeof__(*(ptr)) __res; \ 187 \ 188 /* \ 189 * In the Loongson3 workaround case __cmpxchg_asm() already \ 190 * contains a completion barrier prior to the LL, so we don't \ 191 * need to emit an extra one here. \ 192 */ \ 193 if (!__SYNC_loongson3_war) \ 194 smp_mb__before_llsc(); \ 195 \ 196 __res = cmpxchg_local((ptr), (old), (new)); \ 197 \ 198 /* \ 199 * In the Loongson3 workaround case __cmpxchg_asm() already \ 200 * contains a completion barrier after the SC, so we don't \ 201 * need to emit an extra one here. \ 202 */ \ 203 if (!__SYNC_loongson3_war) \ 204 smp_llsc_mb(); \ 205 \ 206 __res; \ 207 }) 208 209 #ifdef CONFIG_64BIT 210 #define cmpxchg64_local(ptr, o, n) \ 211 ({ \ 212 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ 213 cmpxchg_local((ptr), (o), (n)); \ 214 }) 215 216 #define cmpxchg64(ptr, o, n) \ 217 ({ \ 218 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ 219 cmpxchg((ptr), (o), (n)); \ 220 }) 221 #else 222 223 # include <asm-generic/cmpxchg-local.h> 224 # define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) 225 226 # ifdef CONFIG_SMP 227 228 static inline unsigned long __cmpxchg64(volatile void *ptr, 229 unsigned long long old, 230 unsigned long long new) 231 { 232 unsigned long long tmp, ret; 233 unsigned long flags; 234 235 /* 236 * The assembly below has to combine 32 bit values into a 64 bit 237 * register, and split 64 bit values from one register into two. If we 238 * were to take an interrupt in the middle of this we'd only save the 239 * least significant 32 bits of each register & probably clobber the 240 * most significant 32 bits of the 64 bit values we're using. In order 241 * to avoid this we must disable interrupts. 242 */ 243 local_irq_save(flags); 244 245 asm volatile( 246 " .set push \n" 247 " .set " MIPS_ISA_ARCH_LEVEL " \n" 248 /* Load 64 bits from ptr */ 249 " " __SYNC(full, loongson3_war) " \n" 250 "1: lld %L0, %3 # __cmpxchg64 \n" 251 /* 252 * Split the 64 bit value we loaded into the 2 registers that hold the 253 * ret variable. 254 */ 255 " dsra %M0, %L0, 32 \n" 256 " sll %L0, %L0, 0 \n" 257 /* 258 * Compare ret against old, breaking out of the loop if they don't 259 * match. 260 */ 261 " bne %M0, %M4, 2f \n" 262 " bne %L0, %L4, 2f \n" 263 /* 264 * Combine the 32 bit halves from the 2 registers that hold the new 265 * variable into a single 64 bit register. 266 */ 267 # if MIPS_ISA_REV >= 2 268 " move %L1, %L5 \n" 269 " dins %L1, %M5, 32, 32 \n" 270 # else 271 " dsll %L1, %L5, 32 \n" 272 " dsrl %L1, %L1, 32 \n" 273 " .set noat \n" 274 " dsll $at, %M5, 32 \n" 275 " or %L1, %L1, $at \n" 276 " .set at \n" 277 # endif 278 /* Attempt to store new at ptr */ 279 " scd %L1, %2 \n" 280 /* If we failed, loop! */ 281 "\t" __SC_BEQZ "%L1, 1b \n" 282 " .set pop \n" 283 "2: " __SYNC(full, loongson3_war) " \n" 284 : "=&r"(ret), 285 "=&r"(tmp), 286 "=" GCC_OFF_SMALL_ASM() (*(unsigned long long *)ptr) 287 : GCC_OFF_SMALL_ASM() (*(unsigned long long *)ptr), 288 "r" (old), 289 "r" (new) 290 : "memory"); 291 292 local_irq_restore(flags); 293 return ret; 294 } 295 296 # define cmpxchg64(ptr, o, n) ({ \ 297 unsigned long long __old = (__typeof__(*(ptr)))(o); \ 298 unsigned long long __new = (__typeof__(*(ptr)))(n); \ 299 __typeof__(*(ptr)) __res; \ 300 \ 301 /* \ 302 * We can only use cmpxchg64 if we know that the CPU supports \ 303 * 64-bits, ie. lld & scd. Our call to __cmpxchg64_unsupported \ 304 * will cause a build error unless cpu_has_64bits is a \ 305 * compile-time constant 1. \ 306 */ \ 307 if (cpu_has_64bits && kernel_uses_llsc) { \ 308 smp_mb__before_llsc(); \ 309 __res = __cmpxchg64((ptr), __old, __new); \ 310 smp_llsc_mb(); \ 311 } else { \ 312 __res = __cmpxchg64_unsupported(); \ 313 } \ 314 \ 315 __res; \ 316 }) 317 318 # else /* !CONFIG_SMP */ 319 # define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n)) 320 # endif /* !CONFIG_SMP */ 321 #endif /* !CONFIG_64BIT */ 322 323 #endif /* __ASM_CMPXCHG_H */ 324