1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003 Ralf Baechle 7 */ 8 #ifndef _ASM_ASMMACRO_H 9 #define _ASM_ASMMACRO_H 10 11 #include <asm/hazards.h> 12 #include <asm/asm-offsets.h> 13 #include <asm/msa.h> 14 15 #ifdef CONFIG_32BIT 16 #include <asm/asmmacro-32.h> 17 #endif 18 #ifdef CONFIG_64BIT 19 #include <asm/asmmacro-64.h> 20 #endif 21 22 #ifdef CONFIG_CPU_MIPSR2 23 .macro local_irq_enable reg=t0 24 ei 25 irq_enable_hazard 26 .endm 27 28 .macro local_irq_disable reg=t0 29 di 30 irq_disable_hazard 31 .endm 32 #else 33 .macro local_irq_enable reg=t0 34 mfc0 \reg, CP0_STATUS 35 ori \reg, \reg, 1 36 mtc0 \reg, CP0_STATUS 37 irq_enable_hazard 38 .endm 39 40 .macro local_irq_disable reg=t0 41 #ifdef CONFIG_PREEMPT 42 lw \reg, TI_PRE_COUNT($28) 43 addi \reg, \reg, 1 44 sw \reg, TI_PRE_COUNT($28) 45 #endif 46 mfc0 \reg, CP0_STATUS 47 ori \reg, \reg, 1 48 xori \reg, \reg, 1 49 mtc0 \reg, CP0_STATUS 50 irq_disable_hazard 51 #ifdef CONFIG_PREEMPT 52 lw \reg, TI_PRE_COUNT($28) 53 addi \reg, \reg, -1 54 sw \reg, TI_PRE_COUNT($28) 55 #endif 56 .endm 57 #endif /* CONFIG_CPU_MIPSR2 */ 58 59 .macro fpu_save_16even thread tmp=t0 60 cfc1 \tmp, fcr31 61 sdc1 $f0, THREAD_FPR0_LS64(\thread) 62 sdc1 $f2, THREAD_FPR2_LS64(\thread) 63 sdc1 $f4, THREAD_FPR4_LS64(\thread) 64 sdc1 $f6, THREAD_FPR6_LS64(\thread) 65 sdc1 $f8, THREAD_FPR8_LS64(\thread) 66 sdc1 $f10, THREAD_FPR10_LS64(\thread) 67 sdc1 $f12, THREAD_FPR12_LS64(\thread) 68 sdc1 $f14, THREAD_FPR14_LS64(\thread) 69 sdc1 $f16, THREAD_FPR16_LS64(\thread) 70 sdc1 $f18, THREAD_FPR18_LS64(\thread) 71 sdc1 $f20, THREAD_FPR20_LS64(\thread) 72 sdc1 $f22, THREAD_FPR22_LS64(\thread) 73 sdc1 $f24, THREAD_FPR24_LS64(\thread) 74 sdc1 $f26, THREAD_FPR26_LS64(\thread) 75 sdc1 $f28, THREAD_FPR28_LS64(\thread) 76 sdc1 $f30, THREAD_FPR30_LS64(\thread) 77 sw \tmp, THREAD_FCR31(\thread) 78 .endm 79 80 .macro fpu_save_16odd thread 81 .set push 82 .set mips64r2 83 sdc1 $f1, THREAD_FPR1_LS64(\thread) 84 sdc1 $f3, THREAD_FPR3_LS64(\thread) 85 sdc1 $f5, THREAD_FPR5_LS64(\thread) 86 sdc1 $f7, THREAD_FPR7_LS64(\thread) 87 sdc1 $f9, THREAD_FPR9_LS64(\thread) 88 sdc1 $f11, THREAD_FPR11_LS64(\thread) 89 sdc1 $f13, THREAD_FPR13_LS64(\thread) 90 sdc1 $f15, THREAD_FPR15_LS64(\thread) 91 sdc1 $f17, THREAD_FPR17_LS64(\thread) 92 sdc1 $f19, THREAD_FPR19_LS64(\thread) 93 sdc1 $f21, THREAD_FPR21_LS64(\thread) 94 sdc1 $f23, THREAD_FPR23_LS64(\thread) 95 sdc1 $f25, THREAD_FPR25_LS64(\thread) 96 sdc1 $f27, THREAD_FPR27_LS64(\thread) 97 sdc1 $f29, THREAD_FPR29_LS64(\thread) 98 sdc1 $f31, THREAD_FPR31_LS64(\thread) 99 .set pop 100 .endm 101 102 .macro fpu_save_double thread status tmp 103 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) 104 sll \tmp, \status, 5 105 bgez \tmp, 10f 106 fpu_save_16odd \thread 107 10: 108 #endif 109 fpu_save_16even \thread \tmp 110 .endm 111 112 .macro fpu_restore_16even thread tmp=t0 113 lw \tmp, THREAD_FCR31(\thread) 114 ldc1 $f0, THREAD_FPR0_LS64(\thread) 115 ldc1 $f2, THREAD_FPR2_LS64(\thread) 116 ldc1 $f4, THREAD_FPR4_LS64(\thread) 117 ldc1 $f6, THREAD_FPR6_LS64(\thread) 118 ldc1 $f8, THREAD_FPR8_LS64(\thread) 119 ldc1 $f10, THREAD_FPR10_LS64(\thread) 120 ldc1 $f12, THREAD_FPR12_LS64(\thread) 121 ldc1 $f14, THREAD_FPR14_LS64(\thread) 122 ldc1 $f16, THREAD_FPR16_LS64(\thread) 123 ldc1 $f18, THREAD_FPR18_LS64(\thread) 124 ldc1 $f20, THREAD_FPR20_LS64(\thread) 125 ldc1 $f22, THREAD_FPR22_LS64(\thread) 126 ldc1 $f24, THREAD_FPR24_LS64(\thread) 127 ldc1 $f26, THREAD_FPR26_LS64(\thread) 128 ldc1 $f28, THREAD_FPR28_LS64(\thread) 129 ldc1 $f30, THREAD_FPR30_LS64(\thread) 130 ctc1 \tmp, fcr31 131 .endm 132 133 .macro fpu_restore_16odd thread 134 .set push 135 .set mips64r2 136 ldc1 $f1, THREAD_FPR1_LS64(\thread) 137 ldc1 $f3, THREAD_FPR3_LS64(\thread) 138 ldc1 $f5, THREAD_FPR5_LS64(\thread) 139 ldc1 $f7, THREAD_FPR7_LS64(\thread) 140 ldc1 $f9, THREAD_FPR9_LS64(\thread) 141 ldc1 $f11, THREAD_FPR11_LS64(\thread) 142 ldc1 $f13, THREAD_FPR13_LS64(\thread) 143 ldc1 $f15, THREAD_FPR15_LS64(\thread) 144 ldc1 $f17, THREAD_FPR17_LS64(\thread) 145 ldc1 $f19, THREAD_FPR19_LS64(\thread) 146 ldc1 $f21, THREAD_FPR21_LS64(\thread) 147 ldc1 $f23, THREAD_FPR23_LS64(\thread) 148 ldc1 $f25, THREAD_FPR25_LS64(\thread) 149 ldc1 $f27, THREAD_FPR27_LS64(\thread) 150 ldc1 $f29, THREAD_FPR29_LS64(\thread) 151 ldc1 $f31, THREAD_FPR31_LS64(\thread) 152 .set pop 153 .endm 154 155 .macro fpu_restore_double thread status tmp 156 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) 157 sll \tmp, \status, 5 158 bgez \tmp, 10f # 16 register mode? 159 160 fpu_restore_16odd \thread 161 10: 162 #endif 163 fpu_restore_16even \thread \tmp 164 .endm 165 166 #ifdef CONFIG_CPU_MIPSR2 167 .macro _EXT rd, rs, p, s 168 ext \rd, \rs, \p, \s 169 .endm 170 #else /* !CONFIG_CPU_MIPSR2 */ 171 .macro _EXT rd, rs, p, s 172 srl \rd, \rs, \p 173 andi \rd, \rd, (1 << \s) - 1 174 .endm 175 #endif /* !CONFIG_CPU_MIPSR2 */ 176 177 /* 178 * Temporary until all gas have MT ASE support 179 */ 180 .macro DMT reg=0 181 .word 0x41600bc1 | (\reg << 16) 182 .endm 183 184 .macro EMT reg=0 185 .word 0x41600be1 | (\reg << 16) 186 .endm 187 188 .macro DVPE reg=0 189 .word 0x41600001 | (\reg << 16) 190 .endm 191 192 .macro EVPE reg=0 193 .word 0x41600021 | (\reg << 16) 194 .endm 195 196 .macro MFTR rt=0, rd=0, u=0, sel=0 197 .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) 198 .endm 199 200 .macro MTTR rt=0, rd=0, u=0, sel=0 201 .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) 202 .endm 203 204 #ifdef TOOLCHAIN_SUPPORTS_MSA 205 .macro ld_d wd, off, base 206 .set push 207 .set mips32r2 208 .set msa 209 ld.d $w\wd, \off(\base) 210 .set pop 211 .endm 212 213 .macro st_d wd, off, base 214 .set push 215 .set mips32r2 216 .set msa 217 st.d $w\wd, \off(\base) 218 .set pop 219 .endm 220 221 .macro copy_u_w rd, ws, n 222 .set push 223 .set mips32r2 224 .set msa 225 copy_u.w \rd, $w\ws[\n] 226 .set pop 227 .endm 228 229 .macro copy_u_d rd, ws, n 230 .set push 231 .set mips64r2 232 .set msa 233 copy_u.d \rd, $w\ws[\n] 234 .set pop 235 .endm 236 237 .macro insert_w wd, n, rs 238 .set push 239 .set mips32r2 240 .set msa 241 insert.w $w\wd[\n], \rs 242 .set pop 243 .endm 244 245 .macro insert_d wd, n, rs 246 .set push 247 .set mips64r2 248 .set msa 249 insert.d $w\wd[\n], \rs 250 .set pop 251 .endm 252 #else 253 254 #ifdef CONFIG_CPU_MICROMIPS 255 #define CFC_MSA_INSN 0x587e0056 256 #define CTC_MSA_INSN 0x583e0816 257 #define LDD_MSA_INSN 0x58000837 258 #define STD_MSA_INSN 0x5800083f 259 #define COPY_UW_MSA_INSN 0x58f00056 260 #define COPY_UD_MSA_INSN 0x58f80056 261 #define INSERT_W_MSA_INSN 0x59300816 262 #define INSERT_D_MSA_INSN 0x59380816 263 #else 264 #define CFC_MSA_INSN 0x787e0059 265 #define CTC_MSA_INSN 0x783e0819 266 #define LDD_MSA_INSN 0x78000823 267 #define STD_MSA_INSN 0x78000827 268 #define COPY_UW_MSA_INSN 0x78f00059 269 #define COPY_UD_MSA_INSN 0x78f80059 270 #define INSERT_W_MSA_INSN 0x79300819 271 #define INSERT_D_MSA_INSN 0x79380819 272 #endif 273 274 /* 275 * Temporary until all toolchains in use include MSA support. 276 */ 277 .macro cfcmsa rd, cs 278 .set push 279 .set noat 280 .insn 281 .word CFC_MSA_INSN | (\cs << 11) 282 move \rd, $1 283 .set pop 284 .endm 285 286 .macro ctcmsa cd, rs 287 .set push 288 .set noat 289 move $1, \rs 290 .word CTC_MSA_INSN | (\cd << 6) 291 .set pop 292 .endm 293 294 .macro ld_d wd, off, base 295 .set push 296 .set noat 297 add $1, \base, \off 298 .word LDD_MSA_INSN | (\wd << 6) 299 .set pop 300 .endm 301 302 .macro st_d wd, off, base 303 .set push 304 .set noat 305 add $1, \base, \off 306 .word STD_MSA_INSN | (\wd << 6) 307 .set pop 308 .endm 309 310 .macro copy_u_w rd, ws, n 311 .set push 312 .set noat 313 .insn 314 .word COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11) 315 /* move triggers an assembler bug... */ 316 or \rd, $1, zero 317 .set pop 318 .endm 319 320 .macro copy_u_d rd, ws, n 321 .set push 322 .set noat 323 .insn 324 .word COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11) 325 /* move triggers an assembler bug... */ 326 or \rd, $1, zero 327 .set pop 328 .endm 329 330 .macro insert_w wd, n, rs 331 .set push 332 .set noat 333 /* move triggers an assembler bug... */ 334 or $1, \rs, zero 335 .word INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6) 336 .set pop 337 .endm 338 339 .macro insert_d wd, n, rs 340 .set push 341 .set noat 342 /* move triggers an assembler bug... */ 343 or $1, \rs, zero 344 .word INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6) 345 .set pop 346 .endm 347 #endif 348 349 .macro msa_save_all thread 350 st_d 0, THREAD_FPR0, \thread 351 st_d 1, THREAD_FPR1, \thread 352 st_d 2, THREAD_FPR2, \thread 353 st_d 3, THREAD_FPR3, \thread 354 st_d 4, THREAD_FPR4, \thread 355 st_d 5, THREAD_FPR5, \thread 356 st_d 6, THREAD_FPR6, \thread 357 st_d 7, THREAD_FPR7, \thread 358 st_d 8, THREAD_FPR8, \thread 359 st_d 9, THREAD_FPR9, \thread 360 st_d 10, THREAD_FPR10, \thread 361 st_d 11, THREAD_FPR11, \thread 362 st_d 12, THREAD_FPR12, \thread 363 st_d 13, THREAD_FPR13, \thread 364 st_d 14, THREAD_FPR14, \thread 365 st_d 15, THREAD_FPR15, \thread 366 st_d 16, THREAD_FPR16, \thread 367 st_d 17, THREAD_FPR17, \thread 368 st_d 18, THREAD_FPR18, \thread 369 st_d 19, THREAD_FPR19, \thread 370 st_d 20, THREAD_FPR20, \thread 371 st_d 21, THREAD_FPR21, \thread 372 st_d 22, THREAD_FPR22, \thread 373 st_d 23, THREAD_FPR23, \thread 374 st_d 24, THREAD_FPR24, \thread 375 st_d 25, THREAD_FPR25, \thread 376 st_d 26, THREAD_FPR26, \thread 377 st_d 27, THREAD_FPR27, \thread 378 st_d 28, THREAD_FPR28, \thread 379 st_d 29, THREAD_FPR29, \thread 380 st_d 30, THREAD_FPR30, \thread 381 st_d 31, THREAD_FPR31, \thread 382 .set push 383 .set noat 384 cfcmsa $1, MSA_CSR 385 sw $1, THREAD_MSA_CSR(\thread) 386 .set pop 387 .endm 388 389 .macro msa_restore_all thread 390 .set push 391 .set noat 392 lw $1, THREAD_MSA_CSR(\thread) 393 ctcmsa MSA_CSR, $1 394 .set pop 395 ld_d 0, THREAD_FPR0, \thread 396 ld_d 1, THREAD_FPR1, \thread 397 ld_d 2, THREAD_FPR2, \thread 398 ld_d 3, THREAD_FPR3, \thread 399 ld_d 4, THREAD_FPR4, \thread 400 ld_d 5, THREAD_FPR5, \thread 401 ld_d 6, THREAD_FPR6, \thread 402 ld_d 7, THREAD_FPR7, \thread 403 ld_d 8, THREAD_FPR8, \thread 404 ld_d 9, THREAD_FPR9, \thread 405 ld_d 10, THREAD_FPR10, \thread 406 ld_d 11, THREAD_FPR11, \thread 407 ld_d 12, THREAD_FPR12, \thread 408 ld_d 13, THREAD_FPR13, \thread 409 ld_d 14, THREAD_FPR14, \thread 410 ld_d 15, THREAD_FPR15, \thread 411 ld_d 16, THREAD_FPR16, \thread 412 ld_d 17, THREAD_FPR17, \thread 413 ld_d 18, THREAD_FPR18, \thread 414 ld_d 19, THREAD_FPR19, \thread 415 ld_d 20, THREAD_FPR20, \thread 416 ld_d 21, THREAD_FPR21, \thread 417 ld_d 22, THREAD_FPR22, \thread 418 ld_d 23, THREAD_FPR23, \thread 419 ld_d 24, THREAD_FPR24, \thread 420 ld_d 25, THREAD_FPR25, \thread 421 ld_d 26, THREAD_FPR26, \thread 422 ld_d 27, THREAD_FPR27, \thread 423 ld_d 28, THREAD_FPR28, \thread 424 ld_d 29, THREAD_FPR29, \thread 425 ld_d 30, THREAD_FPR30, \thread 426 ld_d 31, THREAD_FPR31, \thread 427 .endm 428 429 .macro msa_init_upper wd 430 #ifdef CONFIG_64BIT 431 insert_d \wd, 1 432 #else 433 insert_w \wd, 2 434 insert_w \wd, 3 435 #endif 436 .if 31-\wd 437 msa_init_upper (\wd+1) 438 .endif 439 .endm 440 441 .macro msa_init_all_upper 442 .set push 443 .set noat 444 not $1, zero 445 msa_init_upper 0 446 .set pop 447 .endm 448 449 #endif /* _ASM_ASMMACRO_H */ 450