1 /* 2 * System-specific setup, especially interrupts. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1998 Harald Koerfgen 9 * Copyright (C) 2000, 2001, 2002, 2003, 2005, 2020 Maciej W. Rozycki 10 */ 11 #include <linux/console.h> 12 #include <linux/export.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/ioport.h> 16 #include <linux/irq.h> 17 #include <linux/irqnr.h> 18 #include <linux/memblock.h> 19 #include <linux/param.h> 20 #include <linux/percpu-defs.h> 21 #include <linux/sched.h> 22 #include <linux/spinlock.h> 23 #include <linux/types.h> 24 #include <linux/pm.h> 25 26 #include <asm/addrspace.h> 27 #include <asm/bootinfo.h> 28 #include <asm/cpu.h> 29 #include <asm/cpu-features.h> 30 #include <asm/cpu-type.h> 31 #include <asm/irq.h> 32 #include <asm/irq_cpu.h> 33 #include <asm/mipsregs.h> 34 #include <asm/page.h> 35 #include <asm/reboot.h> 36 #include <asm/sections.h> 37 #include <asm/time.h> 38 #include <asm/traps.h> 39 #include <asm/wbflush.h> 40 41 #include <asm/dec/interrupts.h> 42 #include <asm/dec/ioasic.h> 43 #include <asm/dec/ioasic_addrs.h> 44 #include <asm/dec/ioasic_ints.h> 45 #include <asm/dec/kn01.h> 46 #include <asm/dec/kn02.h> 47 #include <asm/dec/kn02ba.h> 48 #include <asm/dec/kn02ca.h> 49 #include <asm/dec/kn03.h> 50 #include <asm/dec/kn230.h> 51 #include <asm/dec/reset.h> 52 #include <asm/dec/system.h> 53 54 55 unsigned long dec_kn_slot_base, dec_kn_slot_size; 56 57 EXPORT_SYMBOL(dec_kn_slot_base); 58 EXPORT_SYMBOL(dec_kn_slot_size); 59 60 int dec_tc_bus; 61 62 DEFINE_SPINLOCK(ioasic_ssr_lock); 63 EXPORT_SYMBOL(ioasic_ssr_lock); 64 65 volatile u32 *ioasic_base; 66 67 EXPORT_SYMBOL(ioasic_base); 68 69 /* 70 * IRQ routing and priority tables. Priorities are set as follows: 71 * 72 * KN01 KN230 KN02 KN02-BA KN02-CA KN03 73 * 74 * MEMORY CPU CPU CPU ASIC CPU CPU 75 * RTC CPU CPU CPU ASIC CPU CPU 76 * DMA - - - ASIC ASIC ASIC 77 * SERIAL0 CPU CPU CSR ASIC ASIC ASIC 78 * SERIAL1 - - - ASIC - ASIC 79 * SCSI CPU CPU CSR ASIC ASIC ASIC 80 * ETHERNET CPU * CSR ASIC ASIC ASIC 81 * other - - - ASIC - - 82 * TC2 - - CSR CPU ASIC ASIC 83 * TC1 - - CSR CPU ASIC ASIC 84 * TC0 - - CSR CPU ASIC ASIC 85 * other - CPU - CPU ASIC ASIC 86 * other - - - - CPU CPU 87 * 88 * * -- shared with SCSI 89 */ 90 91 int dec_interrupt[DEC_NR_INTS] = { 92 [0 ... DEC_NR_INTS - 1] = -1 93 }; 94 95 EXPORT_SYMBOL(dec_interrupt); 96 97 int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = { 98 { { .i = ~0 }, { .p = dec_intr_unimplemented } }, 99 }; 100 int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = { 101 { { .i = ~0 }, { .p = asic_intr_unimplemented } }, 102 }; 103 int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU); 104 int *fpu_kstat_irq; 105 106 static irq_handler_t busirq_handler; 107 static unsigned int busirq_flags = IRQF_NO_THREAD; 108 109 /* 110 * Bus error (DBE/IBE exceptions and bus interrupts) handling setup. 111 */ 112 static void __init dec_be_init(void) 113 { 114 switch (mips_machtype) { 115 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ 116 mips_set_be_handler(dec_kn01_be_handler); 117 busirq_handler = dec_kn01_be_interrupt; 118 busirq_flags |= IRQF_SHARED; 119 dec_kn01_be_init(); 120 break; 121 case MACH_DS5000_1XX: /* DS5000/1xx 3min */ 122 case MACH_DS5000_XX: /* DS5000/xx Maxine */ 123 mips_set_be_handler(dec_kn02xa_be_handler); 124 busirq_handler = dec_kn02xa_be_interrupt; 125 dec_kn02xa_be_init(); 126 break; 127 case MACH_DS5000_200: /* DS5000/200 3max */ 128 case MACH_DS5000_2X0: /* DS5000/240 3max+ */ 129 case MACH_DS5900: /* DS5900 bigmax */ 130 mips_set_be_handler(dec_ecc_be_handler); 131 busirq_handler = dec_ecc_be_interrupt; 132 dec_ecc_be_init(); 133 break; 134 } 135 } 136 137 void __init plat_mem_setup(void) 138 { 139 board_be_init = dec_be_init; 140 141 wbflush_setup(); 142 143 _machine_restart = dec_machine_restart; 144 _machine_halt = dec_machine_halt; 145 pm_power_off = dec_machine_power_off; 146 147 ioport_resource.start = ~0UL; 148 ioport_resource.end = 0UL; 149 150 /* Stay away from the firmware working memory area for now. */ 151 memblock_reserve(PHYS_OFFSET, __pa_symbol(&_text) - PHYS_OFFSET); 152 } 153 154 /* 155 * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin) 156 * or DS3100 (aka Pmax). 157 */ 158 static int kn01_interrupt[DEC_NR_INTS] __initdata = { 159 [DEC_IRQ_CASCADE] = -1, 160 [DEC_IRQ_AB_RECV] = -1, 161 [DEC_IRQ_AB_XMIT] = -1, 162 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11), 163 [DEC_IRQ_ASC] = -1, 164 [DEC_IRQ_FLOPPY] = -1, 165 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 166 [DEC_IRQ_HALT] = -1, 167 [DEC_IRQ_ISDN] = -1, 168 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE), 169 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS), 170 [DEC_IRQ_PSU] = -1, 171 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC), 172 [DEC_IRQ_SCC0] = -1, 173 [DEC_IRQ_SCC1] = -1, 174 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII), 175 [DEC_IRQ_TC0] = -1, 176 [DEC_IRQ_TC1] = -1, 177 [DEC_IRQ_TC2] = -1, 178 [DEC_IRQ_TIMER] = -1, 179 [DEC_IRQ_VIDEO] = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO), 180 [DEC_IRQ_ASC_MERR] = -1, 181 [DEC_IRQ_ASC_ERR] = -1, 182 [DEC_IRQ_ASC_DMA] = -1, 183 [DEC_IRQ_FLOPPY_ERR] = -1, 184 [DEC_IRQ_ISDN_ERR] = -1, 185 [DEC_IRQ_ISDN_RXDMA] = -1, 186 [DEC_IRQ_ISDN_TXDMA] = -1, 187 [DEC_IRQ_LANCE_MERR] = -1, 188 [DEC_IRQ_SCC0A_RXERR] = -1, 189 [DEC_IRQ_SCC0A_RXDMA] = -1, 190 [DEC_IRQ_SCC0A_TXERR] = -1, 191 [DEC_IRQ_SCC0A_TXDMA] = -1, 192 [DEC_IRQ_AB_RXERR] = -1, 193 [DEC_IRQ_AB_RXDMA] = -1, 194 [DEC_IRQ_AB_TXERR] = -1, 195 [DEC_IRQ_AB_TXDMA] = -1, 196 [DEC_IRQ_SCC1A_RXERR] = -1, 197 [DEC_IRQ_SCC1A_RXDMA] = -1, 198 [DEC_IRQ_SCC1A_TXERR] = -1, 199 [DEC_IRQ_SCC1A_TXDMA] = -1, 200 }; 201 202 static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = { 203 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) }, 204 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } }, 205 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) }, 206 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } }, 207 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) }, 208 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } }, 209 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) }, 210 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } }, 211 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) }, 212 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } }, 213 { { .i = DEC_CPU_IRQ_ALL }, 214 { .p = cpu_all_int } }, 215 }; 216 217 static void __init dec_init_kn01(void) 218 { 219 /* IRQ routing. */ 220 memcpy(&dec_interrupt, &kn01_interrupt, 221 sizeof(kn01_interrupt)); 222 223 /* CPU IRQ priorities. */ 224 memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl, 225 sizeof(kn01_cpu_mask_nr_tbl)); 226 227 mips_cpu_irq_init(); 228 229 } /* dec_init_kn01 */ 230 231 232 /* 233 * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate. 234 */ 235 static int kn230_interrupt[DEC_NR_INTS] __initdata = { 236 [DEC_IRQ_CASCADE] = -1, 237 [DEC_IRQ_AB_RECV] = -1, 238 [DEC_IRQ_AB_XMIT] = -1, 239 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11), 240 [DEC_IRQ_ASC] = -1, 241 [DEC_IRQ_FLOPPY] = -1, 242 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 243 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT), 244 [DEC_IRQ_ISDN] = -1, 245 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE), 246 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS), 247 [DEC_IRQ_PSU] = -1, 248 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC), 249 [DEC_IRQ_SCC0] = -1, 250 [DEC_IRQ_SCC1] = -1, 251 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII), 252 [DEC_IRQ_TC0] = -1, 253 [DEC_IRQ_TC1] = -1, 254 [DEC_IRQ_TC2] = -1, 255 [DEC_IRQ_TIMER] = -1, 256 [DEC_IRQ_VIDEO] = -1, 257 [DEC_IRQ_ASC_MERR] = -1, 258 [DEC_IRQ_ASC_ERR] = -1, 259 [DEC_IRQ_ASC_DMA] = -1, 260 [DEC_IRQ_FLOPPY_ERR] = -1, 261 [DEC_IRQ_ISDN_ERR] = -1, 262 [DEC_IRQ_ISDN_RXDMA] = -1, 263 [DEC_IRQ_ISDN_TXDMA] = -1, 264 [DEC_IRQ_LANCE_MERR] = -1, 265 [DEC_IRQ_SCC0A_RXERR] = -1, 266 [DEC_IRQ_SCC0A_RXDMA] = -1, 267 [DEC_IRQ_SCC0A_TXERR] = -1, 268 [DEC_IRQ_SCC0A_TXDMA] = -1, 269 [DEC_IRQ_AB_RXERR] = -1, 270 [DEC_IRQ_AB_RXDMA] = -1, 271 [DEC_IRQ_AB_TXERR] = -1, 272 [DEC_IRQ_AB_TXDMA] = -1, 273 [DEC_IRQ_SCC1A_RXERR] = -1, 274 [DEC_IRQ_SCC1A_RXDMA] = -1, 275 [DEC_IRQ_SCC1A_TXERR] = -1, 276 [DEC_IRQ_SCC1A_TXDMA] = -1, 277 }; 278 279 static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = { 280 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) }, 281 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } }, 282 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) }, 283 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } }, 284 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) }, 285 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } }, 286 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) }, 287 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } }, 288 { { .i = DEC_CPU_IRQ_ALL }, 289 { .p = cpu_all_int } }, 290 }; 291 292 static void __init dec_init_kn230(void) 293 { 294 /* IRQ routing. */ 295 memcpy(&dec_interrupt, &kn230_interrupt, 296 sizeof(kn230_interrupt)); 297 298 /* CPU IRQ priorities. */ 299 memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl, 300 sizeof(kn230_cpu_mask_nr_tbl)); 301 302 mips_cpu_irq_init(); 303 304 } /* dec_init_kn230 */ 305 306 307 /* 308 * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max. 309 */ 310 static int kn02_interrupt[DEC_NR_INTS] __initdata = { 311 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE), 312 [DEC_IRQ_AB_RECV] = -1, 313 [DEC_IRQ_AB_XMIT] = -1, 314 [DEC_IRQ_DZ11] = KN02_IRQ_NR(KN02_CSR_INR_DZ11), 315 [DEC_IRQ_ASC] = KN02_IRQ_NR(KN02_CSR_INR_ASC), 316 [DEC_IRQ_FLOPPY] = -1, 317 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 318 [DEC_IRQ_HALT] = -1, 319 [DEC_IRQ_ISDN] = -1, 320 [DEC_IRQ_LANCE] = KN02_IRQ_NR(KN02_CSR_INR_LANCE), 321 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS), 322 [DEC_IRQ_PSU] = -1, 323 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC), 324 [DEC_IRQ_SCC0] = -1, 325 [DEC_IRQ_SCC1] = -1, 326 [DEC_IRQ_SII] = -1, 327 [DEC_IRQ_TC0] = KN02_IRQ_NR(KN02_CSR_INR_TC0), 328 [DEC_IRQ_TC1] = KN02_IRQ_NR(KN02_CSR_INR_TC1), 329 [DEC_IRQ_TC2] = KN02_IRQ_NR(KN02_CSR_INR_TC2), 330 [DEC_IRQ_TIMER] = -1, 331 [DEC_IRQ_VIDEO] = -1, 332 [DEC_IRQ_ASC_MERR] = -1, 333 [DEC_IRQ_ASC_ERR] = -1, 334 [DEC_IRQ_ASC_DMA] = -1, 335 [DEC_IRQ_FLOPPY_ERR] = -1, 336 [DEC_IRQ_ISDN_ERR] = -1, 337 [DEC_IRQ_ISDN_RXDMA] = -1, 338 [DEC_IRQ_ISDN_TXDMA] = -1, 339 [DEC_IRQ_LANCE_MERR] = -1, 340 [DEC_IRQ_SCC0A_RXERR] = -1, 341 [DEC_IRQ_SCC0A_RXDMA] = -1, 342 [DEC_IRQ_SCC0A_TXERR] = -1, 343 [DEC_IRQ_SCC0A_TXDMA] = -1, 344 [DEC_IRQ_AB_RXERR] = -1, 345 [DEC_IRQ_AB_RXDMA] = -1, 346 [DEC_IRQ_AB_TXERR] = -1, 347 [DEC_IRQ_AB_TXDMA] = -1, 348 [DEC_IRQ_SCC1A_RXERR] = -1, 349 [DEC_IRQ_SCC1A_RXDMA] = -1, 350 [DEC_IRQ_SCC1A_TXERR] = -1, 351 [DEC_IRQ_SCC1A_TXDMA] = -1, 352 }; 353 354 static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = { 355 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) }, 356 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } }, 357 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) }, 358 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } }, 359 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) }, 360 { .p = kn02_io_int } }, 361 { { .i = DEC_CPU_IRQ_ALL }, 362 { .p = cpu_all_int } }, 363 }; 364 365 static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = { 366 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) }, 367 { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } }, 368 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) }, 369 { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } }, 370 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) }, 371 { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } }, 372 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) }, 373 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } }, 374 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) }, 375 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } }, 376 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) }, 377 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } }, 378 { { .i = KN02_IRQ_ALL }, 379 { .p = kn02_all_int } }, 380 }; 381 382 static void __init dec_init_kn02(void) 383 { 384 /* IRQ routing. */ 385 memcpy(&dec_interrupt, &kn02_interrupt, 386 sizeof(kn02_interrupt)); 387 388 /* CPU IRQ priorities. */ 389 memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl, 390 sizeof(kn02_cpu_mask_nr_tbl)); 391 392 /* KN02 CSR IRQ priorities. */ 393 memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl, 394 sizeof(kn02_asic_mask_nr_tbl)); 395 396 mips_cpu_irq_init(); 397 init_kn02_irqs(KN02_IRQ_BASE); 398 399 } /* dec_init_kn02 */ 400 401 402 /* 403 * Machine-specific initialisation for KN02-BA, aka DS5000/1xx 404 * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka 405 * DS5000/150, aka 4min. 406 */ 407 static int kn02ba_interrupt[DEC_NR_INTS] __initdata = { 408 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE), 409 [DEC_IRQ_AB_RECV] = -1, 410 [DEC_IRQ_AB_XMIT] = -1, 411 [DEC_IRQ_DZ11] = -1, 412 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02BA_IO_INR_ASC), 413 [DEC_IRQ_FLOPPY] = -1, 414 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 415 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT), 416 [DEC_IRQ_ISDN] = -1, 417 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02BA_IO_INR_LANCE), 418 [DEC_IRQ_BUS] = IO_IRQ_NR(KN02BA_IO_INR_BUS), 419 [DEC_IRQ_PSU] = IO_IRQ_NR(KN02BA_IO_INR_PSU), 420 [DEC_IRQ_RTC] = IO_IRQ_NR(KN02BA_IO_INR_RTC), 421 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02BA_IO_INR_SCC0), 422 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN02BA_IO_INR_SCC1), 423 [DEC_IRQ_SII] = -1, 424 [DEC_IRQ_TC0] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0), 425 [DEC_IRQ_TC1] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1), 426 [DEC_IRQ_TC2] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2), 427 [DEC_IRQ_TIMER] = -1, 428 [DEC_IRQ_VIDEO] = -1, 429 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), 430 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), 431 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), 432 [DEC_IRQ_FLOPPY_ERR] = -1, 433 [DEC_IRQ_ISDN_ERR] = -1, 434 [DEC_IRQ_ISDN_RXDMA] = -1, 435 [DEC_IRQ_ISDN_TXDMA] = -1, 436 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), 437 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), 438 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), 439 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), 440 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), 441 [DEC_IRQ_AB_RXERR] = -1, 442 [DEC_IRQ_AB_RXDMA] = -1, 443 [DEC_IRQ_AB_TXERR] = -1, 444 [DEC_IRQ_AB_TXDMA] = -1, 445 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR), 446 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA), 447 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR), 448 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA), 449 }; 450 451 static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = { 452 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) }, 453 { .p = kn02xa_io_int } }, 454 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) }, 455 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } }, 456 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) }, 457 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } }, 458 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) }, 459 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } }, 460 { { .i = DEC_CPU_IRQ_ALL }, 461 { .p = cpu_all_int } }, 462 }; 463 464 static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = { 465 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) }, 466 { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } }, 467 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) }, 468 { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } }, 469 { { .i = IO_IRQ_DMA }, 470 { .p = asic_dma_int } }, 471 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) }, 472 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } }, 473 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) }, 474 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } }, 475 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) }, 476 { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } }, 477 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) }, 478 { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } }, 479 { { .i = IO_IRQ_ALL }, 480 { .p = asic_all_int } }, 481 }; 482 483 static void __init dec_init_kn02ba(void) 484 { 485 /* IRQ routing. */ 486 memcpy(&dec_interrupt, &kn02ba_interrupt, 487 sizeof(kn02ba_interrupt)); 488 489 /* CPU IRQ priorities. */ 490 memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl, 491 sizeof(kn02ba_cpu_mask_nr_tbl)); 492 493 /* I/O ASIC IRQ priorities. */ 494 memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl, 495 sizeof(kn02ba_asic_mask_nr_tbl)); 496 497 mips_cpu_irq_init(); 498 init_ioasic_irqs(IO_IRQ_BASE); 499 500 } /* dec_init_kn02ba */ 501 502 503 /* 504 * Machine-specific initialisation for KN02-CA, aka DS5000/xx, 505 * (xx = 20, 25, 33), aka MAXine. Also applies to KN04(-CA), aka 506 * DS5000/50, aka 4MAXine. 507 */ 508 static int kn02ca_interrupt[DEC_NR_INTS] __initdata = { 509 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE), 510 [DEC_IRQ_AB_RECV] = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV), 511 [DEC_IRQ_AB_XMIT] = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT), 512 [DEC_IRQ_DZ11] = -1, 513 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02CA_IO_INR_ASC), 514 [DEC_IRQ_FLOPPY] = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY), 515 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 516 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT), 517 [DEC_IRQ_ISDN] = IO_IRQ_NR(KN02CA_IO_INR_ISDN), 518 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02CA_IO_INR_LANCE), 519 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS), 520 [DEC_IRQ_PSU] = -1, 521 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC), 522 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02CA_IO_INR_SCC0), 523 [DEC_IRQ_SCC1] = -1, 524 [DEC_IRQ_SII] = -1, 525 [DEC_IRQ_TC0] = IO_IRQ_NR(KN02CA_IO_INR_TC0), 526 [DEC_IRQ_TC1] = IO_IRQ_NR(KN02CA_IO_INR_TC1), 527 [DEC_IRQ_TC2] = -1, 528 [DEC_IRQ_TIMER] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER), 529 [DEC_IRQ_VIDEO] = IO_IRQ_NR(KN02CA_IO_INR_VIDEO), 530 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), 531 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), 532 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), 533 [DEC_IRQ_FLOPPY_ERR] = IO_IRQ_NR(IO_INR_FLOPPY_ERR), 534 [DEC_IRQ_ISDN_ERR] = IO_IRQ_NR(IO_INR_ISDN_ERR), 535 [DEC_IRQ_ISDN_RXDMA] = IO_IRQ_NR(IO_INR_ISDN_RXDMA), 536 [DEC_IRQ_ISDN_TXDMA] = IO_IRQ_NR(IO_INR_ISDN_TXDMA), 537 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), 538 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), 539 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), 540 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), 541 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), 542 [DEC_IRQ_AB_RXERR] = IO_IRQ_NR(IO_INR_AB_RXERR), 543 [DEC_IRQ_AB_RXDMA] = IO_IRQ_NR(IO_INR_AB_RXDMA), 544 [DEC_IRQ_AB_TXERR] = IO_IRQ_NR(IO_INR_AB_TXERR), 545 [DEC_IRQ_AB_TXDMA] = IO_IRQ_NR(IO_INR_AB_TXDMA), 546 [DEC_IRQ_SCC1A_RXERR] = -1, 547 [DEC_IRQ_SCC1A_RXDMA] = -1, 548 [DEC_IRQ_SCC1A_TXERR] = -1, 549 [DEC_IRQ_SCC1A_TXDMA] = -1, 550 }; 551 552 static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = { 553 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) }, 554 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } }, 555 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) }, 556 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } }, 557 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) }, 558 { .p = kn02xa_io_int } }, 559 { { .i = DEC_CPU_IRQ_ALL }, 560 { .p = cpu_all_int } }, 561 }; 562 563 static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = { 564 { { .i = IO_IRQ_DMA }, 565 { .p = asic_dma_int } }, 566 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) }, 567 { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } }, 568 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) }, 569 { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } }, 570 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) }, 571 { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } }, 572 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) }, 573 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } }, 574 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) }, 575 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } }, 576 { { .i = IO_IRQ_ALL }, 577 { .p = asic_all_int } }, 578 }; 579 580 static void __init dec_init_kn02ca(void) 581 { 582 /* IRQ routing. */ 583 memcpy(&dec_interrupt, &kn02ca_interrupt, 584 sizeof(kn02ca_interrupt)); 585 586 /* CPU IRQ priorities. */ 587 memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl, 588 sizeof(kn02ca_cpu_mask_nr_tbl)); 589 590 /* I/O ASIC IRQ priorities. */ 591 memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl, 592 sizeof(kn02ca_asic_mask_nr_tbl)); 593 594 mips_cpu_irq_init(); 595 init_ioasic_irqs(IO_IRQ_BASE); 596 597 } /* dec_init_kn02ca */ 598 599 600 /* 601 * Machine-specific initialisation for KN03, aka DS5000/240, 602 * aka 3max+ and DS5900, aka BIGmax. Also applies to KN05, aka 603 * DS5000/260, aka 4max+ and DS5900/260. 604 */ 605 static int kn03_interrupt[DEC_NR_INTS] __initdata = { 606 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE), 607 [DEC_IRQ_AB_RECV] = -1, 608 [DEC_IRQ_AB_XMIT] = -1, 609 [DEC_IRQ_DZ11] = -1, 610 [DEC_IRQ_ASC] = IO_IRQ_NR(KN03_IO_INR_ASC), 611 [DEC_IRQ_FLOPPY] = -1, 612 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 613 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT), 614 [DEC_IRQ_ISDN] = -1, 615 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN03_IO_INR_LANCE), 616 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS), 617 [DEC_IRQ_PSU] = IO_IRQ_NR(KN03_IO_INR_PSU), 618 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC), 619 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN03_IO_INR_SCC0), 620 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN03_IO_INR_SCC1), 621 [DEC_IRQ_SII] = -1, 622 [DEC_IRQ_TC0] = IO_IRQ_NR(KN03_IO_INR_TC0), 623 [DEC_IRQ_TC1] = IO_IRQ_NR(KN03_IO_INR_TC1), 624 [DEC_IRQ_TC2] = IO_IRQ_NR(KN03_IO_INR_TC2), 625 [DEC_IRQ_TIMER] = -1, 626 [DEC_IRQ_VIDEO] = -1, 627 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), 628 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), 629 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), 630 [DEC_IRQ_FLOPPY_ERR] = -1, 631 [DEC_IRQ_ISDN_ERR] = -1, 632 [DEC_IRQ_ISDN_RXDMA] = -1, 633 [DEC_IRQ_ISDN_TXDMA] = -1, 634 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), 635 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), 636 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), 637 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), 638 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), 639 [DEC_IRQ_AB_RXERR] = -1, 640 [DEC_IRQ_AB_RXDMA] = -1, 641 [DEC_IRQ_AB_TXERR] = -1, 642 [DEC_IRQ_AB_TXDMA] = -1, 643 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR), 644 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA), 645 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR), 646 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA), 647 }; 648 649 static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = { 650 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) }, 651 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } }, 652 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) }, 653 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } }, 654 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) }, 655 { .p = kn03_io_int } }, 656 { { .i = DEC_CPU_IRQ_ALL }, 657 { .p = cpu_all_int } }, 658 }; 659 660 static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = { 661 { { .i = IO_IRQ_DMA }, 662 { .p = asic_dma_int } }, 663 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) }, 664 { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } }, 665 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) }, 666 { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } }, 667 { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) }, 668 { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } }, 669 { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) }, 670 { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } }, 671 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) }, 672 { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } }, 673 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) }, 674 { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } }, 675 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) }, 676 { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } }, 677 { { .i = IO_IRQ_ALL }, 678 { .p = asic_all_int } }, 679 }; 680 681 static void __init dec_init_kn03(void) 682 { 683 /* IRQ routing. */ 684 memcpy(&dec_interrupt, &kn03_interrupt, 685 sizeof(kn03_interrupt)); 686 687 /* CPU IRQ priorities. */ 688 memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl, 689 sizeof(kn03_cpu_mask_nr_tbl)); 690 691 /* I/O ASIC IRQ priorities. */ 692 memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl, 693 sizeof(kn03_asic_mask_nr_tbl)); 694 695 mips_cpu_irq_init(); 696 init_ioasic_irqs(IO_IRQ_BASE); 697 698 } /* dec_init_kn03 */ 699 700 701 void __init arch_init_irq(void) 702 { 703 switch (mips_machtype) { 704 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ 705 dec_init_kn01(); 706 break; 707 case MACH_DS5100: /* DS5100 MIPSmate */ 708 dec_init_kn230(); 709 break; 710 case MACH_DS5000_200: /* DS5000/200 3max */ 711 dec_init_kn02(); 712 break; 713 case MACH_DS5000_1XX: /* DS5000/1xx 3min */ 714 dec_init_kn02ba(); 715 break; 716 case MACH_DS5000_2X0: /* DS5000/240 3max+ */ 717 case MACH_DS5900: /* DS5900 bigmax */ 718 dec_init_kn03(); 719 break; 720 case MACH_DS5000_XX: /* Personal DS5000/xx */ 721 dec_init_kn02ca(); 722 break; 723 case MACH_DS5800: /* DS5800 Isis */ 724 panic("Don't know how to set this up!"); 725 break; 726 case MACH_DS5400: /* DS5400 MIPSfair */ 727 panic("Don't know how to set this up!"); 728 break; 729 case MACH_DS5500: /* DS5500 MIPSfair-2 */ 730 panic("Don't know how to set this up!"); 731 break; 732 } 733 734 /* Free the FPU interrupt if the exception is present. */ 735 if (!cpu_has_nofpuex) { 736 cpu_fpu_mask = 0; 737 dec_interrupt[DEC_IRQ_FPU] = -1; 738 } 739 /* Free the halt interrupt unused on R4k systems. */ 740 if (current_cpu_type() == CPU_R4000SC || 741 current_cpu_type() == CPU_R4400SC) 742 dec_interrupt[DEC_IRQ_HALT] = -1; 743 744 /* Register board interrupts: FPU and cascade. */ 745 if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT) && 746 dec_interrupt[DEC_IRQ_FPU] >= 0 && cpu_has_fpu) { 747 struct irq_desc *desc_fpu; 748 int irq_fpu; 749 750 irq_fpu = dec_interrupt[DEC_IRQ_FPU]; 751 if (request_irq(irq_fpu, no_action, IRQF_NO_THREAD, "fpu", 752 NULL)) 753 pr_err("Failed to register fpu interrupt\n"); 754 desc_fpu = irq_to_desc(irq_fpu); 755 fpu_kstat_irq = this_cpu_ptr(&desc_fpu->kstat_irqs->cnt); 756 } 757 if (dec_interrupt[DEC_IRQ_CASCADE] >= 0) { 758 if (request_irq(dec_interrupt[DEC_IRQ_CASCADE], no_action, 759 IRQF_NO_THREAD, "cascade", NULL)) 760 pr_err("Failed to register cascade interrupt\n"); 761 } 762 /* Register the bus error interrupt. */ 763 if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq_handler) { 764 if (request_irq(dec_interrupt[DEC_IRQ_BUS], busirq_handler, 765 busirq_flags, "bus error", busirq_handler)) 766 pr_err("Failed to register bus error interrupt\n"); 767 } 768 /* Register the HALT interrupt. */ 769 if (dec_interrupt[DEC_IRQ_HALT] >= 0) { 770 if (request_irq(dec_interrupt[DEC_IRQ_HALT], dec_intr_halt, 771 IRQF_NO_THREAD, "halt", NULL)) 772 pr_err("Failed to register halt interrupt\n"); 773 } 774 } 775