1 /* 2 * System-specific setup, especially interrupts. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1998 Harald Koerfgen 9 * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki 10 */ 11 #include <linux/console.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/ioport.h> 15 #include <linux/module.h> 16 #include <linux/param.h> 17 #include <linux/sched.h> 18 #include <linux/spinlock.h> 19 #include <linux/types.h> 20 #include <linux/pm.h> 21 22 #include <asm/bootinfo.h> 23 #include <asm/cpu.h> 24 #include <asm/cpu-features.h> 25 #include <asm/irq.h> 26 #include <asm/irq_cpu.h> 27 #include <asm/mipsregs.h> 28 #include <asm/reboot.h> 29 #include <asm/time.h> 30 #include <asm/traps.h> 31 #include <asm/wbflush.h> 32 33 #include <asm/dec/interrupts.h> 34 #include <asm/dec/ioasic.h> 35 #include <asm/dec/ioasic_addrs.h> 36 #include <asm/dec/ioasic_ints.h> 37 #include <asm/dec/kn01.h> 38 #include <asm/dec/kn02.h> 39 #include <asm/dec/kn02ba.h> 40 #include <asm/dec/kn02ca.h> 41 #include <asm/dec/kn03.h> 42 #include <asm/dec/kn230.h> 43 #include <asm/dec/system.h> 44 45 46 extern void dec_machine_restart(char *command); 47 extern void dec_machine_halt(void); 48 extern void dec_machine_power_off(void); 49 extern irqreturn_t dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs); 50 51 unsigned long dec_kn_slot_base, dec_kn_slot_size; 52 53 EXPORT_SYMBOL(dec_kn_slot_base); 54 EXPORT_SYMBOL(dec_kn_slot_size); 55 56 spinlock_t ioasic_ssr_lock; 57 58 volatile u32 *ioasic_base; 59 60 EXPORT_SYMBOL(ioasic_base); 61 62 /* 63 * IRQ routing and priority tables. Priorites are set as follows: 64 * 65 * KN01 KN230 KN02 KN02-BA KN02-CA KN03 66 * 67 * MEMORY CPU CPU CPU ASIC CPU CPU 68 * RTC CPU CPU CPU ASIC CPU CPU 69 * DMA - - - ASIC ASIC ASIC 70 * SERIAL0 CPU CPU CSR ASIC ASIC ASIC 71 * SERIAL1 - - - ASIC - ASIC 72 * SCSI CPU CPU CSR ASIC ASIC ASIC 73 * ETHERNET CPU * CSR ASIC ASIC ASIC 74 * other - - - ASIC - - 75 * TC2 - - CSR CPU ASIC ASIC 76 * TC1 - - CSR CPU ASIC ASIC 77 * TC0 - - CSR CPU ASIC ASIC 78 * other - CPU - CPU ASIC ASIC 79 * other - - - - CPU CPU 80 * 81 * * -- shared with SCSI 82 */ 83 84 int dec_interrupt[DEC_NR_INTS] = { 85 [0 ... DEC_NR_INTS - 1] = -1 86 }; 87 88 EXPORT_SYMBOL(dec_interrupt); 89 90 int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = { 91 { { .i = ~0 }, { .p = dec_intr_unimplemented } }, 92 }; 93 int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = { 94 { { .i = ~0 }, { .p = asic_intr_unimplemented } }, 95 }; 96 int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU); 97 98 static struct irqaction ioirq = { 99 .handler = no_action, 100 .name = "cascade", 101 }; 102 static struct irqaction fpuirq = { 103 .handler = no_action, 104 .name = "fpu", 105 }; 106 107 static struct irqaction busirq = { 108 .flags = IRQF_DISABLED, 109 .name = "bus error", 110 }; 111 112 static struct irqaction haltirq = { 113 .handler = dec_intr_halt, 114 .name = "halt", 115 }; 116 117 118 /* 119 * Bus error (DBE/IBE exceptions and bus interrupts) handling setup. 120 */ 121 static void __init dec_be_init(void) 122 { 123 switch (mips_machtype) { 124 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ 125 board_be_handler = dec_kn01_be_handler; 126 busirq.handler = dec_kn01_be_interrupt; 127 busirq.flags |= IRQF_SHARED; 128 dec_kn01_be_init(); 129 break; 130 case MACH_DS5000_1XX: /* DS5000/1xx 3min */ 131 case MACH_DS5000_XX: /* DS5000/xx Maxine */ 132 board_be_handler = dec_kn02xa_be_handler; 133 busirq.handler = dec_kn02xa_be_interrupt; 134 dec_kn02xa_be_init(); 135 break; 136 case MACH_DS5000_200: /* DS5000/200 3max */ 137 case MACH_DS5000_2X0: /* DS5000/240 3max+ */ 138 case MACH_DS5900: /* DS5900 bigmax */ 139 board_be_handler = dec_ecc_be_handler; 140 busirq.handler = dec_ecc_be_interrupt; 141 dec_ecc_be_init(); 142 break; 143 } 144 } 145 146 147 extern void dec_time_init(void); 148 149 void __init plat_mem_setup(void) 150 { 151 board_be_init = dec_be_init; 152 board_time_init = dec_time_init; 153 154 wbflush_setup(); 155 156 _machine_restart = dec_machine_restart; 157 _machine_halt = dec_machine_halt; 158 pm_power_off = dec_machine_power_off; 159 160 ioport_resource.start = ~0UL; 161 ioport_resource.end = 0UL; 162 } 163 164 /* 165 * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin) 166 * or DS3100 (aka Pmax). 167 */ 168 static int kn01_interrupt[DEC_NR_INTS] __initdata = { 169 [DEC_IRQ_CASCADE] = -1, 170 [DEC_IRQ_AB_RECV] = -1, 171 [DEC_IRQ_AB_XMIT] = -1, 172 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11), 173 [DEC_IRQ_ASC] = -1, 174 [DEC_IRQ_FLOPPY] = -1, 175 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 176 [DEC_IRQ_HALT] = -1, 177 [DEC_IRQ_ISDN] = -1, 178 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE), 179 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS), 180 [DEC_IRQ_PSU] = -1, 181 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC), 182 [DEC_IRQ_SCC0] = -1, 183 [DEC_IRQ_SCC1] = -1, 184 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII), 185 [DEC_IRQ_TC0] = -1, 186 [DEC_IRQ_TC1] = -1, 187 [DEC_IRQ_TC2] = -1, 188 [DEC_IRQ_TIMER] = -1, 189 [DEC_IRQ_VIDEO] = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO), 190 [DEC_IRQ_ASC_MERR] = -1, 191 [DEC_IRQ_ASC_ERR] = -1, 192 [DEC_IRQ_ASC_DMA] = -1, 193 [DEC_IRQ_FLOPPY_ERR] = -1, 194 [DEC_IRQ_ISDN_ERR] = -1, 195 [DEC_IRQ_ISDN_RXDMA] = -1, 196 [DEC_IRQ_ISDN_TXDMA] = -1, 197 [DEC_IRQ_LANCE_MERR] = -1, 198 [DEC_IRQ_SCC0A_RXERR] = -1, 199 [DEC_IRQ_SCC0A_RXDMA] = -1, 200 [DEC_IRQ_SCC0A_TXERR] = -1, 201 [DEC_IRQ_SCC0A_TXDMA] = -1, 202 [DEC_IRQ_AB_RXERR] = -1, 203 [DEC_IRQ_AB_RXDMA] = -1, 204 [DEC_IRQ_AB_TXERR] = -1, 205 [DEC_IRQ_AB_TXDMA] = -1, 206 [DEC_IRQ_SCC1A_RXERR] = -1, 207 [DEC_IRQ_SCC1A_RXDMA] = -1, 208 [DEC_IRQ_SCC1A_TXERR] = -1, 209 [DEC_IRQ_SCC1A_TXDMA] = -1, 210 }; 211 212 static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = { 213 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) }, 214 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } }, 215 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) }, 216 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } }, 217 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) }, 218 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } }, 219 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) }, 220 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } }, 221 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) }, 222 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } }, 223 { { .i = DEC_CPU_IRQ_ALL }, 224 { .p = cpu_all_int } }, 225 }; 226 227 static void __init dec_init_kn01(void) 228 { 229 /* IRQ routing. */ 230 memcpy(&dec_interrupt, &kn01_interrupt, 231 sizeof(kn01_interrupt)); 232 233 /* CPU IRQ priorities. */ 234 memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl, 235 sizeof(kn01_cpu_mask_nr_tbl)); 236 237 mips_cpu_irq_init(DEC_CPU_IRQ_BASE); 238 239 } /* dec_init_kn01 */ 240 241 242 /* 243 * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate. 244 */ 245 static int kn230_interrupt[DEC_NR_INTS] __initdata = { 246 [DEC_IRQ_CASCADE] = -1, 247 [DEC_IRQ_AB_RECV] = -1, 248 [DEC_IRQ_AB_XMIT] = -1, 249 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11), 250 [DEC_IRQ_ASC] = -1, 251 [DEC_IRQ_FLOPPY] = -1, 252 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 253 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT), 254 [DEC_IRQ_ISDN] = -1, 255 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE), 256 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS), 257 [DEC_IRQ_PSU] = -1, 258 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC), 259 [DEC_IRQ_SCC0] = -1, 260 [DEC_IRQ_SCC1] = -1, 261 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII), 262 [DEC_IRQ_TC0] = -1, 263 [DEC_IRQ_TC1] = -1, 264 [DEC_IRQ_TC2] = -1, 265 [DEC_IRQ_TIMER] = -1, 266 [DEC_IRQ_VIDEO] = -1, 267 [DEC_IRQ_ASC_MERR] = -1, 268 [DEC_IRQ_ASC_ERR] = -1, 269 [DEC_IRQ_ASC_DMA] = -1, 270 [DEC_IRQ_FLOPPY_ERR] = -1, 271 [DEC_IRQ_ISDN_ERR] = -1, 272 [DEC_IRQ_ISDN_RXDMA] = -1, 273 [DEC_IRQ_ISDN_TXDMA] = -1, 274 [DEC_IRQ_LANCE_MERR] = -1, 275 [DEC_IRQ_SCC0A_RXERR] = -1, 276 [DEC_IRQ_SCC0A_RXDMA] = -1, 277 [DEC_IRQ_SCC0A_TXERR] = -1, 278 [DEC_IRQ_SCC0A_TXDMA] = -1, 279 [DEC_IRQ_AB_RXERR] = -1, 280 [DEC_IRQ_AB_RXDMA] = -1, 281 [DEC_IRQ_AB_TXERR] = -1, 282 [DEC_IRQ_AB_TXDMA] = -1, 283 [DEC_IRQ_SCC1A_RXERR] = -1, 284 [DEC_IRQ_SCC1A_RXDMA] = -1, 285 [DEC_IRQ_SCC1A_TXERR] = -1, 286 [DEC_IRQ_SCC1A_TXDMA] = -1, 287 }; 288 289 static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = { 290 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) }, 291 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } }, 292 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) }, 293 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } }, 294 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) }, 295 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } }, 296 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) }, 297 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } }, 298 { { .i = DEC_CPU_IRQ_ALL }, 299 { .p = cpu_all_int } }, 300 }; 301 302 static void __init dec_init_kn230(void) 303 { 304 /* IRQ routing. */ 305 memcpy(&dec_interrupt, &kn230_interrupt, 306 sizeof(kn230_interrupt)); 307 308 /* CPU IRQ priorities. */ 309 memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl, 310 sizeof(kn230_cpu_mask_nr_tbl)); 311 312 mips_cpu_irq_init(DEC_CPU_IRQ_BASE); 313 314 } /* dec_init_kn230 */ 315 316 317 /* 318 * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max. 319 */ 320 static int kn02_interrupt[DEC_NR_INTS] __initdata = { 321 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE), 322 [DEC_IRQ_AB_RECV] = -1, 323 [DEC_IRQ_AB_XMIT] = -1, 324 [DEC_IRQ_DZ11] = KN02_IRQ_NR(KN02_CSR_INR_DZ11), 325 [DEC_IRQ_ASC] = KN02_IRQ_NR(KN02_CSR_INR_ASC), 326 [DEC_IRQ_FLOPPY] = -1, 327 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 328 [DEC_IRQ_HALT] = -1, 329 [DEC_IRQ_ISDN] = -1, 330 [DEC_IRQ_LANCE] = KN02_IRQ_NR(KN02_CSR_INR_LANCE), 331 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS), 332 [DEC_IRQ_PSU] = -1, 333 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC), 334 [DEC_IRQ_SCC0] = -1, 335 [DEC_IRQ_SCC1] = -1, 336 [DEC_IRQ_SII] = -1, 337 [DEC_IRQ_TC0] = KN02_IRQ_NR(KN02_CSR_INR_TC0), 338 [DEC_IRQ_TC1] = KN02_IRQ_NR(KN02_CSR_INR_TC1), 339 [DEC_IRQ_TC2] = KN02_IRQ_NR(KN02_CSR_INR_TC2), 340 [DEC_IRQ_TIMER] = -1, 341 [DEC_IRQ_VIDEO] = -1, 342 [DEC_IRQ_ASC_MERR] = -1, 343 [DEC_IRQ_ASC_ERR] = -1, 344 [DEC_IRQ_ASC_DMA] = -1, 345 [DEC_IRQ_FLOPPY_ERR] = -1, 346 [DEC_IRQ_ISDN_ERR] = -1, 347 [DEC_IRQ_ISDN_RXDMA] = -1, 348 [DEC_IRQ_ISDN_TXDMA] = -1, 349 [DEC_IRQ_LANCE_MERR] = -1, 350 [DEC_IRQ_SCC0A_RXERR] = -1, 351 [DEC_IRQ_SCC0A_RXDMA] = -1, 352 [DEC_IRQ_SCC0A_TXERR] = -1, 353 [DEC_IRQ_SCC0A_TXDMA] = -1, 354 [DEC_IRQ_AB_RXERR] = -1, 355 [DEC_IRQ_AB_RXDMA] = -1, 356 [DEC_IRQ_AB_TXERR] = -1, 357 [DEC_IRQ_AB_TXDMA] = -1, 358 [DEC_IRQ_SCC1A_RXERR] = -1, 359 [DEC_IRQ_SCC1A_RXDMA] = -1, 360 [DEC_IRQ_SCC1A_TXERR] = -1, 361 [DEC_IRQ_SCC1A_TXDMA] = -1, 362 }; 363 364 static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = { 365 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) }, 366 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } }, 367 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) }, 368 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } }, 369 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) }, 370 { .p = kn02_io_int } }, 371 { { .i = DEC_CPU_IRQ_ALL }, 372 { .p = cpu_all_int } }, 373 }; 374 375 static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = { 376 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) }, 377 { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } }, 378 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) }, 379 { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } }, 380 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) }, 381 { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } }, 382 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) }, 383 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } }, 384 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) }, 385 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } }, 386 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) }, 387 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } }, 388 { { .i = KN02_IRQ_ALL }, 389 { .p = kn02_all_int } }, 390 }; 391 392 static void __init dec_init_kn02(void) 393 { 394 /* IRQ routing. */ 395 memcpy(&dec_interrupt, &kn02_interrupt, 396 sizeof(kn02_interrupt)); 397 398 /* CPU IRQ priorities. */ 399 memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl, 400 sizeof(kn02_cpu_mask_nr_tbl)); 401 402 /* KN02 CSR IRQ priorities. */ 403 memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl, 404 sizeof(kn02_asic_mask_nr_tbl)); 405 406 mips_cpu_irq_init(DEC_CPU_IRQ_BASE); 407 init_kn02_irqs(KN02_IRQ_BASE); 408 409 } /* dec_init_kn02 */ 410 411 412 /* 413 * Machine-specific initialisation for KN02-BA, aka DS5000/1xx 414 * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka 415 * DS5000/150, aka 4min. 416 */ 417 static int kn02ba_interrupt[DEC_NR_INTS] __initdata = { 418 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE), 419 [DEC_IRQ_AB_RECV] = -1, 420 [DEC_IRQ_AB_XMIT] = -1, 421 [DEC_IRQ_DZ11] = -1, 422 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02BA_IO_INR_ASC), 423 [DEC_IRQ_FLOPPY] = -1, 424 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 425 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT), 426 [DEC_IRQ_ISDN] = -1, 427 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02BA_IO_INR_LANCE), 428 [DEC_IRQ_BUS] = IO_IRQ_NR(KN02BA_IO_INR_BUS), 429 [DEC_IRQ_PSU] = IO_IRQ_NR(KN02BA_IO_INR_PSU), 430 [DEC_IRQ_RTC] = IO_IRQ_NR(KN02BA_IO_INR_RTC), 431 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02BA_IO_INR_SCC0), 432 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN02BA_IO_INR_SCC1), 433 [DEC_IRQ_SII] = -1, 434 [DEC_IRQ_TC0] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0), 435 [DEC_IRQ_TC1] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1), 436 [DEC_IRQ_TC2] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2), 437 [DEC_IRQ_TIMER] = -1, 438 [DEC_IRQ_VIDEO] = -1, 439 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), 440 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), 441 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), 442 [DEC_IRQ_FLOPPY_ERR] = -1, 443 [DEC_IRQ_ISDN_ERR] = -1, 444 [DEC_IRQ_ISDN_RXDMA] = -1, 445 [DEC_IRQ_ISDN_TXDMA] = -1, 446 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), 447 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), 448 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), 449 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), 450 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), 451 [DEC_IRQ_AB_RXERR] = -1, 452 [DEC_IRQ_AB_RXDMA] = -1, 453 [DEC_IRQ_AB_TXERR] = -1, 454 [DEC_IRQ_AB_TXDMA] = -1, 455 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR), 456 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA), 457 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR), 458 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA), 459 }; 460 461 static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = { 462 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) }, 463 { .p = kn02xa_io_int } }, 464 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) }, 465 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } }, 466 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) }, 467 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } }, 468 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) }, 469 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } }, 470 { { .i = DEC_CPU_IRQ_ALL }, 471 { .p = cpu_all_int } }, 472 }; 473 474 static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = { 475 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) }, 476 { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } }, 477 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) }, 478 { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } }, 479 { { .i = IO_IRQ_DMA }, 480 { .p = asic_dma_int } }, 481 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) }, 482 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } }, 483 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) }, 484 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } }, 485 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) }, 486 { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } }, 487 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) }, 488 { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } }, 489 { { .i = IO_IRQ_ALL }, 490 { .p = asic_all_int } }, 491 }; 492 493 static void __init dec_init_kn02ba(void) 494 { 495 /* IRQ routing. */ 496 memcpy(&dec_interrupt, &kn02ba_interrupt, 497 sizeof(kn02ba_interrupt)); 498 499 /* CPU IRQ priorities. */ 500 memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl, 501 sizeof(kn02ba_cpu_mask_nr_tbl)); 502 503 /* I/O ASIC IRQ priorities. */ 504 memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl, 505 sizeof(kn02ba_asic_mask_nr_tbl)); 506 507 mips_cpu_irq_init(DEC_CPU_IRQ_BASE); 508 init_ioasic_irqs(IO_IRQ_BASE); 509 510 } /* dec_init_kn02ba */ 511 512 513 /* 514 * Machine-specific initialisation for KN02-CA, aka DS5000/xx, 515 * (xx = 20, 25, 33), aka MAXine. Also applies to KN04(-CA), aka 516 * DS5000/50, aka 4MAXine. 517 */ 518 static int kn02ca_interrupt[DEC_NR_INTS] __initdata = { 519 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE), 520 [DEC_IRQ_AB_RECV] = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV), 521 [DEC_IRQ_AB_XMIT] = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT), 522 [DEC_IRQ_DZ11] = -1, 523 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02CA_IO_INR_ASC), 524 [DEC_IRQ_FLOPPY] = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY), 525 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 526 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT), 527 [DEC_IRQ_ISDN] = IO_IRQ_NR(KN02CA_IO_INR_ISDN), 528 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02CA_IO_INR_LANCE), 529 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS), 530 [DEC_IRQ_PSU] = -1, 531 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC), 532 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02CA_IO_INR_SCC0), 533 [DEC_IRQ_SCC1] = -1, 534 [DEC_IRQ_SII] = -1, 535 [DEC_IRQ_TC0] = IO_IRQ_NR(KN02CA_IO_INR_TC0), 536 [DEC_IRQ_TC1] = IO_IRQ_NR(KN02CA_IO_INR_TC1), 537 [DEC_IRQ_TC2] = -1, 538 [DEC_IRQ_TIMER] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER), 539 [DEC_IRQ_VIDEO] = IO_IRQ_NR(KN02CA_IO_INR_VIDEO), 540 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), 541 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), 542 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), 543 [DEC_IRQ_FLOPPY_ERR] = IO_IRQ_NR(IO_INR_FLOPPY_ERR), 544 [DEC_IRQ_ISDN_ERR] = IO_IRQ_NR(IO_INR_ISDN_ERR), 545 [DEC_IRQ_ISDN_RXDMA] = IO_IRQ_NR(IO_INR_ISDN_RXDMA), 546 [DEC_IRQ_ISDN_TXDMA] = IO_IRQ_NR(IO_INR_ISDN_TXDMA), 547 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), 548 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), 549 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), 550 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), 551 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), 552 [DEC_IRQ_AB_RXERR] = IO_IRQ_NR(IO_INR_AB_RXERR), 553 [DEC_IRQ_AB_RXDMA] = IO_IRQ_NR(IO_INR_AB_RXDMA), 554 [DEC_IRQ_AB_TXERR] = IO_IRQ_NR(IO_INR_AB_TXERR), 555 [DEC_IRQ_AB_TXDMA] = IO_IRQ_NR(IO_INR_AB_TXDMA), 556 [DEC_IRQ_SCC1A_RXERR] = -1, 557 [DEC_IRQ_SCC1A_RXDMA] = -1, 558 [DEC_IRQ_SCC1A_TXERR] = -1, 559 [DEC_IRQ_SCC1A_TXDMA] = -1, 560 }; 561 562 static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = { 563 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) }, 564 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } }, 565 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) }, 566 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } }, 567 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) }, 568 { .p = kn02xa_io_int } }, 569 { { .i = DEC_CPU_IRQ_ALL }, 570 { .p = cpu_all_int } }, 571 }; 572 573 static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = { 574 { { .i = IO_IRQ_DMA }, 575 { .p = asic_dma_int } }, 576 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) }, 577 { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } }, 578 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) }, 579 { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } }, 580 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) }, 581 { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } }, 582 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) }, 583 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } }, 584 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) }, 585 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } }, 586 { { .i = IO_IRQ_ALL }, 587 { .p = asic_all_int } }, 588 }; 589 590 static void __init dec_init_kn02ca(void) 591 { 592 /* IRQ routing. */ 593 memcpy(&dec_interrupt, &kn02ca_interrupt, 594 sizeof(kn02ca_interrupt)); 595 596 /* CPU IRQ priorities. */ 597 memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl, 598 sizeof(kn02ca_cpu_mask_nr_tbl)); 599 600 /* I/O ASIC IRQ priorities. */ 601 memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl, 602 sizeof(kn02ca_asic_mask_nr_tbl)); 603 604 mips_cpu_irq_init(DEC_CPU_IRQ_BASE); 605 init_ioasic_irqs(IO_IRQ_BASE); 606 607 } /* dec_init_kn02ca */ 608 609 610 /* 611 * Machine-specific initialisation for KN03, aka DS5000/240, 612 * aka 3max+ and DS5900, aka BIGmax. Also applies to KN05, aka 613 * DS5000/260, aka 4max+ and DS5900/260. 614 */ 615 static int kn03_interrupt[DEC_NR_INTS] __initdata = { 616 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE), 617 [DEC_IRQ_AB_RECV] = -1, 618 [DEC_IRQ_AB_XMIT] = -1, 619 [DEC_IRQ_DZ11] = -1, 620 [DEC_IRQ_ASC] = IO_IRQ_NR(KN03_IO_INR_ASC), 621 [DEC_IRQ_FLOPPY] = -1, 622 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), 623 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT), 624 [DEC_IRQ_ISDN] = -1, 625 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN03_IO_INR_LANCE), 626 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS), 627 [DEC_IRQ_PSU] = IO_IRQ_NR(KN03_IO_INR_PSU), 628 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC), 629 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN03_IO_INR_SCC0), 630 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN03_IO_INR_SCC1), 631 [DEC_IRQ_SII] = -1, 632 [DEC_IRQ_TC0] = IO_IRQ_NR(KN03_IO_INR_TC0), 633 [DEC_IRQ_TC1] = IO_IRQ_NR(KN03_IO_INR_TC1), 634 [DEC_IRQ_TC2] = IO_IRQ_NR(KN03_IO_INR_TC2), 635 [DEC_IRQ_TIMER] = -1, 636 [DEC_IRQ_VIDEO] = -1, 637 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), 638 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), 639 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), 640 [DEC_IRQ_FLOPPY_ERR] = -1, 641 [DEC_IRQ_ISDN_ERR] = -1, 642 [DEC_IRQ_ISDN_RXDMA] = -1, 643 [DEC_IRQ_ISDN_TXDMA] = -1, 644 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), 645 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), 646 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), 647 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), 648 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), 649 [DEC_IRQ_AB_RXERR] = -1, 650 [DEC_IRQ_AB_RXDMA] = -1, 651 [DEC_IRQ_AB_TXERR] = -1, 652 [DEC_IRQ_AB_TXDMA] = -1, 653 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR), 654 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA), 655 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR), 656 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA), 657 }; 658 659 static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = { 660 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) }, 661 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } }, 662 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) }, 663 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } }, 664 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) }, 665 { .p = kn03_io_int } }, 666 { { .i = DEC_CPU_IRQ_ALL }, 667 { .p = cpu_all_int } }, 668 }; 669 670 static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = { 671 { { .i = IO_IRQ_DMA }, 672 { .p = asic_dma_int } }, 673 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) }, 674 { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } }, 675 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) }, 676 { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } }, 677 { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) }, 678 { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } }, 679 { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) }, 680 { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } }, 681 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) }, 682 { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } }, 683 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) }, 684 { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } }, 685 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) }, 686 { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } }, 687 { { .i = IO_IRQ_ALL }, 688 { .p = asic_all_int } }, 689 }; 690 691 static void __init dec_init_kn03(void) 692 { 693 /* IRQ routing. */ 694 memcpy(&dec_interrupt, &kn03_interrupt, 695 sizeof(kn03_interrupt)); 696 697 /* CPU IRQ priorities. */ 698 memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl, 699 sizeof(kn03_cpu_mask_nr_tbl)); 700 701 /* I/O ASIC IRQ priorities. */ 702 memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl, 703 sizeof(kn03_asic_mask_nr_tbl)); 704 705 mips_cpu_irq_init(DEC_CPU_IRQ_BASE); 706 init_ioasic_irqs(IO_IRQ_BASE); 707 708 } /* dec_init_kn03 */ 709 710 711 void __init arch_init_irq(void) 712 { 713 switch (mips_machtype) { 714 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ 715 dec_init_kn01(); 716 break; 717 case MACH_DS5100: /* DS5100 MIPSmate */ 718 dec_init_kn230(); 719 break; 720 case MACH_DS5000_200: /* DS5000/200 3max */ 721 dec_init_kn02(); 722 break; 723 case MACH_DS5000_1XX: /* DS5000/1xx 3min */ 724 dec_init_kn02ba(); 725 break; 726 case MACH_DS5000_2X0: /* DS5000/240 3max+ */ 727 case MACH_DS5900: /* DS5900 bigmax */ 728 dec_init_kn03(); 729 break; 730 case MACH_DS5000_XX: /* Personal DS5000/xx */ 731 dec_init_kn02ca(); 732 break; 733 case MACH_DS5800: /* DS5800 Isis */ 734 panic("Don't know how to set this up!"); 735 break; 736 case MACH_DS5400: /* DS5400 MIPSfair */ 737 panic("Don't know how to set this up!"); 738 break; 739 case MACH_DS5500: /* DS5500 MIPSfair-2 */ 740 panic("Don't know how to set this up!"); 741 break; 742 } 743 744 /* Free the FPU interrupt if the exception is present. */ 745 if (!cpu_has_nofpuex) { 746 cpu_fpu_mask = 0; 747 dec_interrupt[DEC_IRQ_FPU] = -1; 748 } 749 750 /* Register board interrupts: FPU and cascade. */ 751 if (dec_interrupt[DEC_IRQ_FPU] >= 0) 752 setup_irq(dec_interrupt[DEC_IRQ_FPU], &fpuirq); 753 if (dec_interrupt[DEC_IRQ_CASCADE] >= 0) 754 setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq); 755 756 /* Register the bus error interrupt. */ 757 if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler) 758 setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq); 759 760 /* Register the HALT interrupt. */ 761 if (dec_interrupt[DEC_IRQ_HALT] >= 0) 762 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq); 763 } 764