1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Bus error event handling code for 5000-series systems equipped 4 * with parity error detection logic, i.e. DECstation/DECsystem 5 * 5000/120, /125, /133 (KN02-BA), 5000/150 (KN04-BA) and Personal 6 * DECstation/DECsystem 5000/20, /25, /33 (KN02-CA), 5000/50 7 * (KN04-CA) systems. 8 * 9 * Copyright (c) 2005, 2026 Maciej W. Rozycki 10 */ 11 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/ratelimit.h> 16 #include <linux/types.h> 17 18 #include <asm/addrspace.h> 19 #include <asm/cpu-type.h> 20 #include <asm/irq_regs.h> 21 #include <asm/ptrace.h> 22 #include <asm/traps.h> 23 24 #include <asm/dec/kn02ca.h> 25 #include <asm/dec/kn02xa.h> 26 #include <asm/dec/kn05.h> 27 28 static inline void dec_kn02xa_be_ack(void) 29 { 30 volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER); 31 volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR); 32 33 *mer = KN02CA_MER_INTR; /* Clear errors; keep the ARC IRQ. */ 34 *mem_intr = 0; /* Any write clears the bus IRQ. */ 35 iob(); 36 } 37 38 static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup, 39 int invoker) 40 { 41 volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER); 42 volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR); 43 44 static const char excstr[] = "exception"; 45 static const char intstr[] = "interrupt"; 46 static const char cpustr[] = "CPU"; 47 static const char mreadstr[] = "memory read"; 48 static const char readstr[] = "read"; 49 static const char writestr[] = "write"; 50 static const char timestr[] = "timeout"; 51 static const char paritystr[] = "parity error"; 52 static const char lanestat[][4] = { " OK", "BAD" }; 53 54 static DEFINE_RATELIMIT_STATE(rs, 55 DEFAULT_RATELIMIT_INTERVAL, 56 DEFAULT_RATELIMIT_BURST); 57 58 const char *kind, *agent, *cycle, *event; 59 unsigned long address; 60 61 u32 mer = *kn02xa_mer; 62 u32 ear = *kn02xa_ear; 63 int action = MIPS_BE_FATAL; 64 65 /* Ack ASAP, so that any subsequent errors get caught. */ 66 dec_kn02xa_be_ack(); 67 68 kind = invoker ? intstr : excstr; 69 70 /* No DMA errors? */ 71 agent = cpustr; 72 73 address = ear & KN02XA_EAR_ADDRESS; 74 75 /* Low 256MB is decoded as memory, high -- as TC. */ 76 if (address < 0x10000000) { 77 cycle = mreadstr; 78 event = paritystr; 79 } else { 80 cycle = invoker ? writestr : readstr; 81 event = timestr; 82 } 83 84 if (is_fixup) 85 action = MIPS_BE_FIXUP; 86 87 if (action != MIPS_BE_FIXUP && __ratelimit(&rs)) { 88 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n", 89 kind, agent, cycle, event, address); 90 91 if (address < 0x10000000) 92 printk(KERN_ALERT " Byte lane status %#3x -- " 93 "#3: %s, #2: %s, #1: %s, #0: %s\n", 94 (mer & KN02XA_MER_BYTERR) >> 8, 95 lanestat[(mer & KN02XA_MER_BYTERR_3) != 0], 96 lanestat[(mer & KN02XA_MER_BYTERR_2) != 0], 97 lanestat[(mer & KN02XA_MER_BYTERR_1) != 0], 98 lanestat[(mer & KN02XA_MER_BYTERR_0) != 0]); 99 } 100 101 return action; 102 } 103 104 int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup) 105 { 106 return dec_kn02xa_be_backend(regs, is_fixup, 0); 107 } 108 109 irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id) 110 { 111 struct pt_regs *regs = get_irq_regs(); 112 int action = dec_kn02xa_be_backend(regs, 0, 1); 113 114 if (action == MIPS_BE_DISCARD) 115 return IRQ_HANDLED; 116 117 /* 118 * FIXME: Find the affected processes and kill them, otherwise 119 * we must die. 120 * 121 * The interrupt is asynchronously delivered thus EPC and RA 122 * may be irrelevant, but are printed for a reference. 123 */ 124 printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n", 125 regs->cp0_epc, regs->regs[31]); 126 die("Unrecoverable bus error", regs); 127 } 128 129 130 void __init dec_kn02xa_be_init(void) 131 { 132 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); 133 134 /* For KN04 we need to make sure EE (?) is enabled in the MB. */ 135 if (current_cpu_type() == CPU_R4000SC) 136 *mbcs |= KN4K_MB_CSR_EE; 137 fast_iob(); 138 139 /* Clear any leftover errors from the firmware. */ 140 dec_kn02xa_be_ack(); 141 } 142