1 /* 2 * DECstation 5000/200 (KN02) Control and Status Register 3 * interrupts. 4 * 5 * Copyright (c) 2002, 2003, 2005 Maciej W. Rozycki 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <linux/init.h> 14 #include <linux/irq.h> 15 #include <linux/types.h> 16 17 #include <asm/dec/kn02.h> 18 19 20 /* 21 * Bits 7:0 of the Control Register are write-only -- the 22 * corresponding bits of the Status Register have a different 23 * meaning. Hence we use a cache. It speeds up things a bit 24 * as well. 25 * 26 * There is no default value -- it has to be initialized. 27 */ 28 u32 cached_kn02_csr; 29 30 static int kn02_irq_base; 31 32 static void unmask_kn02_irq(struct irq_data *d) 33 { 34 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + 35 KN02_CSR); 36 37 cached_kn02_csr |= (1 << (d->irq - kn02_irq_base + 16)); 38 *csr = cached_kn02_csr; 39 } 40 41 static void mask_kn02_irq(struct irq_data *d) 42 { 43 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + 44 KN02_CSR); 45 46 cached_kn02_csr &= ~(1 << (d->irq - kn02_irq_base + 16)); 47 *csr = cached_kn02_csr; 48 } 49 50 static void ack_kn02_irq(struct irq_data *d) 51 { 52 mask_kn02_irq(d); 53 iob(); 54 } 55 56 static struct irq_chip kn02_irq_type = { 57 .name = "KN02-CSR", 58 .irq_ack = ack_kn02_irq, 59 .irq_mask = mask_kn02_irq, 60 .irq_mask_ack = ack_kn02_irq, 61 .irq_unmask = unmask_kn02_irq, 62 }; 63 64 void __init init_kn02_irqs(int base) 65 { 66 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + 67 KN02_CSR); 68 int i; 69 70 /* Mask interrupts. */ 71 cached_kn02_csr &= ~KN02_CSR_IOINTEN; 72 *csr = cached_kn02_csr; 73 iob(); 74 75 for (i = base; i < base + KN02_IRQ_LINES; i++) 76 irq_set_chip_and_handler(i, &kn02_irq_type, handle_level_irq); 77 78 kn02_irq_base = base; 79 } 80