1/* 2 * arch/mips/dec/int-handler.S 3 * 4 * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen 5 * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki 6 * 7 * Written by Ralf Baechle and Andreas Busse, modified for DECstation 8 * support by Paul Antoine and Harald Koerfgen. 9 * 10 * completly rewritten: 11 * Copyright (C) 1998 Harald Koerfgen 12 * 13 * Rewritten extensively for controller-driven IRQ support 14 * by Maciej W. Rozycki. 15 */ 16#include <linux/config.h> 17 18#include <asm/addrspace.h> 19#include <asm/asm.h> 20#include <asm/mipsregs.h> 21#include <asm/regdef.h> 22#include <asm/stackframe.h> 23 24#include <asm/dec/interrupts.h> 25#include <asm/dec/ioasic_addrs.h> 26#include <asm/dec/ioasic_ints.h> 27#include <asm/dec/kn01.h> 28#include <asm/dec/kn02.h> 29#include <asm/dec/kn02xa.h> 30#include <asm/dec/kn03.h> 31 32#define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR) 33#define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL) 34#define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL) 35 36 .text 37 .set noreorder 38/* 39 * decstation_handle_int: Interrupt handler for DECstations 40 * 41 * We follow the model in the Indy interrupt code by David Miller, where he 42 * says: a lot of complication here is taken away because: 43 * 44 * 1) We handle one interrupt and return, sitting in a loop 45 * and moving across all the pending IRQ bits in the cause 46 * register is _NOT_ the answer, the common case is one 47 * pending IRQ so optimize in that direction. 48 * 49 * 2) We need not check against bits in the status register 50 * IRQ mask, that would make this routine slow as hell. 51 * 52 * 3) Linux only thinks in terms of all IRQs on or all IRQs 53 * off, nothing in between like BSD spl() brain-damage. 54 * 55 * Furthermore, the IRQs on the DECstations look basically (barring 56 * software IRQs which we don't use at all) like... 57 * 58 * DS2100/3100's, aka kn01, aka Pmax: 59 * 60 * MIPS IRQ Source 61 * -------- ------ 62 * 0 Software (ignored) 63 * 1 Software (ignored) 64 * 2 SCSI 65 * 3 Lance Ethernet 66 * 4 DZ11 serial 67 * 5 RTC 68 * 6 Memory Controller & Video 69 * 7 FPU 70 * 71 * DS5000/200, aka kn02, aka 3max: 72 * 73 * MIPS IRQ Source 74 * -------- ------ 75 * 0 Software (ignored) 76 * 1 Software (ignored) 77 * 2 TurboChannel 78 * 3 RTC 79 * 4 Reserved 80 * 5 Memory Controller 81 * 6 Reserved 82 * 7 FPU 83 * 84 * DS5000/1xx's, aka kn02ba, aka 3min: 85 * 86 * MIPS IRQ Source 87 * -------- ------ 88 * 0 Software (ignored) 89 * 1 Software (ignored) 90 * 2 TurboChannel Slot 0 91 * 3 TurboChannel Slot 1 92 * 4 TurboChannel Slot 2 93 * 5 TurboChannel Slot 3 (ASIC) 94 * 6 Halt button 95 * 7 FPU/R4k timer 96 * 97 * DS5000/2x's, aka kn02ca, aka maxine: 98 * 99 * MIPS IRQ Source 100 * -------- ------ 101 * 0 Software (ignored) 102 * 1 Software (ignored) 103 * 2 Periodic Interrupt (100usec) 104 * 3 RTC 105 * 4 I/O write timeout 106 * 5 TurboChannel (ASIC) 107 * 6 Halt Keycode from Access.Bus keyboard (CTRL-ALT-ENTER) 108 * 7 FPU/R4k timer 109 * 110 * DS5000/2xx's, aka kn03, aka 3maxplus: 111 * 112 * MIPS IRQ Source 113 * -------- ------ 114 * 0 Software (ignored) 115 * 1 Software (ignored) 116 * 2 System Board (ASIC) 117 * 3 RTC 118 * 4 Reserved 119 * 5 Memory 120 * 6 Halt Button 121 * 7 FPU/R4k timer 122 * 123 * We handle the IRQ according to _our_ priority (see setup.c), 124 * then we just return. If multiple IRQs are pending then we will 125 * just take another exception, big deal. 126 */ 127 .align 5 128 NESTED(decstation_handle_int, PT_SIZE, ra) 129 .set noat 130 SAVE_ALL 131 CLI # TEST: interrupts should be off 132 .set at 133 .set noreorder 134 135 /* 136 * Get pending Interrupts 137 */ 138 mfc0 t0,CP0_CAUSE # get pending interrupts 139 mfc0 t1,CP0_STATUS 140#ifdef CONFIG_32BIT 141 lw t2,cpu_fpu_mask 142#endif 143 andi t0,ST0_IM # CAUSE.CE may be non-zero! 144 and t0,t1 # isolate allowed ones 145 146 beqz t0,spurious 147 148#ifdef CONFIG_32BIT 149 and t2,t0 150 bnez t2,fpu # handle FPU immediately 151#endif 152 153 /* 154 * Find irq with highest priority 155 */ 156 PTR_LA t1,cpu_mask_nr_tbl 1571: lw t2,(t1) 158 nop 159 and t2,t0 160 beqz t2,1b 161 addu t1,2*PTRSIZE # delay slot 162 163 /* 164 * Do the low-level stuff 165 */ 166 lw a0,(-PTRSIZE)(t1) 167 nop 168 bgez a0,handle_it # irq_nr >= 0? 169 # irq_nr < 0: it is an address 170 nop 171 jr a0 172 # a trick to save a branch: 173 lui t2,(KN03_IOASIC_BASE>>16)&0xffff 174 # upper part of IOASIC Address 175 176/* 177 * Handle "IRQ Controller" Interrupts 178 * Masked Interrupts are still visible and have to be masked "by hand". 179 */ 180 FEXPORT(kn02_io_int) # 3max 181 lui t0,(KN02_CSR_BASE>>16)&0xffff 182 # get interrupt status and mask 183 lw t0,(t0) 184 nop 185 andi t1,t0,KN02_IRQ_ALL 186 b 1f 187 srl t0,16 # shift interrupt mask 188 189 FEXPORT(kn02xa_io_int) # 3min/maxine 190 lui t2,(KN02XA_IOASIC_BASE>>16)&0xffff 191 # upper part of IOASIC Address 192 193 FEXPORT(kn03_io_int) # 3max+ (t2 loaded earlier) 194 lw t0,IO_REG_SIR(t2) # get status: IOASIC sir 195 lw t1,IO_REG_SIMR(t2) # get mask: IOASIC simr 196 nop 197 1981: and t0,t1 # mask out allowed ones 199 200 beqz t0,spurious 201 202 /* 203 * Find irq with highest priority 204 */ 205 PTR_LA t1,asic_mask_nr_tbl 2062: lw t2,(t1) 207 nop 208 and t2,t0 209 beq zero,t2,2b 210 addu t1,2*PTRSIZE # delay slot 211 212 /* 213 * Do the low-level stuff 214 */ 215 lw a0,%lo(-PTRSIZE)(t1) 216 nop 217 bgez a0,handle_it # irq_nr >= 0? 218 # irq_nr < 0: it is an address 219 nop 220 jr a0 221 nop # delay slot 222 223/* 224 * Dispatch low-priority interrupts. We reconsider all status 225 * bits again, which looks like a lose, but it makes the code 226 * simple and O(log n), so it gets compensated. 227 */ 228 FEXPORT(cpu_all_int) # HALT, timers, software junk 229 li a0,DEC_CPU_IRQ_BASE 230 srl t0,CAUSEB_IP 231 li t1,CAUSEF_IP>>CAUSEB_IP # mask 232 b 1f 233 li t2,4 # nr of bits / 2 234 235 FEXPORT(kn02_all_int) # impossible ? 236 li a0,KN02_IRQ_BASE 237 li t1,KN02_IRQ_ALL # mask 238 b 1f 239 li t2,4 # nr of bits / 2 240 241 FEXPORT(asic_all_int) # various I/O ASIC junk 242 li a0,IO_IRQ_BASE 243 li t1,IO_IRQ_ALL # mask 244 b 1f 245 li t2,8 # nr of bits / 2 246 247/* 248 * Dispatch DMA interrupts -- O(log n). 249 */ 250 FEXPORT(asic_dma_int) # I/O ASIC DMA events 251 li a0,IO_IRQ_BASE+IO_INR_DMA 252 srl t0,IO_INR_DMA 253 li t1,IO_IRQ_DMA>>IO_INR_DMA # mask 254 li t2,8 # nr of bits / 2 255 256 /* 257 * Find irq with highest priority. 258 * Highest irq number takes precedence. 259 */ 2601: srlv t3,t1,t2 2612: xor t1,t3 262 and t3,t0,t1 263 beqz t3,3f 264 nop 265 move t0,t3 266 addu a0,t2 2673: srl t2,1 268 bnez t2,2b 269 srlv t3,t1,t2 270 271handle_it: 272 jal do_IRQ 273 move a1,sp 274 275 j ret_from_irq 276 nop 277 278#ifdef CONFIG_32BIT 279fpu: 280 j handle_fpe_int 281 nop 282#endif 283 284spurious: 285 j spurious_interrupt 286 nop 287 END(decstation_handle_int) 288 289/* 290 * Generic unimplemented interrupt routines -- cpu_mask_nr_tbl 291 * and asic_mask_nr_tbl are initialized to point all interrupts here. 292 * The tables are then filled in by machine-specific initialisation 293 * in dec_setup(). 294 */ 295 FEXPORT(dec_intr_unimplemented) 296 move a1,t0 # cheats way of printing an arg! 297 PANIC("Unimplemented cpu interrupt! CP0_CAUSE: 0x%08x"); 298 299 FEXPORT(asic_intr_unimplemented) 300 move a1,t0 # cheats way of printing an arg! 301 PANIC("Unimplemented asic interrupt! ASIC ISR: 0x%08x"); 302