xref: /linux/arch/mips/cobalt/setup.c (revision d8327c784b51b57dac2c26cfad87dce0d68dfd98)
1 /*
2  * Setup pointers to hardware dependent routines.
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org)
9  * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
10  *
11  */
12 #include <linux/config.h>
13 #include <linux/interrupt.h>
14 #include <linux/pci.h>
15 #include <linux/init.h>
16 #include <linux/pm.h>
17 #include <linux/serial.h>
18 #include <linux/serial_core.h>
19 
20 #include <asm/bootinfo.h>
21 #include <asm/time.h>
22 #include <asm/io.h>
23 #include <asm/irq.h>
24 #include <asm/processor.h>
25 #include <asm/reboot.h>
26 #include <asm/gt64120.h>
27 #include <asm/serial.h>
28 
29 #include <asm/mach-cobalt/cobalt.h>
30 
31 extern void cobalt_machine_restart(char *command);
32 extern void cobalt_machine_halt(void);
33 extern void cobalt_machine_power_off(void);
34 
35 int cobalt_board_id;
36 
37 const char *get_system_type(void)
38 {
39 	switch (cobalt_board_id) {
40 		case COBALT_BRD_ID_QUBE1:
41 			return "Cobalt Qube";
42 		case COBALT_BRD_ID_RAQ1:
43 			return "Cobalt RaQ";
44 		case COBALT_BRD_ID_QUBE2:
45 			return "Cobalt Qube2";
46 		case COBALT_BRD_ID_RAQ2:
47 			return "Cobalt RaQ2";
48 	}
49 	return "MIPS Cobalt";
50 }
51 
52 static void __init cobalt_timer_setup(struct irqaction *irq)
53 {
54 	/* Load timer value for 1KHz (TCLK is 50MHz) */
55 	GALILEO_OUTL(50*1000*1000 / 1000, GT_TC0_OFS);
56 
57 	/* Enable timer */
58 	GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS);
59 
60 	/* Register interrupt */
61 	setup_irq(COBALT_GALILEO_IRQ, irq);
62 
63 	/* Enable interrupt */
64 	GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
65 }
66 
67 extern struct pci_ops gt64111_pci_ops;
68 
69 static struct resource cobalt_mem_resource = {
70 	"PCI memory", GT64111_MEM_BASE, GT64111_MEM_END, IORESOURCE_MEM
71 };
72 
73 static struct resource cobalt_io_resource = {
74 	"PCI I/O", 0x1000, 0xffff, IORESOURCE_IO
75 };
76 
77 static struct resource cobalt_io_resources[] = {
78 	{ "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
79 	{ "timer", 0x40, 0x5f, IORESOURCE_BUSY },
80 	{ "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
81 	{ "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
82 	{ "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
83 };
84 
85 #define COBALT_IO_RESOURCES (sizeof(cobalt_io_resources)/sizeof(struct resource))
86 
87 static struct pci_controller cobalt_pci_controller = {
88 	.pci_ops	= &gt64111_pci_ops,
89 	.mem_resource	= &cobalt_mem_resource,
90 	.mem_offset	= 0,
91 	.io_resource	= &cobalt_io_resource,
92 	.io_offset	= 0 - GT64111_IO_BASE
93 };
94 
95 void __init plat_setup(void)
96 {
97 	static struct uart_port uart;
98 	unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
99 	int i;
100 
101 	_machine_restart = cobalt_machine_restart;
102 	_machine_halt = cobalt_machine_halt;
103 	pm_power_off = cobalt_machine_power_off;
104 
105 	board_timer_setup = cobalt_timer_setup;
106 
107         set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE));
108 
109 	/* I/O port resource must include UART and LCD/buttons */
110 	ioport_resource.end = 0x0fffffff;
111 
112 	/*
113 	 * This is a prom style console. We just poke at the
114 	 *  UART to make it talk.
115 	 * Only use this console if you really screw up and can't
116 	 *  get to the stage of setting up a real serial console.
117 	 */
118 	/*ns16550_setup_console();*/
119 
120 	/* request I/O space for devices used on all i[345]86 PCs */
121 	for (i = 0; i < COBALT_IO_RESOURCES; i++)
122 		request_resource(&ioport_resource, cobalt_io_resources + i);
123 
124         /* Read the cobalt id register out of the PCI config space */
125         PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
126         cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS);
127         cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
128         cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
129 
130 	printk("Cobalt board ID: %d\n", cobalt_board_id);
131 
132 #ifdef CONFIG_PCI
133 	register_pci_controller(&cobalt_pci_controller);
134 #endif
135 
136 #ifdef CONFIG_SERIAL_8250
137 	if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
138 
139 		uart.line	= 0;
140 		uart.type	= PORT_UNKNOWN;
141 		uart.uartclk	= 18432000;
142 		uart.irq	= COBALT_SERIAL_IRQ;
143 		uart.flags	= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
144 		uart.iobase	= 0xc800000;
145 		uart.iotype	= UPIO_PORT;
146 
147 		early_serial_setup(&uart);
148 	}
149 #endif
150 }
151 
152 /*
153  * Prom init. We read our one and only communication with the firmware.
154  * Grab the amount of installed memory.
155  * Better boot loaders (CoLo) pass a command line too :-)
156  */
157 
158 void __init prom_init(void)
159 {
160 	int narg, indx, posn, nchr;
161 	unsigned long memsz;
162 	char **argv;
163 
164 	mips_machgroup = MACH_GROUP_COBALT;
165 
166 	memsz = fw_arg0 & 0x7fff0000;
167 	narg = fw_arg0 & 0x0000ffff;
168 
169 	if (narg) {
170 		arcs_cmdline[0] = '\0';
171 		argv = (char **) fw_arg1;
172 		posn = 0;
173 		for (indx = 1; indx < narg; ++indx) {
174 			nchr = strlen(argv[indx]);
175 			if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline))
176 				break;
177 			if (posn)
178 				arcs_cmdline[posn++] = ' ';
179 			strcpy(arcs_cmdline + posn, argv[indx]);
180 			posn += nchr;
181 		}
182 	}
183 
184 	add_memory_region(0x0, memsz, BOOT_MEM_RAM);
185 }
186 
187 unsigned long __init prom_free_prom_memory(void)
188 {
189 	/* Nothing to do! */
190 	return 0;
191 }
192