1 /* 2 * Setup pointers to hardware dependent routines. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org) 9 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) 10 * 11 */ 12 #include <linux/interrupt.h> 13 #include <linux/pci.h> 14 #include <linux/init.h> 15 #include <linux/pm.h> 16 #include <linux/serial.h> 17 #include <linux/serial_core.h> 18 19 #include <asm/bootinfo.h> 20 #include <asm/time.h> 21 #include <asm/io.h> 22 #include <asm/irq.h> 23 #include <asm/processor.h> 24 #include <asm/reboot.h> 25 #include <asm/gt64120.h> 26 27 #include <asm/mach-cobalt/cobalt.h> 28 29 extern void cobalt_machine_restart(char *command); 30 extern void cobalt_machine_halt(void); 31 extern void cobalt_machine_power_off(void); 32 extern void cobalt_early_console(void); 33 34 int cobalt_board_id; 35 36 const char *get_system_type(void) 37 { 38 switch (cobalt_board_id) { 39 case COBALT_BRD_ID_QUBE1: 40 return "Cobalt Qube"; 41 case COBALT_BRD_ID_RAQ1: 42 return "Cobalt RaQ"; 43 case COBALT_BRD_ID_QUBE2: 44 return "Cobalt Qube2"; 45 case COBALT_BRD_ID_RAQ2: 46 return "Cobalt RaQ2"; 47 } 48 return "MIPS Cobalt"; 49 } 50 51 void __init plat_timer_setup(struct irqaction *irq) 52 { 53 /* Load timer value for HZ (TCLK is 50MHz) */ 54 GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ); 55 56 /* Enable timer */ 57 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); 58 59 /* Register interrupt */ 60 setup_irq(COBALT_GALILEO_IRQ, irq); 61 62 /* Enable interrupt */ 63 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS)); 64 } 65 66 extern struct pci_ops gt64111_pci_ops; 67 68 static struct resource cobalt_mem_resource = { 69 .start = GT_DEF_PCI0_MEM0_BASE, 70 .end = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1, 71 .name = "PCI memory", 72 .flags = IORESOURCE_MEM 73 }; 74 75 static struct resource cobalt_io_resource = { 76 .start = 0x1000, 77 .end = 0xffff, 78 .name = "PCI I/O", 79 .flags = IORESOURCE_IO 80 }; 81 82 /* 83 * Cobalt doesn't have PS/2 keyboard/mouse interfaces, 84 * keyboard conntroller is never used. 85 * Also PCI-ISA bridge DMA contoroller is never used. 86 */ 87 static struct resource cobalt_reserved_resources[] = { 88 { /* dma1 */ 89 .start = 0x00, 90 .end = 0x1f, 91 .name = "reserved", 92 .flags = IORESOURCE_BUSY | IORESOURCE_IO, 93 }, 94 { /* keyboard */ 95 .start = 0x60, 96 .end = 0x6f, 97 .name = "reserved", 98 .flags = IORESOURCE_BUSY | IORESOURCE_IO, 99 }, 100 { /* dma page reg */ 101 .start = 0x80, 102 .end = 0x8f, 103 .name = "reserved", 104 .flags = IORESOURCE_BUSY | IORESOURCE_IO, 105 }, 106 { /* dma2 */ 107 .start = 0xc0, 108 .end = 0xdf, 109 .name = "reserved", 110 .flags = IORESOURCE_BUSY | IORESOURCE_IO, 111 }, 112 }; 113 114 static struct pci_controller cobalt_pci_controller = { 115 .pci_ops = >64111_pci_ops, 116 .mem_resource = &cobalt_mem_resource, 117 .mem_offset = 0, 118 .io_resource = &cobalt_io_resource, 119 .io_offset = 0 - GT_DEF_PCI0_IO_BASE, 120 }; 121 122 void __init plat_mem_setup(void) 123 { 124 static struct uart_port uart; 125 unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0); 126 int i; 127 128 _machine_restart = cobalt_machine_restart; 129 _machine_halt = cobalt_machine_halt; 130 pm_power_off = cobalt_machine_power_off; 131 132 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); 133 134 /* I/O port resource must include LCD/buttons */ 135 ioport_resource.end = 0x0fffffff; 136 137 /* These resources have been reserved by VIA SuperI/O chip. */ 138 for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++) 139 request_resource(&ioport_resource, cobalt_reserved_resources + i); 140 141 /* Read the cobalt id register out of the PCI config space */ 142 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3)); 143 cobalt_board_id = GT_READ(GT_PCI0_CFGDATA_OFS); 144 cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8); 145 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id); 146 147 printk("Cobalt board ID: %d\n", cobalt_board_id); 148 149 #ifdef CONFIG_PCI 150 register_pci_controller(&cobalt_pci_controller); 151 #endif 152 153 if (cobalt_board_id > COBALT_BRD_ID_RAQ1) { 154 #ifdef CONFIG_SERIAL_8250 155 uart.line = 0; 156 uart.type = PORT_UNKNOWN; 157 uart.uartclk = 18432000; 158 uart.irq = COBALT_SERIAL_IRQ; 159 uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | 160 UPF_SKIP_TEST; 161 uart.iotype = UPIO_MEM; 162 uart.mapbase = 0x1c800000; 163 164 early_serial_setup(&uart); 165 #endif 166 } 167 } 168 169 /* 170 * Prom init. We read our one and only communication with the firmware. 171 * Grab the amount of installed memory. 172 * Better boot loaders (CoLo) pass a command line too :-) 173 */ 174 175 void __init prom_init(void) 176 { 177 int narg, indx, posn, nchr; 178 unsigned long memsz; 179 char **argv; 180 181 mips_machgroup = MACH_GROUP_COBALT; 182 183 memsz = fw_arg0 & 0x7fff0000; 184 narg = fw_arg0 & 0x0000ffff; 185 186 if (narg) { 187 arcs_cmdline[0] = '\0'; 188 argv = (char **) fw_arg1; 189 posn = 0; 190 for (indx = 1; indx < narg; ++indx) { 191 nchr = strlen(argv[indx]); 192 if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline)) 193 break; 194 if (posn) 195 arcs_cmdline[posn++] = ' '; 196 strcpy(arcs_cmdline + posn, argv[indx]); 197 posn += nchr; 198 } 199 } 200 201 add_memory_region(0x0, memsz, BOOT_MEM_RAM); 202 } 203 204 void __init prom_free_prom_memory(void) 205 { 206 /* Nothing to do! */ 207 } 208