1 /* 2 * Setup pointers to hardware dependent routines. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org) 9 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) 10 * 11 */ 12 #include <linux/interrupt.h> 13 #include <linux/pci.h> 14 #include <linux/init.h> 15 #include <linux/pm.h> 16 #include <linux/serial.h> 17 #include <linux/serial_core.h> 18 19 #include <asm/bootinfo.h> 20 #include <asm/time.h> 21 #include <asm/io.h> 22 #include <asm/irq.h> 23 #include <asm/processor.h> 24 #include <asm/reboot.h> 25 #include <asm/gt64120.h> 26 27 #include <asm/mach-cobalt/cobalt.h> 28 29 extern void cobalt_machine_restart(char *command); 30 extern void cobalt_machine_halt(void); 31 extern void cobalt_machine_power_off(void); 32 extern void cobalt_early_console(void); 33 34 int cobalt_board_id; 35 36 const char *get_system_type(void) 37 { 38 switch (cobalt_board_id) { 39 case COBALT_BRD_ID_QUBE1: 40 return "Cobalt Qube"; 41 case COBALT_BRD_ID_RAQ1: 42 return "Cobalt RaQ"; 43 case COBALT_BRD_ID_QUBE2: 44 return "Cobalt Qube2"; 45 case COBALT_BRD_ID_RAQ2: 46 return "Cobalt RaQ2"; 47 } 48 return "MIPS Cobalt"; 49 } 50 51 void __init plat_timer_setup(struct irqaction *irq) 52 { 53 /* Load timer value for HZ (TCLK is 50MHz) */ 54 GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ); 55 56 /* Enable timer */ 57 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); 58 59 /* Register interrupt */ 60 setup_irq(COBALT_GALILEO_IRQ, irq); 61 62 /* Enable interrupt */ 63 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS)); 64 } 65 66 extern struct pci_ops gt64111_pci_ops; 67 68 static struct resource cobalt_mem_resource = { 69 .start = GT_DEF_PCI0_MEM0_BASE, 70 .end = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1, 71 .name = "PCI memory", 72 .flags = IORESOURCE_MEM 73 }; 74 75 static struct resource cobalt_io_resource = { 76 .start = 0x1000, 77 .end = 0xffff, 78 .name = "PCI I/O", 79 .flags = IORESOURCE_IO 80 }; 81 82 static struct resource cobalt_io_resources[] = { 83 { 84 .start = 0x00, 85 .end = 0x1f, 86 .name = "dma1", 87 .flags = IORESOURCE_BUSY 88 }, { 89 .start = 0x40, 90 .end = 0x5f, 91 .name = "timer", 92 .flags = IORESOURCE_BUSY 93 }, { 94 .start = 0x60, 95 .end = 0x6f, 96 .name = "keyboard", 97 .flags = IORESOURCE_BUSY 98 }, { 99 .start = 0x80, 100 .end = 0x8f, 101 .name = "dma page reg", 102 .flags = IORESOURCE_BUSY 103 }, { 104 .start = 0xc0, 105 .end = 0xdf, 106 .name = "dma2", 107 .flags = IORESOURCE_BUSY 108 }, 109 }; 110 111 #define COBALT_IO_RESOURCES (sizeof(cobalt_io_resources)/sizeof(struct resource)) 112 113 static struct pci_controller cobalt_pci_controller = { 114 .pci_ops = >64111_pci_ops, 115 .mem_resource = &cobalt_mem_resource, 116 .mem_offset = 0, 117 .io_resource = &cobalt_io_resource, 118 .io_offset = 0 - GT_DEF_PCI0_IO_BASE, 119 }; 120 121 void __init plat_mem_setup(void) 122 { 123 static struct uart_port uart; 124 unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0); 125 int i; 126 127 _machine_restart = cobalt_machine_restart; 128 _machine_halt = cobalt_machine_halt; 129 pm_power_off = cobalt_machine_power_off; 130 131 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); 132 133 /* I/O port resource must include UART and LCD/buttons */ 134 ioport_resource.end = 0x0fffffff; 135 136 /* request I/O space for devices used on all i[345]86 PCs */ 137 for (i = 0; i < COBALT_IO_RESOURCES; i++) 138 request_resource(&ioport_resource, cobalt_io_resources + i); 139 140 /* Read the cobalt id register out of the PCI config space */ 141 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3)); 142 cobalt_board_id = GT_READ(GT_PCI0_CFGDATA_OFS); 143 cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8); 144 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id); 145 146 printk("Cobalt board ID: %d\n", cobalt_board_id); 147 148 #ifdef CONFIG_PCI 149 register_pci_controller(&cobalt_pci_controller); 150 #endif 151 152 #ifdef CONFIG_SERIAL_8250 153 if (cobalt_board_id > COBALT_BRD_ID_RAQ1) { 154 155 #ifdef CONFIG_EARLY_PRINTK 156 cobalt_early_console(); 157 #endif 158 159 uart.line = 0; 160 uart.type = PORT_UNKNOWN; 161 uart.uartclk = 18432000; 162 uart.irq = COBALT_SERIAL_IRQ; 163 uart.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; 164 uart.iobase = 0xc800000; 165 uart.iotype = UPIO_PORT; 166 167 early_serial_setup(&uart); 168 } 169 #endif 170 } 171 172 /* 173 * Prom init. We read our one and only communication with the firmware. 174 * Grab the amount of installed memory. 175 * Better boot loaders (CoLo) pass a command line too :-) 176 */ 177 178 void __init prom_init(void) 179 { 180 int narg, indx, posn, nchr; 181 unsigned long memsz; 182 char **argv; 183 184 mips_machgroup = MACH_GROUP_COBALT; 185 186 memsz = fw_arg0 & 0x7fff0000; 187 narg = fw_arg0 & 0x0000ffff; 188 189 if (narg) { 190 arcs_cmdline[0] = '\0'; 191 argv = (char **) fw_arg1; 192 posn = 0; 193 for (indx = 1; indx < narg; ++indx) { 194 nchr = strlen(argv[indx]); 195 if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline)) 196 break; 197 if (posn) 198 arcs_cmdline[posn++] = ' '; 199 strcpy(arcs_cmdline + posn, argv[indx]); 200 posn += nchr; 201 } 202 } 203 204 add_memory_region(0x0, memsz, BOOT_MEM_RAM); 205 } 206 207 void __init prom_free_prom_memory(void) 208 { 209 /* Nothing to do! */ 210 } 211