1 /* 2 * Setup pointers to hardware dependent routines. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org) 9 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) 10 * 11 */ 12 #include <linux/interrupt.h> 13 #include <linux/pci.h> 14 #include <linux/init.h> 15 #include <linux/pm.h> 16 #include <linux/serial.h> 17 #include <linux/serial_core.h> 18 19 #include <asm/bootinfo.h> 20 #include <asm/time.h> 21 #include <asm/io.h> 22 #include <asm/irq.h> 23 #include <asm/processor.h> 24 #include <asm/reboot.h> 25 #include <asm/gt64120.h> 26 #include <asm/serial.h> 27 28 #include <asm/mach-cobalt/cobalt.h> 29 30 extern void cobalt_machine_restart(char *command); 31 extern void cobalt_machine_halt(void); 32 extern void cobalt_machine_power_off(void); 33 extern void cobalt_early_console(void); 34 35 int cobalt_board_id; 36 37 const char *get_system_type(void) 38 { 39 switch (cobalt_board_id) { 40 case COBALT_BRD_ID_QUBE1: 41 return "Cobalt Qube"; 42 case COBALT_BRD_ID_RAQ1: 43 return "Cobalt RaQ"; 44 case COBALT_BRD_ID_QUBE2: 45 return "Cobalt Qube2"; 46 case COBALT_BRD_ID_RAQ2: 47 return "Cobalt RaQ2"; 48 } 49 return "MIPS Cobalt"; 50 } 51 52 static void __init cobalt_timer_setup(struct irqaction *irq) 53 { 54 /* Load timer value for 1KHz (TCLK is 50MHz) */ 55 GALILEO_OUTL(50*1000*1000 / 1000, GT_TC0_OFS); 56 57 /* Enable timer */ 58 GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS); 59 60 /* Register interrupt */ 61 setup_irq(COBALT_GALILEO_IRQ, irq); 62 63 /* Enable interrupt */ 64 GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS); 65 } 66 67 extern struct pci_ops gt64111_pci_ops; 68 69 static struct resource cobalt_mem_resource = { 70 .start = GT64111_MEM_BASE, 71 .end = GT64111_MEM_END, 72 .name = "PCI memory", 73 .flags = IORESOURCE_MEM 74 }; 75 76 static struct resource cobalt_io_resource = { 77 .start = 0x1000, 78 .end = 0xffff, 79 .name = "PCI I/O", 80 .flags = IORESOURCE_IO 81 }; 82 83 static struct resource cobalt_io_resources[] = { 84 { 85 .start = 0x00, 86 .end = 0x1f, 87 .name = "dma1", 88 .flags = IORESOURCE_BUSY 89 }, { 90 .start = 0x40, 91 .end = 0x5f, 92 .name = "timer", 93 .flags = IORESOURCE_BUSY 94 }, { 95 .start = 0x60, 96 .end = 0x6f, 97 .name = "keyboard", 98 .flags = IORESOURCE_BUSY 99 }, { 100 .start = 0x80, 101 .end = 0x8f, 102 .name = "dma page reg", 103 .flags = IORESOURCE_BUSY 104 }, { 105 .start = 0xc0, 106 .end = 0xdf, 107 .name = "dma2", 108 .flags = IORESOURCE_BUSY 109 }, 110 }; 111 112 #define COBALT_IO_RESOURCES (sizeof(cobalt_io_resources)/sizeof(struct resource)) 113 114 static struct pci_controller cobalt_pci_controller = { 115 .pci_ops = >64111_pci_ops, 116 .mem_resource = &cobalt_mem_resource, 117 .mem_offset = 0, 118 .io_resource = &cobalt_io_resource, 119 .io_offset = 0 - GT64111_IO_BASE 120 }; 121 122 void __init plat_mem_setup(void) 123 { 124 static struct uart_port uart; 125 unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0); 126 int i; 127 128 _machine_restart = cobalt_machine_restart; 129 _machine_halt = cobalt_machine_halt; 130 pm_power_off = cobalt_machine_power_off; 131 132 board_timer_setup = cobalt_timer_setup; 133 134 set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE)); 135 136 /* I/O port resource must include UART and LCD/buttons */ 137 ioport_resource.end = 0x0fffffff; 138 139 /* request I/O space for devices used on all i[345]86 PCs */ 140 for (i = 0; i < COBALT_IO_RESOURCES; i++) 141 request_resource(&ioport_resource, cobalt_io_resources + i); 142 143 /* Read the cobalt id register out of the PCI config space */ 144 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3)); 145 cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS); 146 cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8); 147 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id); 148 149 printk("Cobalt board ID: %d\n", cobalt_board_id); 150 151 #ifdef CONFIG_PCI 152 register_pci_controller(&cobalt_pci_controller); 153 #endif 154 155 #ifdef CONFIG_SERIAL_8250 156 if (cobalt_board_id > COBALT_BRD_ID_RAQ1) { 157 158 #ifdef CONFIG_EARLY_PRINTK 159 cobalt_early_console(); 160 #endif 161 162 uart.line = 0; 163 uart.type = PORT_UNKNOWN; 164 uart.uartclk = 18432000; 165 uart.irq = COBALT_SERIAL_IRQ; 166 uart.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; 167 uart.iobase = 0xc800000; 168 uart.iotype = UPIO_PORT; 169 170 early_serial_setup(&uart); 171 } 172 #endif 173 } 174 175 /* 176 * Prom init. We read our one and only communication with the firmware. 177 * Grab the amount of installed memory. 178 * Better boot loaders (CoLo) pass a command line too :-) 179 */ 180 181 void __init prom_init(void) 182 { 183 int narg, indx, posn, nchr; 184 unsigned long memsz; 185 char **argv; 186 187 mips_machgroup = MACH_GROUP_COBALT; 188 189 memsz = fw_arg0 & 0x7fff0000; 190 narg = fw_arg0 & 0x0000ffff; 191 192 if (narg) { 193 arcs_cmdline[0] = '\0'; 194 argv = (char **) fw_arg1; 195 posn = 0; 196 for (indx = 1; indx < narg; ++indx) { 197 nchr = strlen(argv[indx]); 198 if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline)) 199 break; 200 if (posn) 201 arcs_cmdline[posn++] = ' '; 202 strcpy(arcs_cmdline + posn, argv[indx]); 203 posn += nchr; 204 } 205 } 206 207 add_memory_region(0x0, memsz, BOOT_MEM_RAM); 208 } 209 210 unsigned long __init prom_free_prom_memory(void) 211 { 212 /* Nothing to do! */ 213 return 0; 214 } 215