1 /* 2 * IRQ vector handles 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle 9 */ 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/irq.h> 13 #include <linux/interrupt.h> 14 #include <linux/pci.h> 15 16 #include <asm/i8259.h> 17 #include <asm/irq_cpu.h> 18 #include <asm/gt64120.h> 19 20 #include <asm/mach-cobalt/cobalt.h> 21 22 /* 23 * We have two types of interrupts that we handle, ones that come in through 24 * the CPU interrupt lines, and ones that come in on the via chip. The CPU 25 * mappings are: 26 * 27 * 16 - Software interrupt 0 (unused) IE_SW0 28 * 17 - Software interrupt 1 (unused) IE_SW1 29 * 18 - Galileo chip (timer) IE_IRQ0 30 * 19 - Tulip 0 + NCR SCSI IE_IRQ1 31 * 20 - Tulip 1 IE_IRQ2 32 * 21 - 16550 UART IE_IRQ3 33 * 22 - VIA southbridge PIC IE_IRQ4 34 * 23 - unused IE_IRQ5 35 * 36 * The VIA chip is a master/slave 8259 setup and has the following interrupts: 37 * 38 * 8 - RTC 39 * 9 - PCI 40 * 14 - IDE0 41 * 15 - IDE1 42 */ 43 44 static inline void galileo_irq(void) 45 { 46 unsigned int mask, pending, devfn; 47 48 mask = GT_READ(GT_INTRMASK_OFS); 49 pending = GT_READ(GT_INTRCAUSE_OFS) & mask; 50 51 if (pending & GT_INTR_T0EXP_MSK) { 52 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK); 53 do_IRQ(COBALT_GALILEO_IRQ); 54 } else if (pending & GT_INTR_RETRYCTR0_MSK) { 55 devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8; 56 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK); 57 printk(KERN_WARNING 58 "Galileo: PCI retry count exceeded (%02x.%u)\n", 59 PCI_SLOT(devfn), PCI_FUNC(devfn)); 60 } else { 61 GT_WRITE(GT_INTRMASK_OFS, mask & ~pending); 62 printk(KERN_WARNING 63 "Galileo: masking unexpected interrupt %08x\n", pending); 64 } 65 } 66 67 static inline void via_pic_irq(void) 68 { 69 int irq; 70 71 irq = i8259_irq(); 72 if (irq >= 0) 73 do_IRQ(irq); 74 } 75 76 asmlinkage void plat_irq_dispatch(void) 77 { 78 unsigned pending = read_c0_status() & read_c0_cause(); 79 80 if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */ 81 galileo_irq(); 82 else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */ 83 via_pic_irq(); 84 else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */ 85 do_IRQ(COBALT_CPU_IRQ + 3); 86 else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */ 87 do_IRQ(COBALT_CPU_IRQ + 4); 88 else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */ 89 do_IRQ(COBALT_CPU_IRQ + 5); 90 else if (pending & CAUSEF_IP7) /* IRQ 23 */ 91 do_IRQ(COBALT_CPU_IRQ + 7); 92 } 93 94 static struct irqaction irq_via = { 95 no_action, 0, { { 0, } }, "cascade", NULL, NULL 96 }; 97 98 void __init arch_init_irq(void) 99 { 100 /* 101 * Mask all Galileo interrupts. The Galileo 102 * handler is set in cobalt_timer_setup() 103 */ 104 GT_WRITE(GT_INTRMASK_OFS, 0); 105 106 init_i8259_irqs(); /* 0 ... 15 */ 107 mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */ 108 109 /* 110 * Mask all cpu interrupts 111 * (except IE4, we already masked those at VIA level) 112 */ 113 change_c0_status(ST0_IM, IE_IRQ4); 114 115 setup_irq(COBALT_VIA_IRQ, &irq_via); 116 } 117