1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks 7 */ 8 #include <linux/cpu.h> 9 #include <linux/delay.h> 10 #include <linux/smp.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/sched.h> 14 #include <linux/module.h> 15 16 #include <asm/mmu_context.h> 17 #include <asm/time.h> 18 #include <asm/setup.h> 19 20 #include <asm/octeon/octeon.h> 21 22 #include "octeon_boot.h" 23 24 volatile unsigned long octeon_processor_boot = 0xff; 25 volatile unsigned long octeon_processor_sp; 26 volatile unsigned long octeon_processor_gp; 27 28 #ifdef CONFIG_HOTPLUG_CPU 29 uint64_t octeon_bootloader_entry_addr; 30 EXPORT_SYMBOL(octeon_bootloader_entry_addr); 31 #endif 32 33 static void octeon_icache_flush(void) 34 { 35 asm volatile ("synci 0($0)\n"); 36 } 37 38 static void (*octeon_message_functions[8])(void) = { 39 scheduler_ipi, 40 generic_smp_call_function_interrupt, 41 octeon_icache_flush, 42 }; 43 44 static irqreturn_t mailbox_interrupt(int irq, void *dev_id) 45 { 46 u64 mbox_clrx = CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()); 47 u64 action; 48 int i; 49 50 /* 51 * Make sure the function array initialization remains 52 * correct. 53 */ 54 BUILD_BUG_ON(SMP_RESCHEDULE_YOURSELF != (1 << 0)); 55 BUILD_BUG_ON(SMP_CALL_FUNCTION != (1 << 1)); 56 BUILD_BUG_ON(SMP_ICACHE_FLUSH != (1 << 2)); 57 58 /* 59 * Load the mailbox register to figure out what we're supposed 60 * to do. 61 */ 62 action = cvmx_read_csr(mbox_clrx); 63 64 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 65 action &= 0xff; 66 else 67 action &= 0xffff; 68 69 /* Clear the mailbox to clear the interrupt */ 70 cvmx_write_csr(mbox_clrx, action); 71 72 for (i = 0; i < ARRAY_SIZE(octeon_message_functions) && action;) { 73 if (action & 1) { 74 void (*fn)(void) = octeon_message_functions[i]; 75 76 if (fn) 77 fn(); 78 } 79 action >>= 1; 80 i++; 81 } 82 return IRQ_HANDLED; 83 } 84 85 /** 86 * Cause the function described by call_data to be executed on the passed 87 * cpu. When the function has finished, increment the finished field of 88 * call_data. 89 */ 90 void octeon_send_ipi_single(int cpu, unsigned int action) 91 { 92 int coreid = cpu_logical_map(cpu); 93 /* 94 pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu, 95 coreid, action); 96 */ 97 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); 98 } 99 100 static inline void octeon_send_ipi_mask(const struct cpumask *mask, 101 unsigned int action) 102 { 103 unsigned int i; 104 105 for_each_cpu(i, mask) 106 octeon_send_ipi_single(i, action); 107 } 108 109 /** 110 * Detect available CPUs, populate cpu_possible_mask 111 */ 112 static void octeon_smp_hotplug_setup(void) 113 { 114 #ifdef CONFIG_HOTPLUG_CPU 115 struct linux_app_boot_info *labi; 116 117 if (!setup_max_cpus) 118 return; 119 120 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 121 if (labi->labi_signature != LABI_SIGNATURE) { 122 pr_info("The bootloader on this board does not support HOTPLUG_CPU."); 123 return; 124 } 125 126 octeon_bootloader_entry_addr = labi->InitTLBStart_addr; 127 #endif 128 } 129 130 static void __init octeon_smp_setup(void) 131 { 132 const int coreid = cvmx_get_core_num(); 133 int cpus; 134 int id; 135 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); 136 137 #ifdef CONFIG_HOTPLUG_CPU 138 int core_mask = octeon_get_boot_coremask(); 139 unsigned int num_cores = cvmx_octeon_num_cores(); 140 #endif 141 142 /* The present CPUs are initially just the boot cpu (CPU 0). */ 143 for (id = 0; id < NR_CPUS; id++) { 144 set_cpu_possible(id, id == 0); 145 set_cpu_present(id, id == 0); 146 } 147 148 __cpu_number_map[coreid] = 0; 149 __cpu_logical_map[0] = coreid; 150 151 /* The present CPUs get the lowest CPU numbers. */ 152 cpus = 1; 153 for (id = 0; id < NR_CPUS; id++) { 154 if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) { 155 set_cpu_possible(cpus, true); 156 set_cpu_present(cpus, true); 157 __cpu_number_map[id] = cpus; 158 __cpu_logical_map[cpus] = id; 159 cpus++; 160 } 161 } 162 163 #ifdef CONFIG_HOTPLUG_CPU 164 /* 165 * The possible CPUs are all those present on the chip. We 166 * will assign CPU numbers for possible cores as well. Cores 167 * are always consecutively numberd from 0. 168 */ 169 for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr && 170 id < num_cores && id < NR_CPUS; id++) { 171 if (!(core_mask & (1 << id))) { 172 set_cpu_possible(cpus, true); 173 __cpu_number_map[id] = cpus; 174 __cpu_logical_map[cpus] = id; 175 cpus++; 176 } 177 } 178 #endif 179 180 octeon_smp_hotplug_setup(); 181 } 182 183 /** 184 * Firmware CPU startup hook 185 * 186 */ 187 static void octeon_boot_secondary(int cpu, struct task_struct *idle) 188 { 189 int count; 190 191 pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu, 192 cpu_logical_map(cpu)); 193 194 octeon_processor_sp = __KSTK_TOS(idle); 195 octeon_processor_gp = (unsigned long)(task_thread_info(idle)); 196 octeon_processor_boot = cpu_logical_map(cpu); 197 mb(); 198 199 count = 10000; 200 while (octeon_processor_sp && count) { 201 /* Waiting for processor to get the SP and GP */ 202 udelay(1); 203 count--; 204 } 205 if (count == 0) 206 pr_err("Secondary boot timeout\n"); 207 } 208 209 /** 210 * After we've done initial boot, this function is called to allow the 211 * board code to clean up state, if needed 212 */ 213 static void octeon_init_secondary(void) 214 { 215 unsigned int sr; 216 217 sr = set_c0_status(ST0_BEV); 218 write_c0_ebase((u32)ebase); 219 write_c0_status(sr); 220 221 octeon_check_cpu_bist(); 222 octeon_init_cvmcount(); 223 224 octeon_irq_setup_secondary(); 225 } 226 227 /** 228 * Callout to firmware before smp_init 229 * 230 */ 231 static void __init octeon_prepare_cpus(unsigned int max_cpus) 232 { 233 /* 234 * Only the low order mailbox bits are used for IPIs, leave 235 * the other bits alone. 236 */ 237 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff); 238 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, 239 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI", 240 mailbox_interrupt)) { 241 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)"); 242 } 243 } 244 245 /** 246 * Last chance for the board code to finish SMP initialization before 247 * the CPU is "online". 248 */ 249 static void octeon_smp_finish(void) 250 { 251 octeon_user_io_init(); 252 253 /* to generate the first CPU timer interrupt */ 254 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); 255 local_irq_enable(); 256 } 257 258 #ifdef CONFIG_HOTPLUG_CPU 259 260 /* State of each CPU. */ 261 DEFINE_PER_CPU(int, cpu_state); 262 263 static int octeon_cpu_disable(void) 264 { 265 unsigned int cpu = smp_processor_id(); 266 267 if (cpu == 0) 268 return -EBUSY; 269 270 if (!octeon_bootloader_entry_addr) 271 return -ENOTSUPP; 272 273 set_cpu_online(cpu, false); 274 cpumask_clear_cpu(cpu, &cpu_callin_map); 275 octeon_fixup_irqs(); 276 277 __flush_cache_all(); 278 local_flush_tlb_all(); 279 280 return 0; 281 } 282 283 static void octeon_cpu_die(unsigned int cpu) 284 { 285 int coreid = cpu_logical_map(cpu); 286 uint32_t mask, new_mask; 287 const struct cvmx_bootmem_named_block_desc *block_desc; 288 289 while (per_cpu(cpu_state, cpu) != CPU_DEAD) 290 cpu_relax(); 291 292 /* 293 * This is a bit complicated strategics of getting/settig available 294 * cores mask, copied from bootloader 295 */ 296 297 mask = 1 << coreid; 298 /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */ 299 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); 300 301 if (!block_desc) { 302 struct linux_app_boot_info *labi; 303 304 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 305 306 labi->avail_coremask |= mask; 307 new_mask = labi->avail_coremask; 308 } else { /* alternative, already initialized */ 309 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr + 310 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK); 311 *p |= mask; 312 new_mask = *p; 313 } 314 315 pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask); 316 mb(); 317 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); 318 cvmx_write_csr(CVMX_CIU_PP_RST, 0); 319 } 320 321 void play_dead(void) 322 { 323 int cpu = cpu_number_map(cvmx_get_core_num()); 324 325 idle_task_exit(); 326 octeon_processor_boot = 0xff; 327 per_cpu(cpu_state, cpu) = CPU_DEAD; 328 329 mb(); 330 331 while (1) /* core will be reset here */ 332 ; 333 } 334 335 extern void kernel_entry(unsigned long arg1, ...); 336 337 static void start_after_reset(void) 338 { 339 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */ 340 } 341 342 static int octeon_update_boot_vector(unsigned int cpu) 343 { 344 345 int coreid = cpu_logical_map(cpu); 346 uint32_t avail_coremask; 347 const struct cvmx_bootmem_named_block_desc *block_desc; 348 struct boot_init_vector *boot_vect = 349 (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR); 350 351 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); 352 353 if (!block_desc) { 354 struct linux_app_boot_info *labi; 355 356 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); 357 358 avail_coremask = labi->avail_coremask; 359 labi->avail_coremask &= ~(1 << coreid); 360 } else { /* alternative, already initialized */ 361 avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED( 362 block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK); 363 } 364 365 if (!(avail_coremask & (1 << coreid))) { 366 /* core not available, assume, that caught by simple-executive */ 367 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); 368 cvmx_write_csr(CVMX_CIU_PP_RST, 0); 369 } 370 371 boot_vect[coreid].app_start_func_addr = 372 (uint32_t) (unsigned long) start_after_reset; 373 boot_vect[coreid].code_addr = octeon_bootloader_entry_addr; 374 375 mb(); 376 377 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask); 378 379 return 0; 380 } 381 382 static int octeon_cpu_callback(struct notifier_block *nfb, 383 unsigned long action, void *hcpu) 384 { 385 unsigned int cpu = (unsigned long)hcpu; 386 387 switch (action & ~CPU_TASKS_FROZEN) { 388 case CPU_UP_PREPARE: 389 octeon_update_boot_vector(cpu); 390 break; 391 case CPU_ONLINE: 392 pr_info("Cpu %d online\n", cpu); 393 break; 394 case CPU_DEAD: 395 break; 396 } 397 398 return NOTIFY_OK; 399 } 400 401 static int register_cavium_notifier(void) 402 { 403 hotcpu_notifier(octeon_cpu_callback, 0); 404 return 0; 405 } 406 late_initcall(register_cavium_notifier); 407 408 #endif /* CONFIG_HOTPLUG_CPU */ 409 410 struct plat_smp_ops octeon_smp_ops = { 411 .send_ipi_single = octeon_send_ipi_single, 412 .send_ipi_mask = octeon_send_ipi_mask, 413 .init_secondary = octeon_init_secondary, 414 .smp_finish = octeon_smp_finish, 415 .boot_secondary = octeon_boot_secondary, 416 .smp_setup = octeon_smp_setup, 417 .prepare_cpus = octeon_prepare_cpus, 418 #ifdef CONFIG_HOTPLUG_CPU 419 .cpu_disable = octeon_cpu_disable, 420 .cpu_die = octeon_cpu_die, 421 #endif 422 }; 423 424 static irqreturn_t octeon_78xx_reched_interrupt(int irq, void *dev_id) 425 { 426 scheduler_ipi(); 427 return IRQ_HANDLED; 428 } 429 430 static irqreturn_t octeon_78xx_call_function_interrupt(int irq, void *dev_id) 431 { 432 generic_smp_call_function_interrupt(); 433 return IRQ_HANDLED; 434 } 435 436 static irqreturn_t octeon_78xx_icache_flush_interrupt(int irq, void *dev_id) 437 { 438 octeon_icache_flush(); 439 return IRQ_HANDLED; 440 } 441 442 /* 443 * Callout to firmware before smp_init 444 */ 445 static void octeon_78xx_prepare_cpus(unsigned int max_cpus) 446 { 447 if (request_irq(OCTEON_IRQ_MBOX0 + 0, 448 octeon_78xx_reched_interrupt, 449 IRQF_PERCPU | IRQF_NO_THREAD, "Scheduler", 450 octeon_78xx_reched_interrupt)) { 451 panic("Cannot request_irq for SchedulerIPI"); 452 } 453 if (request_irq(OCTEON_IRQ_MBOX0 + 1, 454 octeon_78xx_call_function_interrupt, 455 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-Call", 456 octeon_78xx_call_function_interrupt)) { 457 panic("Cannot request_irq for SMP-Call"); 458 } 459 if (request_irq(OCTEON_IRQ_MBOX0 + 2, 460 octeon_78xx_icache_flush_interrupt, 461 IRQF_PERCPU | IRQF_NO_THREAD, "ICache-Flush", 462 octeon_78xx_icache_flush_interrupt)) { 463 panic("Cannot request_irq for ICache-Flush"); 464 } 465 } 466 467 static void octeon_78xx_send_ipi_single(int cpu, unsigned int action) 468 { 469 int i; 470 471 for (i = 0; i < 8; i++) { 472 if (action & 1) 473 octeon_ciu3_mbox_send(cpu, i); 474 action >>= 1; 475 } 476 } 477 478 static void octeon_78xx_send_ipi_mask(const struct cpumask *mask, 479 unsigned int action) 480 { 481 unsigned int cpu; 482 483 for_each_cpu(cpu, mask) 484 octeon_78xx_send_ipi_single(cpu, action); 485 } 486 487 static struct plat_smp_ops octeon_78xx_smp_ops = { 488 .send_ipi_single = octeon_78xx_send_ipi_single, 489 .send_ipi_mask = octeon_78xx_send_ipi_mask, 490 .init_secondary = octeon_init_secondary, 491 .smp_finish = octeon_smp_finish, 492 .boot_secondary = octeon_boot_secondary, 493 .smp_setup = octeon_smp_setup, 494 .prepare_cpus = octeon_78xx_prepare_cpus, 495 #ifdef CONFIG_HOTPLUG_CPU 496 .cpu_disable = octeon_cpu_disable, 497 .cpu_die = octeon_cpu_die, 498 #endif 499 }; 500 501 void __init octeon_setup_smp(void) 502 { 503 struct plat_smp_ops *ops; 504 505 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) 506 ops = &octeon_78xx_smp_ops; 507 else 508 ops = &octeon_smp_ops; 509 510 register_smp_ops(ops); 511 } 512