1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2007 Cavium Networks 7 * Copyright (C) 2008, 2009 Wind River Systems 8 * written by Ralf Baechle <ralf@linux-mips.org> 9 */ 10 #include <linux/compiler.h> 11 #include <linux/vmalloc.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/console.h> 15 #include <linux/delay.h> 16 #include <linux/export.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/serial.h> 20 #include <linux/smp.h> 21 #include <linux/types.h> 22 #include <linux/string.h> /* for memset */ 23 #include <linux/tty.h> 24 #include <linux/time.h> 25 #include <linux/platform_device.h> 26 #include <linux/serial_core.h> 27 #include <linux/serial_8250.h> 28 #include <linux/of_fdt.h> 29 #include <linux/libfdt.h> 30 #include <linux/kexec.h> 31 32 #include <asm/processor.h> 33 #include <asm/reboot.h> 34 #include <asm/smp-ops.h> 35 #include <asm/irq_cpu.h> 36 #include <asm/mipsregs.h> 37 #include <asm/bootinfo.h> 38 #include <asm/sections.h> 39 #include <asm/time.h> 40 41 #include <asm/octeon/octeon.h> 42 #include <asm/octeon/pci-octeon.h> 43 #include <asm/octeon/cvmx-rst-defs.h> 44 45 /* 46 * TRUE for devices having registers with little-endian byte 47 * order, FALSE for registers with native-endian byte order. 48 * PCI mandates little-endian, USB and SATA are configuraable, 49 * but we chose little-endian for these. 50 */ 51 const bool octeon_should_swizzle_table[256] = { 52 [0x00] = true, /* bootbus/CF */ 53 [0x1b] = true, /* PCI mmio window */ 54 [0x1c] = true, /* PCI mmio window */ 55 [0x1d] = true, /* PCI mmio window */ 56 [0x1e] = true, /* PCI mmio window */ 57 [0x68] = true, /* OCTEON III USB */ 58 [0x69] = true, /* OCTEON III USB */ 59 [0x6c] = true, /* OCTEON III SATA */ 60 [0x6f] = true, /* OCTEON II USB */ 61 }; 62 EXPORT_SYMBOL(octeon_should_swizzle_table); 63 64 #ifdef CONFIG_PCI 65 extern void pci_console_init(const char *arg); 66 #endif 67 68 static unsigned long long max_memory = ULLONG_MAX; 69 static unsigned long long reserve_low_mem; 70 71 DEFINE_SEMAPHORE(octeon_bootbus_sem); 72 EXPORT_SYMBOL(octeon_bootbus_sem); 73 74 struct octeon_boot_descriptor *octeon_boot_desc_ptr; 75 76 struct cvmx_bootinfo *octeon_bootinfo; 77 EXPORT_SYMBOL(octeon_bootinfo); 78 79 #ifdef CONFIG_KEXEC 80 #ifdef CONFIG_SMP 81 /* 82 * Wait for relocation code is prepared and send 83 * secondary CPUs to spin until kernel is relocated. 84 */ 85 static void octeon_kexec_smp_down(void *ignored) 86 { 87 int cpu = smp_processor_id(); 88 89 local_irq_disable(); 90 set_cpu_online(cpu, false); 91 while (!atomic_read(&kexec_ready_to_reboot)) 92 cpu_relax(); 93 94 asm volatile ( 95 " sync \n" 96 " synci ($0) \n"); 97 98 relocated_kexec_smp_wait(NULL); 99 } 100 #endif 101 102 #define OCTEON_DDR0_BASE (0x0ULL) 103 #define OCTEON_DDR0_SIZE (0x010000000ULL) 104 #define OCTEON_DDR1_BASE (0x410000000ULL) 105 #define OCTEON_DDR1_SIZE (0x010000000ULL) 106 #define OCTEON_DDR2_BASE (0x020000000ULL) 107 #define OCTEON_DDR2_SIZE (0x3e0000000ULL) 108 #define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL) 109 110 static struct kimage *kimage_ptr; 111 112 static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes) 113 { 114 int64_t addr; 115 struct cvmx_bootmem_desc *bootmem_desc; 116 117 bootmem_desc = cvmx_bootmem_get_desc(); 118 119 if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) { 120 mem_size = OCTEON_MAX_PHY_MEM_SIZE; 121 pr_err("Error: requested memory too large," 122 "truncating to maximum size\n"); 123 } 124 125 bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER; 126 bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER; 127 128 addr = (OCTEON_DDR0_BASE + reserve_low_mem + low_reserved_bytes); 129 bootmem_desc->head_addr = 0; 130 131 if (mem_size <= OCTEON_DDR0_SIZE) { 132 __cvmx_bootmem_phy_free(addr, 133 mem_size - reserve_low_mem - 134 low_reserved_bytes, 0); 135 return; 136 } 137 138 __cvmx_bootmem_phy_free(addr, 139 OCTEON_DDR0_SIZE - reserve_low_mem - 140 low_reserved_bytes, 0); 141 142 mem_size -= OCTEON_DDR0_SIZE; 143 144 if (mem_size > OCTEON_DDR1_SIZE) { 145 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0); 146 __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE, 147 mem_size - OCTEON_DDR1_SIZE, 0); 148 } else 149 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0); 150 } 151 152 static int octeon_kexec_prepare(struct kimage *image) 153 { 154 int i; 155 char *bootloader = "kexec"; 156 157 octeon_boot_desc_ptr->argc = 0; 158 for (i = 0; i < image->nr_segments; i++) { 159 if (!strncmp(bootloader, (char *)image->segment[i].buf, 160 strlen(bootloader))) { 161 /* 162 * convert command line string to array 163 * of parameters (as bootloader does). 164 */ 165 int argc = 0, offt; 166 char *str = (char *)image->segment[i].buf; 167 char *ptr = strchr(str, ' '); 168 while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) { 169 *ptr = '\0'; 170 if (ptr[1] != ' ') { 171 offt = (int)(ptr - str + 1); 172 octeon_boot_desc_ptr->argv[argc] = 173 image->segment[i].mem + offt; 174 argc++; 175 } 176 ptr = strchr(ptr + 1, ' '); 177 } 178 octeon_boot_desc_ptr->argc = argc; 179 break; 180 } 181 } 182 183 /* 184 * Information about segments will be needed during pre-boot memory 185 * initialization. 186 */ 187 kimage_ptr = image; 188 return 0; 189 } 190 191 static void octeon_generic_shutdown(void) 192 { 193 int i; 194 #ifdef CONFIG_SMP 195 int cpu; 196 #endif 197 struct cvmx_bootmem_desc *bootmem_desc; 198 void *named_block_array_ptr; 199 200 bootmem_desc = cvmx_bootmem_get_desc(); 201 named_block_array_ptr = 202 cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr); 203 204 #ifdef CONFIG_SMP 205 /* disable watchdogs */ 206 for_each_online_cpu(cpu) 207 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 208 #else 209 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 210 #endif 211 if (kimage_ptr != kexec_crash_image) { 212 memset(named_block_array_ptr, 213 0x0, 214 CVMX_BOOTMEM_NUM_NAMED_BLOCKS * 215 sizeof(struct cvmx_bootmem_named_block_desc)); 216 /* 217 * Mark all memory (except low 0x100000 bytes) as free. 218 * It is the same thing that bootloader does. 219 */ 220 kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL, 221 0x100000); 222 /* 223 * Allocate all segments to avoid their corruption during boot. 224 */ 225 for (i = 0; i < kimage_ptr->nr_segments; i++) 226 cvmx_bootmem_alloc_address( 227 kimage_ptr->segment[i].memsz + 2*PAGE_SIZE, 228 kimage_ptr->segment[i].mem - PAGE_SIZE, 229 PAGE_SIZE); 230 } else { 231 /* 232 * Do not mark all memory as free. Free only named sections 233 * leaving the rest of memory unchanged. 234 */ 235 struct cvmx_bootmem_named_block_desc *ptr = 236 (struct cvmx_bootmem_named_block_desc *) 237 named_block_array_ptr; 238 239 for (i = 0; i < bootmem_desc->named_block_num_blocks; i++) 240 if (ptr[i].size) 241 cvmx_bootmem_free_named(ptr[i].name); 242 } 243 kexec_args[2] = 1UL; /* running on octeon_main_processor */ 244 kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; 245 #ifdef CONFIG_SMP 246 secondary_kexec_args[2] = 0UL; /* running on secondary cpu */ 247 secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; 248 #endif 249 } 250 251 static void octeon_shutdown(void) 252 { 253 octeon_generic_shutdown(); 254 #ifdef CONFIG_SMP 255 smp_call_function(octeon_kexec_smp_down, NULL, 0); 256 smp_wmb(); 257 while (num_online_cpus() > 1) { 258 cpu_relax(); 259 mdelay(1); 260 } 261 #endif 262 } 263 264 static void octeon_crash_shutdown(struct pt_regs *regs) 265 { 266 octeon_generic_shutdown(); 267 default_machine_crash_shutdown(regs); 268 } 269 270 #ifdef CONFIG_SMP 271 void octeon_crash_smp_send_stop(void) 272 { 273 int cpu; 274 275 /* disable watchdogs */ 276 for_each_online_cpu(cpu) 277 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 278 } 279 #endif 280 281 #endif /* CONFIG_KEXEC */ 282 283 #ifdef CONFIG_CAVIUM_RESERVE32 284 uint64_t octeon_reserve32_memory; 285 EXPORT_SYMBOL(octeon_reserve32_memory); 286 #endif 287 288 #ifdef CONFIG_KEXEC 289 /* crashkernel cmdline parameter is parsed _after_ memory setup 290 * we also parse it here (workaround for EHB5200) */ 291 static uint64_t crashk_size, crashk_base; 292 #endif 293 294 static int octeon_uart; 295 296 extern asmlinkage void handle_int(void); 297 298 /** 299 * Return non zero if we are currently running in the Octeon simulator 300 * 301 * Returns 302 */ 303 int octeon_is_simulation(void) 304 { 305 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; 306 } 307 EXPORT_SYMBOL(octeon_is_simulation); 308 309 /** 310 * Return true if Octeon is in PCI Host mode. This means 311 * Linux can control the PCI bus. 312 * 313 * Returns Non zero if Octeon in host mode. 314 */ 315 int octeon_is_pci_host(void) 316 { 317 #ifdef CONFIG_PCI 318 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; 319 #else 320 return 0; 321 #endif 322 } 323 324 /** 325 * Get the clock rate of Octeon 326 * 327 * Returns Clock rate in HZ 328 */ 329 uint64_t octeon_get_clock_rate(void) 330 { 331 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); 332 333 return sysinfo->cpu_clock_hz; 334 } 335 EXPORT_SYMBOL(octeon_get_clock_rate); 336 337 static u64 octeon_io_clock_rate; 338 339 u64 octeon_get_io_clock_rate(void) 340 { 341 return octeon_io_clock_rate; 342 } 343 EXPORT_SYMBOL(octeon_get_io_clock_rate); 344 345 346 /** 347 * Write to the LCD display connected to the bootbus. This display 348 * exists on most Cavium evaluation boards. If it doesn't exist, then 349 * this function doesn't do anything. 350 * 351 * @s: String to write 352 */ 353 void octeon_write_lcd(const char *s) 354 { 355 if (octeon_bootinfo->led_display_base_addr) { 356 void __iomem *lcd_address = 357 ioremap_nocache(octeon_bootinfo->led_display_base_addr, 358 8); 359 int i; 360 for (i = 0; i < 8; i++, s++) { 361 if (*s) 362 iowrite8(*s, lcd_address + i); 363 else 364 iowrite8(' ', lcd_address + i); 365 } 366 iounmap(lcd_address); 367 } 368 } 369 370 /** 371 * Return the console uart passed by the bootloader 372 * 373 * Returns uart (0 or 1) 374 */ 375 int octeon_get_boot_uart(void) 376 { 377 int uart; 378 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 379 uart = 1; 380 #else 381 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? 382 1 : 0; 383 #endif 384 return uart; 385 } 386 387 /** 388 * Get the coremask Linux was booted on. 389 * 390 * Returns Core mask 391 */ 392 int octeon_get_boot_coremask(void) 393 { 394 return octeon_boot_desc_ptr->core_mask; 395 } 396 397 /** 398 * Check the hardware BIST results for a CPU 399 */ 400 void octeon_check_cpu_bist(void) 401 { 402 const int coreid = cvmx_get_core_num(); 403 unsigned long long mask; 404 unsigned long long bist_val; 405 406 /* Check BIST results for COP0 registers */ 407 mask = 0x1f00000000ull; 408 bist_val = read_octeon_c0_icacheerr(); 409 if (bist_val & mask) 410 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", 411 coreid, bist_val); 412 413 bist_val = read_octeon_c0_dcacheerr(); 414 if (bist_val & 1) 415 pr_err("Core%d L1 Dcache parity error: " 416 "CacheErr(dcache) = 0x%llx\n", 417 coreid, bist_val); 418 419 mask = 0xfc00000000000000ull; 420 bist_val = read_c0_cvmmemctl(); 421 if (bist_val & mask) 422 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", 423 coreid, bist_val); 424 425 write_octeon_c0_dcacheerr(0); 426 } 427 428 /** 429 * Reboot Octeon 430 * 431 * @command: Command to pass to the bootloader. Currently ignored. 432 */ 433 static void octeon_restart(char *command) 434 { 435 /* Disable all watchdogs before soft reset. They don't get cleared */ 436 #ifdef CONFIG_SMP 437 int cpu; 438 for_each_online_cpu(cpu) 439 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 440 #else 441 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 442 #endif 443 444 mb(); 445 while (1) 446 if (OCTEON_IS_OCTEON3()) 447 cvmx_write_csr(CVMX_RST_SOFT_RST, 1); 448 else 449 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 450 } 451 452 453 /** 454 * Permanently stop a core. 455 * 456 * @arg: Ignored. 457 */ 458 static void octeon_kill_core(void *arg) 459 { 460 if (octeon_is_simulation()) 461 /* A break instruction causes the simulator stop a core */ 462 asm volatile ("break" ::: "memory"); 463 464 local_irq_disable(); 465 /* Disable watchdog on this core. */ 466 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 467 /* Spin in a low power mode. */ 468 while (true) 469 asm volatile ("wait" ::: "memory"); 470 } 471 472 473 /** 474 * Halt the system 475 */ 476 static void octeon_halt(void) 477 { 478 smp_call_function(octeon_kill_core, NULL, 0); 479 480 switch (octeon_bootinfo->board_type) { 481 case CVMX_BOARD_TYPE_NAO38: 482 /* Driving a 1 to GPIO 12 shuts off this board */ 483 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); 484 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); 485 break; 486 default: 487 octeon_write_lcd("PowerOff"); 488 break; 489 } 490 491 octeon_kill_core(NULL); 492 } 493 494 static char __read_mostly octeon_system_type[80]; 495 496 static void __init init_octeon_system_type(void) 497 { 498 char const *board_type; 499 500 board_type = cvmx_board_type_to_string(octeon_bootinfo->board_type); 501 if (board_type == NULL) { 502 struct device_node *root; 503 int ret; 504 505 root = of_find_node_by_path("/"); 506 ret = of_property_read_string(root, "model", &board_type); 507 of_node_put(root); 508 if (ret) 509 board_type = "Unsupported Board"; 510 } 511 512 snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)", 513 board_type, octeon_model_get_string(read_c0_prid())); 514 } 515 516 /** 517 * Return a string representing the system type 518 * 519 * Returns 520 */ 521 const char *octeon_board_type_string(void) 522 { 523 return octeon_system_type; 524 } 525 526 const char *get_system_type(void) 527 __attribute__ ((alias("octeon_board_type_string"))); 528 529 void octeon_user_io_init(void) 530 { 531 union octeon_cvmemctl cvmmemctl; 532 533 /* Get the current settings for CP0_CVMMEMCTL_REG */ 534 cvmmemctl.u64 = read_c0_cvmmemctl(); 535 /* R/W If set, marked write-buffer entries time out the same 536 * as as other entries; if clear, marked write-buffer entries 537 * use the maximum timeout. */ 538 cvmmemctl.s.dismarkwblongto = 1; 539 /* R/W If set, a merged store does not clear the write-buffer 540 * entry timeout state. */ 541 cvmmemctl.s.dismrgclrwbto = 0; 542 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM 543 * word location for an IOBDMA. The other 8 bits come from the 544 * SCRADDR field of the IOBDMA. */ 545 cvmmemctl.s.iobdmascrmsb = 0; 546 /* R/W If set, SYNCWS and SYNCS only order marked stores; if 547 * clear, SYNCWS and SYNCS only order unmarked 548 * stores. SYNCWSMARKED has no effect when DISSYNCWS is 549 * set. */ 550 cvmmemctl.s.syncwsmarked = 0; 551 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ 552 cvmmemctl.s.dissyncws = 0; 553 /* R/W If set, no stall happens on write buffer full. */ 554 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) 555 cvmmemctl.s.diswbfst = 1; 556 else 557 cvmmemctl.s.diswbfst = 0; 558 /* R/W If set (and SX set), supervisor-level loads/stores can 559 * use XKPHYS addresses with <48>==0 */ 560 cvmmemctl.s.xkmemenas = 0; 561 562 /* R/W If set (and UX set), user-level loads/stores can use 563 * XKPHYS addresses with VA<48>==0 */ 564 cvmmemctl.s.xkmemenau = 0; 565 566 /* R/W If set (and SX set), supervisor-level loads/stores can 567 * use XKPHYS addresses with VA<48>==1 */ 568 cvmmemctl.s.xkioenas = 0; 569 570 /* R/W If set (and UX set), user-level loads/stores can use 571 * XKPHYS addresses with VA<48>==1 */ 572 cvmmemctl.s.xkioenau = 0; 573 574 /* R/W If set, all stores act as SYNCW (NOMERGE must be set 575 * when this is set) RW, reset to 0. */ 576 cvmmemctl.s.allsyncw = 0; 577 578 /* R/W If set, no stores merge, and all stores reach the 579 * coherent bus in order. */ 580 cvmmemctl.s.nomerge = 0; 581 /* R/W Selects the bit in the counter used for DID time-outs 0 582 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is 583 * between 1x and 2x this interval. For example, with 584 * DIDTTO=3, expiration interval is between 16K and 32K. */ 585 cvmmemctl.s.didtto = 0; 586 /* R/W If set, the (mem) CSR clock never turns off. */ 587 cvmmemctl.s.csrckalwys = 0; 588 /* R/W If set, mclk never turns off. */ 589 cvmmemctl.s.mclkalwys = 0; 590 /* R/W Selects the bit in the counter used for write buffer 591 * flush time-outs (WBFLT+11) is the bit position in an 592 * internal counter used to determine expiration. The write 593 * buffer expires between 1x and 2x this interval. For 594 * example, with WBFLT = 0, a write buffer expires between 2K 595 * and 4K cycles after the write buffer entry is allocated. */ 596 cvmmemctl.s.wbfltime = 0; 597 /* R/W If set, do not put Istream in the L2 cache. */ 598 cvmmemctl.s.istrnol2 = 0; 599 600 /* 601 * R/W The write buffer threshold. As per erratum Core-14752 602 * for CN63XX, a sc/scd might fail if the write buffer is 603 * full. Lowering WBTHRESH greatly lowers the chances of the 604 * write buffer ever being full and triggering the erratum. 605 */ 606 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) 607 cvmmemctl.s.wbthresh = 4; 608 else 609 cvmmemctl.s.wbthresh = 10; 610 611 /* R/W If set, CVMSEG is available for loads/stores in 612 * kernel/debug mode. */ 613 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 614 cvmmemctl.s.cvmsegenak = 1; 615 #else 616 cvmmemctl.s.cvmsegenak = 0; 617 #endif 618 /* R/W If set, CVMSEG is available for loads/stores in 619 * supervisor mode. */ 620 cvmmemctl.s.cvmsegenas = 0; 621 /* R/W If set, CVMSEG is available for loads/stores in user 622 * mode. */ 623 cvmmemctl.s.cvmsegenau = 0; 624 625 write_c0_cvmmemctl(cvmmemctl.u64); 626 627 /* Setup of CVMSEG is done in kernel-entry-init.h */ 628 if (smp_processor_id() == 0) 629 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", 630 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, 631 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); 632 633 if (octeon_has_feature(OCTEON_FEATURE_FAU)) { 634 union cvmx_iob_fau_timeout fau_timeout; 635 636 /* Set a default for the hardware timeouts */ 637 fau_timeout.u64 = 0; 638 fau_timeout.s.tout_val = 0xfff; 639 /* Disable tagwait FAU timeout */ 640 fau_timeout.s.tout_enb = 0; 641 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); 642 } 643 644 if ((!OCTEON_IS_MODEL(OCTEON_CN68XX) && 645 !OCTEON_IS_MODEL(OCTEON_CN7XXX)) || 646 OCTEON_IS_MODEL(OCTEON_CN70XX)) { 647 union cvmx_pow_nw_tim nm_tim; 648 649 nm_tim.u64 = 0; 650 /* 4096 cycles */ 651 nm_tim.s.nw_tim = 3; 652 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); 653 } 654 655 write_octeon_c0_icacheerr(0); 656 write_c0_derraddr1(0); 657 } 658 659 /** 660 * Early entry point for arch setup 661 */ 662 void __init prom_init(void) 663 { 664 struct cvmx_sysinfo *sysinfo; 665 const char *arg; 666 char *p; 667 int i; 668 u64 t; 669 int argc; 670 #ifdef CONFIG_CAVIUM_RESERVE32 671 int64_t addr = -1; 672 #endif 673 /* 674 * The bootloader passes a pointer to the boot descriptor in 675 * $a3, this is available as fw_arg3. 676 */ 677 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; 678 octeon_bootinfo = 679 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); 680 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); 681 682 sysinfo = cvmx_sysinfo_get(); 683 memset(sysinfo, 0, sizeof(*sysinfo)); 684 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; 685 sysinfo->phy_mem_desc_addr = (u64)phys_to_virt(octeon_bootinfo->phy_mem_desc_addr); 686 687 if ((octeon_bootinfo->major_version > 1) || 688 (octeon_bootinfo->major_version == 1 && 689 octeon_bootinfo->minor_version >= 4)) 690 cvmx_coremask_copy(&sysinfo->core_mask, 691 &octeon_bootinfo->ext_core_mask); 692 else 693 cvmx_coremask_set64(&sysinfo->core_mask, 694 octeon_bootinfo->core_mask); 695 696 /* Some broken u-boot pass garbage in upper bits, clear them out */ 697 if (!OCTEON_IS_MODEL(OCTEON_CN78XX)) 698 for (i = 512; i < 1024; i++) 699 cvmx_coremask_clear_core(&sysinfo->core_mask, i); 700 701 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; 702 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; 703 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; 704 sysinfo->board_type = octeon_bootinfo->board_type; 705 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; 706 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; 707 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, 708 sizeof(sysinfo->mac_addr_base)); 709 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; 710 memcpy(sysinfo->board_serial_number, 711 octeon_bootinfo->board_serial_number, 712 sizeof(sysinfo->board_serial_number)); 713 sysinfo->compact_flash_common_base_addr = 714 octeon_bootinfo->compact_flash_common_base_addr; 715 sysinfo->compact_flash_attribute_base_addr = 716 octeon_bootinfo->compact_flash_attribute_base_addr; 717 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; 718 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; 719 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; 720 721 if (OCTEON_IS_OCTEON2()) { 722 /* I/O clock runs at a different rate than the CPU. */ 723 union cvmx_mio_rst_boot rst_boot; 724 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); 725 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; 726 } else if (OCTEON_IS_OCTEON3()) { 727 /* I/O clock runs at a different rate than the CPU. */ 728 union cvmx_rst_boot rst_boot; 729 rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT); 730 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; 731 } else { 732 octeon_io_clock_rate = sysinfo->cpu_clock_hz; 733 } 734 735 t = read_c0_cvmctl(); 736 if ((t & (1ull << 27)) == 0) { 737 /* 738 * Setup the multiplier save/restore code if 739 * CvmCtl[NOMUL] clear. 740 */ 741 void *save; 742 void *save_end; 743 void *restore; 744 void *restore_end; 745 int save_len; 746 int restore_len; 747 int save_max = (char *)octeon_mult_save_end - 748 (char *)octeon_mult_save; 749 int restore_max = (char *)octeon_mult_restore_end - 750 (char *)octeon_mult_restore; 751 if (current_cpu_data.cputype == CPU_CAVIUM_OCTEON3) { 752 save = octeon_mult_save3; 753 save_end = octeon_mult_save3_end; 754 restore = octeon_mult_restore3; 755 restore_end = octeon_mult_restore3_end; 756 } else { 757 save = octeon_mult_save2; 758 save_end = octeon_mult_save2_end; 759 restore = octeon_mult_restore2; 760 restore_end = octeon_mult_restore2_end; 761 } 762 save_len = (char *)save_end - (char *)save; 763 restore_len = (char *)restore_end - (char *)restore; 764 if (!WARN_ON(save_len > save_max || 765 restore_len > restore_max)) { 766 memcpy(octeon_mult_save, save, save_len); 767 memcpy(octeon_mult_restore, restore, restore_len); 768 } 769 } 770 771 /* 772 * Only enable the LED controller if we're running on a CN38XX, CN58XX, 773 * or CN56XX. The CN30XX and CN31XX don't have an LED controller. 774 */ 775 if (!octeon_is_simulation() && 776 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { 777 cvmx_write_csr(CVMX_LED_EN, 0); 778 cvmx_write_csr(CVMX_LED_PRT, 0); 779 cvmx_write_csr(CVMX_LED_DBG, 0); 780 cvmx_write_csr(CVMX_LED_PRT_FMT, 0); 781 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); 782 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); 783 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); 784 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); 785 cvmx_write_csr(CVMX_LED_EN, 1); 786 } 787 #ifdef CONFIG_CAVIUM_RESERVE32 788 /* 789 * We need to temporarily allocate all memory in the reserve32 790 * region. This makes sure the kernel doesn't allocate this 791 * memory when it is getting memory from the 792 * bootloader. Later, after the memory allocations are 793 * complete, the reserve32 will be freed. 794 * 795 * Allocate memory for RESERVED32 aligned on 2MB boundary. This 796 * is in case we later use hugetlb entries with it. 797 */ 798 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, 799 0, 0, 2 << 20, 800 "CAVIUM_RESERVE32", 0); 801 if (addr < 0) 802 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); 803 else 804 octeon_reserve32_memory = addr; 805 #endif 806 807 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 808 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { 809 pr_info("Skipping L2 locking due to reduced L2 cache size\n"); 810 } else { 811 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000; 812 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB 813 /* TLB refill */ 814 cvmx_l2c_lock_mem_region(ebase, 0x100); 815 #endif 816 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION 817 /* General exception */ 818 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); 819 #endif 820 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 821 /* Interrupt handler */ 822 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); 823 #endif 824 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT 825 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); 826 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); 827 #endif 828 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY 829 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); 830 #endif 831 } 832 #endif 833 834 octeon_check_cpu_bist(); 835 836 octeon_uart = octeon_get_boot_uart(); 837 838 #ifdef CONFIG_SMP 839 octeon_write_lcd("LinuxSMP"); 840 #else 841 octeon_write_lcd("Linux"); 842 #endif 843 844 octeon_setup_delays(); 845 846 /* 847 * BIST should always be enabled when doing a soft reset. L2 848 * Cache locking for instance is not cleared unless BIST is 849 * enabled. Unfortunately due to a chip errata G-200 for 850 * Cn38XX and CN31XX, BIST msut be disabled on these parts. 851 */ 852 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || 853 OCTEON_IS_MODEL(OCTEON_CN31XX)) 854 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); 855 else 856 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); 857 858 /* Default to 64MB in the simulator to speed things up */ 859 if (octeon_is_simulation()) 860 max_memory = 64ull << 20; 861 862 arg = strstr(arcs_cmdline, "mem="); 863 if (arg) { 864 max_memory = memparse(arg + 4, &p); 865 if (max_memory == 0) 866 max_memory = 32ull << 30; 867 if (*p == '@') 868 reserve_low_mem = memparse(p + 1, &p); 869 } 870 871 arcs_cmdline[0] = 0; 872 argc = octeon_boot_desc_ptr->argc; 873 for (i = 0; i < argc; i++) { 874 const char *arg = 875 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); 876 if ((strncmp(arg, "MEM=", 4) == 0) || 877 (strncmp(arg, "mem=", 4) == 0)) { 878 max_memory = memparse(arg + 4, &p); 879 if (max_memory == 0) 880 max_memory = 32ull << 30; 881 if (*p == '@') 882 reserve_low_mem = memparse(p + 1, &p); 883 #ifdef CONFIG_KEXEC 884 } else if (strncmp(arg, "crashkernel=", 12) == 0) { 885 crashk_size = memparse(arg+12, &p); 886 if (*p == '@') 887 crashk_base = memparse(p+1, &p); 888 strcat(arcs_cmdline, " "); 889 strcat(arcs_cmdline, arg); 890 /* 891 * To do: switch parsing to new style, something like: 892 * parse_crashkernel(arg, sysinfo->system_dram_size, 893 * &crashk_size, &crashk_base); 894 */ 895 #endif 896 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < 897 sizeof(arcs_cmdline) - 1) { 898 strcat(arcs_cmdline, " "); 899 strcat(arcs_cmdline, arg); 900 } 901 } 902 903 if (strstr(arcs_cmdline, "console=") == NULL) { 904 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 905 strcat(arcs_cmdline, " console=ttyS0,115200"); 906 #else 907 if (octeon_uart == 1) 908 strcat(arcs_cmdline, " console=ttyS1,115200"); 909 else 910 strcat(arcs_cmdline, " console=ttyS0,115200"); 911 #endif 912 } 913 914 mips_hpt_frequency = octeon_get_clock_rate(); 915 916 octeon_init_cvmcount(); 917 918 _machine_restart = octeon_restart; 919 _machine_halt = octeon_halt; 920 921 #ifdef CONFIG_KEXEC 922 _machine_kexec_shutdown = octeon_shutdown; 923 _machine_crash_shutdown = octeon_crash_shutdown; 924 _machine_kexec_prepare = octeon_kexec_prepare; 925 #ifdef CONFIG_SMP 926 _crash_smp_send_stop = octeon_crash_smp_send_stop; 927 #endif 928 #endif 929 930 octeon_user_io_init(); 931 octeon_setup_smp(); 932 } 933 934 /* Exclude a single page from the regions obtained in plat_mem_setup. */ 935 #ifndef CONFIG_CRASH_DUMP 936 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) 937 { 938 if (addr > *mem && addr < *mem + *size) { 939 u64 inc = addr - *mem; 940 add_memory_region(*mem, inc, BOOT_MEM_RAM); 941 *mem += inc; 942 *size -= inc; 943 } 944 945 if (addr == *mem && *size > PAGE_SIZE) { 946 *mem += PAGE_SIZE; 947 *size -= PAGE_SIZE; 948 } 949 } 950 #endif /* CONFIG_CRASH_DUMP */ 951 952 void __init fw_init_cmdline(void) 953 { 954 int i; 955 956 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; 957 for (i = 0; i < octeon_boot_desc_ptr->argc; i++) { 958 const char *arg = 959 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); 960 if (strlen(arcs_cmdline) + strlen(arg) + 1 < 961 sizeof(arcs_cmdline) - 1) { 962 strcat(arcs_cmdline, " "); 963 strcat(arcs_cmdline, arg); 964 } 965 } 966 } 967 968 void __init *plat_get_fdt(void) 969 { 970 octeon_bootinfo = 971 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); 972 return phys_to_virt(octeon_bootinfo->fdt_addr); 973 } 974 975 void __init plat_mem_setup(void) 976 { 977 uint64_t mem_alloc_size; 978 uint64_t total; 979 uint64_t crashk_end; 980 #ifndef CONFIG_CRASH_DUMP 981 int64_t memory; 982 uint64_t kernel_start; 983 uint64_t kernel_size; 984 #endif 985 986 total = 0; 987 crashk_end = 0; 988 989 /* 990 * The Mips memory init uses the first memory location for 991 * some memory vectors. When SPARSEMEM is in use, it doesn't 992 * verify that the size is big enough for the final 993 * vectors. Making the smallest chuck 4MB seems to be enough 994 * to consistently work. 995 */ 996 mem_alloc_size = 4 << 20; 997 if (mem_alloc_size > max_memory) 998 mem_alloc_size = max_memory; 999 1000 /* Crashkernel ignores bootmem list. It relies on mem=X@Y option */ 1001 #ifdef CONFIG_CRASH_DUMP 1002 add_memory_region(reserve_low_mem, max_memory, BOOT_MEM_RAM); 1003 total += max_memory; 1004 #else 1005 #ifdef CONFIG_KEXEC 1006 if (crashk_size > 0) { 1007 add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM); 1008 crashk_end = crashk_base + crashk_size; 1009 } 1010 #endif 1011 /* 1012 * When allocating memory, we want incrementing addresses from 1013 * bootmem_alloc so the code in add_memory_region can merge 1014 * regions next to each other. 1015 */ 1016 cvmx_bootmem_lock(); 1017 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) 1018 && (total < max_memory)) { 1019 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 1020 __pa_symbol(&_end), -1, 1021 0x100000, 1022 CVMX_BOOTMEM_FLAG_NO_LOCKING); 1023 if (memory >= 0) { 1024 u64 size = mem_alloc_size; 1025 #ifdef CONFIG_KEXEC 1026 uint64_t end; 1027 #endif 1028 1029 /* 1030 * exclude a page at the beginning and end of 1031 * the 256MB PCIe 'hole' so the kernel will not 1032 * try to allocate multi-page buffers that 1033 * span the discontinuity. 1034 */ 1035 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE, 1036 &memory, &size); 1037 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE + 1038 CVMX_PCIE_BAR1_PHYS_SIZE, 1039 &memory, &size); 1040 #ifdef CONFIG_KEXEC 1041 end = memory + mem_alloc_size; 1042 1043 /* 1044 * This function automatically merges address regions 1045 * next to each other if they are received in 1046 * incrementing order 1047 */ 1048 if (memory < crashk_base && end > crashk_end) { 1049 /* region is fully in */ 1050 add_memory_region(memory, 1051 crashk_base - memory, 1052 BOOT_MEM_RAM); 1053 total += crashk_base - memory; 1054 add_memory_region(crashk_end, 1055 end - crashk_end, 1056 BOOT_MEM_RAM); 1057 total += end - crashk_end; 1058 continue; 1059 } 1060 1061 if (memory >= crashk_base && end <= crashk_end) 1062 /* 1063 * Entire memory region is within the new 1064 * kernel's memory, ignore it. 1065 */ 1066 continue; 1067 1068 if (memory > crashk_base && memory < crashk_end && 1069 end > crashk_end) { 1070 /* 1071 * Overlap with the beginning of the region, 1072 * reserve the beginning. 1073 */ 1074 mem_alloc_size -= crashk_end - memory; 1075 memory = crashk_end; 1076 } else if (memory < crashk_base && end > crashk_base && 1077 end < crashk_end) 1078 /* 1079 * Overlap with the beginning of the region, 1080 * chop of end. 1081 */ 1082 mem_alloc_size -= end - crashk_base; 1083 #endif 1084 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); 1085 total += mem_alloc_size; 1086 /* Recovering mem_alloc_size */ 1087 mem_alloc_size = 4 << 20; 1088 } else { 1089 break; 1090 } 1091 } 1092 cvmx_bootmem_unlock(); 1093 /* Add the memory region for the kernel. */ 1094 kernel_start = (unsigned long) _text; 1095 kernel_size = _end - _text; 1096 1097 /* Adjust for physical offset. */ 1098 kernel_start &= ~0xffffffff80000000ULL; 1099 add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM); 1100 #endif /* CONFIG_CRASH_DUMP */ 1101 1102 #ifdef CONFIG_CAVIUM_RESERVE32 1103 /* 1104 * Now that we've allocated the kernel memory it is safe to 1105 * free the reserved region. We free it here so that builtin 1106 * drivers can use the memory. 1107 */ 1108 if (octeon_reserve32_memory) 1109 cvmx_bootmem_free_named("CAVIUM_RESERVE32"); 1110 #endif /* CONFIG_CAVIUM_RESERVE32 */ 1111 1112 if (total == 0) 1113 panic("Unable to allocate memory from " 1114 "cvmx_bootmem_phy_alloc"); 1115 } 1116 1117 /* 1118 * Emit one character to the boot UART. Exported for use by the 1119 * watchdog timer. 1120 */ 1121 int prom_putchar(char c) 1122 { 1123 uint64_t lsrval; 1124 1125 /* Spin until there is room */ 1126 do { 1127 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); 1128 } while ((lsrval & 0x20) == 0); 1129 1130 /* Write the byte */ 1131 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); 1132 return 1; 1133 } 1134 EXPORT_SYMBOL(prom_putchar); 1135 1136 void __init prom_free_prom_memory(void) 1137 { 1138 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) { 1139 /* Check for presence of Core-14449 fix. */ 1140 u32 insn; 1141 u32 *foo; 1142 1143 foo = &insn; 1144 1145 asm volatile("# before" : : : "memory"); 1146 prefetch(foo); 1147 asm volatile( 1148 ".set push\n\t" 1149 ".set noreorder\n\t" 1150 "bal 1f\n\t" 1151 "nop\n" 1152 "1:\tlw %0,-12($31)\n\t" 1153 ".set pop\n\t" 1154 : "=r" (insn) : : "$31", "memory"); 1155 1156 if ((insn >> 26) != 0x33) 1157 panic("No PREF instruction at Core-14449 probe point."); 1158 1159 if (((insn >> 16) & 0x1f) != 28) 1160 panic("OCTEON II DCache prefetch workaround not in place (%04x).\n" 1161 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", 1162 insn); 1163 } 1164 } 1165 1166 void __init octeon_fill_mac_addresses(void); 1167 int octeon_prune_device_tree(void); 1168 1169 extern const char __appended_dtb; 1170 extern const char __dtb_octeon_3xxx_begin; 1171 extern const char __dtb_octeon_68xx_begin; 1172 void __init device_tree_init(void) 1173 { 1174 const void *fdt; 1175 bool do_prune; 1176 bool fill_mac; 1177 1178 #ifdef CONFIG_MIPS_ELF_APPENDED_DTB 1179 if (!fdt_check_header(&__appended_dtb)) { 1180 fdt = &__appended_dtb; 1181 do_prune = false; 1182 fill_mac = true; 1183 pr_info("Using appended Device Tree.\n"); 1184 } else 1185 #endif 1186 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { 1187 fdt = phys_to_virt(octeon_bootinfo->fdt_addr); 1188 if (fdt_check_header(fdt)) 1189 panic("Corrupt Device Tree passed to kernel."); 1190 do_prune = false; 1191 fill_mac = false; 1192 pr_info("Using passed Device Tree.\n"); 1193 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { 1194 fdt = &__dtb_octeon_68xx_begin; 1195 do_prune = true; 1196 fill_mac = true; 1197 } else { 1198 fdt = &__dtb_octeon_3xxx_begin; 1199 do_prune = true; 1200 fill_mac = true; 1201 } 1202 1203 initial_boot_params = (void *)fdt; 1204 1205 if (do_prune) { 1206 octeon_prune_device_tree(); 1207 pr_info("Using internal Device Tree.\n"); 1208 } 1209 if (fill_mac) 1210 octeon_fill_mac_addresses(); 1211 unflatten_and_copy_device_tree(); 1212 init_octeon_system_type(); 1213 } 1214 1215 static int __initdata disable_octeon_edac_p; 1216 1217 static int __init disable_octeon_edac(char *str) 1218 { 1219 disable_octeon_edac_p = 1; 1220 return 0; 1221 } 1222 early_param("disable_octeon_edac", disable_octeon_edac); 1223 1224 static char *edac_device_names[] = { 1225 "octeon_l2c_edac", 1226 "octeon_pc_edac", 1227 }; 1228 1229 static int __init edac_devinit(void) 1230 { 1231 struct platform_device *dev; 1232 int i, err = 0; 1233 int num_lmc; 1234 char *name; 1235 1236 if (disable_octeon_edac_p) 1237 return 0; 1238 1239 for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) { 1240 name = edac_device_names[i]; 1241 dev = platform_device_register_simple(name, -1, NULL, 0); 1242 if (IS_ERR(dev)) { 1243 pr_err("Registration of %s failed!\n", name); 1244 err = PTR_ERR(dev); 1245 } 1246 } 1247 1248 num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 : 1249 (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1); 1250 for (i = 0; i < num_lmc; i++) { 1251 dev = platform_device_register_simple("octeon_lmc_edac", 1252 i, NULL, 0); 1253 if (IS_ERR(dev)) { 1254 pr_err("Registration of octeon_lmc_edac %d failed!\n", i); 1255 err = PTR_ERR(dev); 1256 } 1257 } 1258 1259 return err; 1260 } 1261 device_initcall(edac_devinit); 1262 1263 static void __initdata *octeon_dummy_iospace; 1264 1265 static int __init octeon_no_pci_init(void) 1266 { 1267 /* 1268 * Initially assume there is no PCI. The PCI/PCIe platform code will 1269 * later re-initialize these to correct values if they are present. 1270 */ 1271 octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT); 1272 set_io_port_base((unsigned long)octeon_dummy_iospace); 1273 ioport_resource.start = MAX_RESOURCE; 1274 ioport_resource.end = 0; 1275 return 0; 1276 } 1277 core_initcall(octeon_no_pci_init); 1278 1279 static int __init octeon_no_pci_release(void) 1280 { 1281 /* 1282 * Release the allocated memory if a real IO space is there. 1283 */ 1284 if ((unsigned long)octeon_dummy_iospace != mips_io_port_base) 1285 vfree(octeon_dummy_iospace); 1286 return 0; 1287 } 1288 late_initcall(octeon_no_pci_release); 1289