1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2007 Cavium Networks 7 * Copyright (C) 2008, 2009 Wind River Systems 8 * written by Ralf Baechle <ralf@linux-mips.org> 9 */ 10 #include <linux/compiler.h> 11 #include <linux/vmalloc.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/console.h> 15 #include <linux/delay.h> 16 #include <linux/export.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/serial.h> 20 #include <linux/smp.h> 21 #include <linux/types.h> 22 #include <linux/string.h> /* for memset */ 23 #include <linux/tty.h> 24 #include <linux/time.h> 25 #include <linux/platform_device.h> 26 #include <linux/serial_core.h> 27 #include <linux/serial_8250.h> 28 #include <linux/of_fdt.h> 29 #include <linux/libfdt.h> 30 #include <linux/kexec.h> 31 32 #include <asm/processor.h> 33 #include <asm/reboot.h> 34 #include <asm/smp-ops.h> 35 #include <asm/irq_cpu.h> 36 #include <asm/mipsregs.h> 37 #include <asm/bootinfo.h> 38 #include <asm/sections.h> 39 #include <asm/time.h> 40 41 #include <asm/octeon/octeon.h> 42 #include <asm/octeon/pci-octeon.h> 43 #include <asm/octeon/cvmx-mio-defs.h> 44 #include <asm/octeon/cvmx-rst-defs.h> 45 46 extern struct plat_smp_ops octeon_smp_ops; 47 48 #ifdef CONFIG_PCI 49 extern void pci_console_init(const char *arg); 50 #endif 51 52 static unsigned long long MAX_MEMORY = 512ull << 20; 53 54 struct octeon_boot_descriptor *octeon_boot_desc_ptr; 55 56 struct cvmx_bootinfo *octeon_bootinfo; 57 EXPORT_SYMBOL(octeon_bootinfo); 58 59 static unsigned long long RESERVE_LOW_MEM = 0ull; 60 #ifdef CONFIG_KEXEC 61 #ifdef CONFIG_SMP 62 /* 63 * Wait for relocation code is prepared and send 64 * secondary CPUs to spin until kernel is relocated. 65 */ 66 static void octeon_kexec_smp_down(void *ignored) 67 { 68 int cpu = smp_processor_id(); 69 70 local_irq_disable(); 71 set_cpu_online(cpu, false); 72 while (!atomic_read(&kexec_ready_to_reboot)) 73 cpu_relax(); 74 75 asm volatile ( 76 " sync \n" 77 " synci ($0) \n"); 78 79 relocated_kexec_smp_wait(NULL); 80 } 81 #endif 82 83 #define OCTEON_DDR0_BASE (0x0ULL) 84 #define OCTEON_DDR0_SIZE (0x010000000ULL) 85 #define OCTEON_DDR1_BASE (0x410000000ULL) 86 #define OCTEON_DDR1_SIZE (0x010000000ULL) 87 #define OCTEON_DDR2_BASE (0x020000000ULL) 88 #define OCTEON_DDR2_SIZE (0x3e0000000ULL) 89 #define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL) 90 91 static struct kimage *kimage_ptr; 92 93 static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes) 94 { 95 int64_t addr; 96 struct cvmx_bootmem_desc *bootmem_desc; 97 98 bootmem_desc = cvmx_bootmem_get_desc(); 99 100 if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) { 101 mem_size = OCTEON_MAX_PHY_MEM_SIZE; 102 pr_err("Error: requested memory too large," 103 "truncating to maximum size\n"); 104 } 105 106 bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER; 107 bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER; 108 109 addr = (OCTEON_DDR0_BASE + RESERVE_LOW_MEM + low_reserved_bytes); 110 bootmem_desc->head_addr = 0; 111 112 if (mem_size <= OCTEON_DDR0_SIZE) { 113 __cvmx_bootmem_phy_free(addr, 114 mem_size - RESERVE_LOW_MEM - 115 low_reserved_bytes, 0); 116 return; 117 } 118 119 __cvmx_bootmem_phy_free(addr, 120 OCTEON_DDR0_SIZE - RESERVE_LOW_MEM - 121 low_reserved_bytes, 0); 122 123 mem_size -= OCTEON_DDR0_SIZE; 124 125 if (mem_size > OCTEON_DDR1_SIZE) { 126 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0); 127 __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE, 128 mem_size - OCTEON_DDR1_SIZE, 0); 129 } else 130 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0); 131 } 132 133 static int octeon_kexec_prepare(struct kimage *image) 134 { 135 int i; 136 char *bootloader = "kexec"; 137 138 octeon_boot_desc_ptr->argc = 0; 139 for (i = 0; i < image->nr_segments; i++) { 140 if (!strncmp(bootloader, (char *)image->segment[i].buf, 141 strlen(bootloader))) { 142 /* 143 * convert command line string to array 144 * of parameters (as bootloader does). 145 */ 146 int argc = 0, offt; 147 char *str = (char *)image->segment[i].buf; 148 char *ptr = strchr(str, ' '); 149 while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) { 150 *ptr = '\0'; 151 if (ptr[1] != ' ') { 152 offt = (int)(ptr - str + 1); 153 octeon_boot_desc_ptr->argv[argc] = 154 image->segment[i].mem + offt; 155 argc++; 156 } 157 ptr = strchr(ptr + 1, ' '); 158 } 159 octeon_boot_desc_ptr->argc = argc; 160 break; 161 } 162 } 163 164 /* 165 * Information about segments will be needed during pre-boot memory 166 * initialization. 167 */ 168 kimage_ptr = image; 169 return 0; 170 } 171 172 static void octeon_generic_shutdown(void) 173 { 174 int i; 175 #ifdef CONFIG_SMP 176 int cpu; 177 #endif 178 struct cvmx_bootmem_desc *bootmem_desc; 179 void *named_block_array_ptr; 180 181 bootmem_desc = cvmx_bootmem_get_desc(); 182 named_block_array_ptr = 183 cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr); 184 185 #ifdef CONFIG_SMP 186 /* disable watchdogs */ 187 for_each_online_cpu(cpu) 188 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 189 #else 190 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 191 #endif 192 if (kimage_ptr != kexec_crash_image) { 193 memset(named_block_array_ptr, 194 0x0, 195 CVMX_BOOTMEM_NUM_NAMED_BLOCKS * 196 sizeof(struct cvmx_bootmem_named_block_desc)); 197 /* 198 * Mark all memory (except low 0x100000 bytes) as free. 199 * It is the same thing that bootloader does. 200 */ 201 kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL, 202 0x100000); 203 /* 204 * Allocate all segments to avoid their corruption during boot. 205 */ 206 for (i = 0; i < kimage_ptr->nr_segments; i++) 207 cvmx_bootmem_alloc_address( 208 kimage_ptr->segment[i].memsz + 2*PAGE_SIZE, 209 kimage_ptr->segment[i].mem - PAGE_SIZE, 210 PAGE_SIZE); 211 } else { 212 /* 213 * Do not mark all memory as free. Free only named sections 214 * leaving the rest of memory unchanged. 215 */ 216 struct cvmx_bootmem_named_block_desc *ptr = 217 (struct cvmx_bootmem_named_block_desc *) 218 named_block_array_ptr; 219 220 for (i = 0; i < bootmem_desc->named_block_num_blocks; i++) 221 if (ptr[i].size) 222 cvmx_bootmem_free_named(ptr[i].name); 223 } 224 kexec_args[2] = 1UL; /* running on octeon_main_processor */ 225 kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; 226 #ifdef CONFIG_SMP 227 secondary_kexec_args[2] = 0UL; /* running on secondary cpu */ 228 secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; 229 #endif 230 } 231 232 static void octeon_shutdown(void) 233 { 234 octeon_generic_shutdown(); 235 #ifdef CONFIG_SMP 236 smp_call_function(octeon_kexec_smp_down, NULL, 0); 237 smp_wmb(); 238 while (num_online_cpus() > 1) { 239 cpu_relax(); 240 mdelay(1); 241 } 242 #endif 243 } 244 245 static void octeon_crash_shutdown(struct pt_regs *regs) 246 { 247 octeon_generic_shutdown(); 248 default_machine_crash_shutdown(regs); 249 } 250 251 #endif /* CONFIG_KEXEC */ 252 253 #ifdef CONFIG_CAVIUM_RESERVE32 254 uint64_t octeon_reserve32_memory; 255 EXPORT_SYMBOL(octeon_reserve32_memory); 256 #endif 257 258 #ifdef CONFIG_KEXEC 259 /* crashkernel cmdline parameter is parsed _after_ memory setup 260 * we also parse it here (workaround for EHB5200) */ 261 static uint64_t crashk_size, crashk_base; 262 #endif 263 264 static int octeon_uart; 265 266 extern asmlinkage void handle_int(void); 267 268 /** 269 * Return non zero if we are currently running in the Octeon simulator 270 * 271 * Returns 272 */ 273 int octeon_is_simulation(void) 274 { 275 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; 276 } 277 EXPORT_SYMBOL(octeon_is_simulation); 278 279 /** 280 * Return true if Octeon is in PCI Host mode. This means 281 * Linux can control the PCI bus. 282 * 283 * Returns Non zero if Octeon in host mode. 284 */ 285 int octeon_is_pci_host(void) 286 { 287 #ifdef CONFIG_PCI 288 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; 289 #else 290 return 0; 291 #endif 292 } 293 294 /** 295 * Get the clock rate of Octeon 296 * 297 * Returns Clock rate in HZ 298 */ 299 uint64_t octeon_get_clock_rate(void) 300 { 301 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); 302 303 return sysinfo->cpu_clock_hz; 304 } 305 EXPORT_SYMBOL(octeon_get_clock_rate); 306 307 static u64 octeon_io_clock_rate; 308 309 u64 octeon_get_io_clock_rate(void) 310 { 311 return octeon_io_clock_rate; 312 } 313 EXPORT_SYMBOL(octeon_get_io_clock_rate); 314 315 316 /** 317 * Write to the LCD display connected to the bootbus. This display 318 * exists on most Cavium evaluation boards. If it doesn't exist, then 319 * this function doesn't do anything. 320 * 321 * @s: String to write 322 */ 323 void octeon_write_lcd(const char *s) 324 { 325 if (octeon_bootinfo->led_display_base_addr) { 326 void __iomem *lcd_address = 327 ioremap_nocache(octeon_bootinfo->led_display_base_addr, 328 8); 329 int i; 330 for (i = 0; i < 8; i++, s++) { 331 if (*s) 332 iowrite8(*s, lcd_address + i); 333 else 334 iowrite8(' ', lcd_address + i); 335 } 336 iounmap(lcd_address); 337 } 338 } 339 340 /** 341 * Return the console uart passed by the bootloader 342 * 343 * Returns uart (0 or 1) 344 */ 345 int octeon_get_boot_uart(void) 346 { 347 int uart; 348 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 349 uart = 1; 350 #else 351 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? 352 1 : 0; 353 #endif 354 return uart; 355 } 356 357 /** 358 * Get the coremask Linux was booted on. 359 * 360 * Returns Core mask 361 */ 362 int octeon_get_boot_coremask(void) 363 { 364 return octeon_boot_desc_ptr->core_mask; 365 } 366 367 /** 368 * Check the hardware BIST results for a CPU 369 */ 370 void octeon_check_cpu_bist(void) 371 { 372 const int coreid = cvmx_get_core_num(); 373 unsigned long long mask; 374 unsigned long long bist_val; 375 376 /* Check BIST results for COP0 registers */ 377 mask = 0x1f00000000ull; 378 bist_val = read_octeon_c0_icacheerr(); 379 if (bist_val & mask) 380 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", 381 coreid, bist_val); 382 383 bist_val = read_octeon_c0_dcacheerr(); 384 if (bist_val & 1) 385 pr_err("Core%d L1 Dcache parity error: " 386 "CacheErr(dcache) = 0x%llx\n", 387 coreid, bist_val); 388 389 mask = 0xfc00000000000000ull; 390 bist_val = read_c0_cvmmemctl(); 391 if (bist_val & mask) 392 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", 393 coreid, bist_val); 394 395 write_octeon_c0_dcacheerr(0); 396 } 397 398 /** 399 * Reboot Octeon 400 * 401 * @command: Command to pass to the bootloader. Currently ignored. 402 */ 403 static void octeon_restart(char *command) 404 { 405 /* Disable all watchdogs before soft reset. They don't get cleared */ 406 #ifdef CONFIG_SMP 407 int cpu; 408 for_each_online_cpu(cpu) 409 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 410 #else 411 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 412 #endif 413 414 mb(); 415 while (1) 416 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 417 } 418 419 420 /** 421 * Permanently stop a core. 422 * 423 * @arg: Ignored. 424 */ 425 static void octeon_kill_core(void *arg) 426 { 427 if (octeon_is_simulation()) 428 /* A break instruction causes the simulator stop a core */ 429 asm volatile ("break" ::: "memory"); 430 431 local_irq_disable(); 432 /* Disable watchdog on this core. */ 433 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 434 /* Spin in a low power mode. */ 435 while (true) 436 asm volatile ("wait" ::: "memory"); 437 } 438 439 440 /** 441 * Halt the system 442 */ 443 static void octeon_halt(void) 444 { 445 smp_call_function(octeon_kill_core, NULL, 0); 446 447 switch (octeon_bootinfo->board_type) { 448 case CVMX_BOARD_TYPE_NAO38: 449 /* Driving a 1 to GPIO 12 shuts off this board */ 450 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); 451 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); 452 break; 453 default: 454 octeon_write_lcd("PowerOff"); 455 break; 456 } 457 458 octeon_kill_core(NULL); 459 } 460 461 static char __read_mostly octeon_system_type[80]; 462 463 static int __init init_octeon_system_type(void) 464 { 465 snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)", 466 cvmx_board_type_to_string(octeon_bootinfo->board_type), 467 octeon_model_get_string(read_c0_prid())); 468 469 return 0; 470 } 471 early_initcall(init_octeon_system_type); 472 473 /** 474 * Return a string representing the system type 475 * 476 * Returns 477 */ 478 const char *octeon_board_type_string(void) 479 { 480 return octeon_system_type; 481 } 482 483 const char *get_system_type(void) 484 __attribute__ ((alias("octeon_board_type_string"))); 485 486 void octeon_user_io_init(void) 487 { 488 union octeon_cvmemctl cvmmemctl; 489 union cvmx_iob_fau_timeout fau_timeout; 490 union cvmx_pow_nw_tim nm_tim; 491 492 /* Get the current settings for CP0_CVMMEMCTL_REG */ 493 cvmmemctl.u64 = read_c0_cvmmemctl(); 494 /* R/W If set, marked write-buffer entries time out the same 495 * as as other entries; if clear, marked write-buffer entries 496 * use the maximum timeout. */ 497 cvmmemctl.s.dismarkwblongto = 1; 498 /* R/W If set, a merged store does not clear the write-buffer 499 * entry timeout state. */ 500 cvmmemctl.s.dismrgclrwbto = 0; 501 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM 502 * word location for an IOBDMA. The other 8 bits come from the 503 * SCRADDR field of the IOBDMA. */ 504 cvmmemctl.s.iobdmascrmsb = 0; 505 /* R/W If set, SYNCWS and SYNCS only order marked stores; if 506 * clear, SYNCWS and SYNCS only order unmarked 507 * stores. SYNCWSMARKED has no effect when DISSYNCWS is 508 * set. */ 509 cvmmemctl.s.syncwsmarked = 0; 510 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ 511 cvmmemctl.s.dissyncws = 0; 512 /* R/W If set, no stall happens on write buffer full. */ 513 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) 514 cvmmemctl.s.diswbfst = 1; 515 else 516 cvmmemctl.s.diswbfst = 0; 517 /* R/W If set (and SX set), supervisor-level loads/stores can 518 * use XKPHYS addresses with <48>==0 */ 519 cvmmemctl.s.xkmemenas = 0; 520 521 /* R/W If set (and UX set), user-level loads/stores can use 522 * XKPHYS addresses with VA<48>==0 */ 523 cvmmemctl.s.xkmemenau = 0; 524 525 /* R/W If set (and SX set), supervisor-level loads/stores can 526 * use XKPHYS addresses with VA<48>==1 */ 527 cvmmemctl.s.xkioenas = 0; 528 529 /* R/W If set (and UX set), user-level loads/stores can use 530 * XKPHYS addresses with VA<48>==1 */ 531 cvmmemctl.s.xkioenau = 0; 532 533 /* R/W If set, all stores act as SYNCW (NOMERGE must be set 534 * when this is set) RW, reset to 0. */ 535 cvmmemctl.s.allsyncw = 0; 536 537 /* R/W If set, no stores merge, and all stores reach the 538 * coherent bus in order. */ 539 cvmmemctl.s.nomerge = 0; 540 /* R/W Selects the bit in the counter used for DID time-outs 0 541 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is 542 * between 1x and 2x this interval. For example, with 543 * DIDTTO=3, expiration interval is between 16K and 32K. */ 544 cvmmemctl.s.didtto = 0; 545 /* R/W If set, the (mem) CSR clock never turns off. */ 546 cvmmemctl.s.csrckalwys = 0; 547 /* R/W If set, mclk never turns off. */ 548 cvmmemctl.s.mclkalwys = 0; 549 /* R/W Selects the bit in the counter used for write buffer 550 * flush time-outs (WBFLT+11) is the bit position in an 551 * internal counter used to determine expiration. The write 552 * buffer expires between 1x and 2x this interval. For 553 * example, with WBFLT = 0, a write buffer expires between 2K 554 * and 4K cycles after the write buffer entry is allocated. */ 555 cvmmemctl.s.wbfltime = 0; 556 /* R/W If set, do not put Istream in the L2 cache. */ 557 cvmmemctl.s.istrnol2 = 0; 558 559 /* 560 * R/W The write buffer threshold. As per erratum Core-14752 561 * for CN63XX, a sc/scd might fail if the write buffer is 562 * full. Lowering WBTHRESH greatly lowers the chances of the 563 * write buffer ever being full and triggering the erratum. 564 */ 565 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) 566 cvmmemctl.s.wbthresh = 4; 567 else 568 cvmmemctl.s.wbthresh = 10; 569 570 /* R/W If set, CVMSEG is available for loads/stores in 571 * kernel/debug mode. */ 572 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 573 cvmmemctl.s.cvmsegenak = 1; 574 #else 575 cvmmemctl.s.cvmsegenak = 0; 576 #endif 577 /* R/W If set, CVMSEG is available for loads/stores in 578 * supervisor mode. */ 579 cvmmemctl.s.cvmsegenas = 0; 580 /* R/W If set, CVMSEG is available for loads/stores in user 581 * mode. */ 582 cvmmemctl.s.cvmsegenau = 0; 583 584 write_c0_cvmmemctl(cvmmemctl.u64); 585 586 /* Setup of CVMSEG is done in kernel-entry-init.h */ 587 if (smp_processor_id() == 0) 588 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", 589 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, 590 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); 591 592 /* Set a default for the hardware timeouts */ 593 fau_timeout.u64 = 0; 594 fau_timeout.s.tout_val = 0xfff; 595 /* Disable tagwait FAU timeout */ 596 fau_timeout.s.tout_enb = 0; 597 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); 598 599 nm_tim.u64 = 0; 600 /* 4096 cycles */ 601 nm_tim.s.nw_tim = 3; 602 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); 603 604 write_octeon_c0_icacheerr(0); 605 write_c0_derraddr1(0); 606 } 607 608 /** 609 * Early entry point for arch setup 610 */ 611 void __init prom_init(void) 612 { 613 struct cvmx_sysinfo *sysinfo; 614 const char *arg; 615 char *p; 616 int i; 617 u64 t; 618 int argc; 619 #ifdef CONFIG_CAVIUM_RESERVE32 620 int64_t addr = -1; 621 #endif 622 /* 623 * The bootloader passes a pointer to the boot descriptor in 624 * $a3, this is available as fw_arg3. 625 */ 626 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; 627 octeon_bootinfo = 628 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); 629 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); 630 631 sysinfo = cvmx_sysinfo_get(); 632 memset(sysinfo, 0, sizeof(*sysinfo)); 633 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; 634 sysinfo->phy_mem_desc_ptr = 635 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr); 636 sysinfo->core_mask = octeon_bootinfo->core_mask; 637 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; 638 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; 639 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; 640 sysinfo->board_type = octeon_bootinfo->board_type; 641 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; 642 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; 643 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, 644 sizeof(sysinfo->mac_addr_base)); 645 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; 646 memcpy(sysinfo->board_serial_number, 647 octeon_bootinfo->board_serial_number, 648 sizeof(sysinfo->board_serial_number)); 649 sysinfo->compact_flash_common_base_addr = 650 octeon_bootinfo->compact_flash_common_base_addr; 651 sysinfo->compact_flash_attribute_base_addr = 652 octeon_bootinfo->compact_flash_attribute_base_addr; 653 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; 654 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; 655 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; 656 657 if (OCTEON_IS_OCTEON2()) { 658 /* I/O clock runs at a different rate than the CPU. */ 659 union cvmx_mio_rst_boot rst_boot; 660 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); 661 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; 662 } else if (OCTEON_IS_OCTEON3()) { 663 /* I/O clock runs at a different rate than the CPU. */ 664 union cvmx_rst_boot rst_boot; 665 rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT); 666 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; 667 } else { 668 octeon_io_clock_rate = sysinfo->cpu_clock_hz; 669 } 670 671 t = read_c0_cvmctl(); 672 if ((t & (1ull << 27)) == 0) { 673 /* 674 * Setup the multiplier save/restore code if 675 * CvmCtl[NOMUL] clear. 676 */ 677 void *save; 678 void *save_end; 679 void *restore; 680 void *restore_end; 681 int save_len; 682 int restore_len; 683 int save_max = (char *)octeon_mult_save_end - 684 (char *)octeon_mult_save; 685 int restore_max = (char *)octeon_mult_restore_end - 686 (char *)octeon_mult_restore; 687 if (current_cpu_data.cputype == CPU_CAVIUM_OCTEON3) { 688 save = octeon_mult_save3; 689 save_end = octeon_mult_save3_end; 690 restore = octeon_mult_restore3; 691 restore_end = octeon_mult_restore3_end; 692 } else { 693 save = octeon_mult_save2; 694 save_end = octeon_mult_save2_end; 695 restore = octeon_mult_restore2; 696 restore_end = octeon_mult_restore2_end; 697 } 698 save_len = (char *)save_end - (char *)save; 699 restore_len = (char *)restore_end - (char *)restore; 700 if (!WARN_ON(save_len > save_max || 701 restore_len > restore_max)) { 702 memcpy(octeon_mult_save, save, save_len); 703 memcpy(octeon_mult_restore, restore, restore_len); 704 } 705 } 706 707 /* 708 * Only enable the LED controller if we're running on a CN38XX, CN58XX, 709 * or CN56XX. The CN30XX and CN31XX don't have an LED controller. 710 */ 711 if (!octeon_is_simulation() && 712 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { 713 cvmx_write_csr(CVMX_LED_EN, 0); 714 cvmx_write_csr(CVMX_LED_PRT, 0); 715 cvmx_write_csr(CVMX_LED_DBG, 0); 716 cvmx_write_csr(CVMX_LED_PRT_FMT, 0); 717 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); 718 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); 719 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); 720 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); 721 cvmx_write_csr(CVMX_LED_EN, 1); 722 } 723 #ifdef CONFIG_CAVIUM_RESERVE32 724 /* 725 * We need to temporarily allocate all memory in the reserve32 726 * region. This makes sure the kernel doesn't allocate this 727 * memory when it is getting memory from the 728 * bootloader. Later, after the memory allocations are 729 * complete, the reserve32 will be freed. 730 * 731 * Allocate memory for RESERVED32 aligned on 2MB boundary. This 732 * is in case we later use hugetlb entries with it. 733 */ 734 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, 735 0, 0, 2 << 20, 736 "CAVIUM_RESERVE32", 0); 737 if (addr < 0) 738 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); 739 else 740 octeon_reserve32_memory = addr; 741 #endif 742 743 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 744 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { 745 pr_info("Skipping L2 locking due to reduced L2 cache size\n"); 746 } else { 747 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000; 748 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB 749 /* TLB refill */ 750 cvmx_l2c_lock_mem_region(ebase, 0x100); 751 #endif 752 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION 753 /* General exception */ 754 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); 755 #endif 756 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 757 /* Interrupt handler */ 758 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); 759 #endif 760 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT 761 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); 762 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); 763 #endif 764 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY 765 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); 766 #endif 767 } 768 #endif 769 770 octeon_check_cpu_bist(); 771 772 octeon_uart = octeon_get_boot_uart(); 773 774 #ifdef CONFIG_SMP 775 octeon_write_lcd("LinuxSMP"); 776 #else 777 octeon_write_lcd("Linux"); 778 #endif 779 780 octeon_setup_delays(); 781 782 /* 783 * BIST should always be enabled when doing a soft reset. L2 784 * Cache locking for instance is not cleared unless BIST is 785 * enabled. Unfortunately due to a chip errata G-200 for 786 * Cn38XX and CN31XX, BIST msut be disabled on these parts. 787 */ 788 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || 789 OCTEON_IS_MODEL(OCTEON_CN31XX)) 790 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); 791 else 792 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); 793 794 /* Default to 64MB in the simulator to speed things up */ 795 if (octeon_is_simulation()) 796 MAX_MEMORY = 64ull << 20; 797 798 arg = strstr(arcs_cmdline, "mem="); 799 if (arg) { 800 MAX_MEMORY = memparse(arg + 4, &p); 801 if (MAX_MEMORY == 0) 802 MAX_MEMORY = 32ull << 30; 803 if (*p == '@') 804 RESERVE_LOW_MEM = memparse(p + 1, &p); 805 } 806 807 arcs_cmdline[0] = 0; 808 argc = octeon_boot_desc_ptr->argc; 809 for (i = 0; i < argc; i++) { 810 const char *arg = 811 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); 812 if ((strncmp(arg, "MEM=", 4) == 0) || 813 (strncmp(arg, "mem=", 4) == 0)) { 814 MAX_MEMORY = memparse(arg + 4, &p); 815 if (MAX_MEMORY == 0) 816 MAX_MEMORY = 32ull << 30; 817 if (*p == '@') 818 RESERVE_LOW_MEM = memparse(p + 1, &p); 819 #ifdef CONFIG_KEXEC 820 } else if (strncmp(arg, "crashkernel=", 12) == 0) { 821 crashk_size = memparse(arg+12, &p); 822 if (*p == '@') 823 crashk_base = memparse(p+1, &p); 824 strcat(arcs_cmdline, " "); 825 strcat(arcs_cmdline, arg); 826 /* 827 * To do: switch parsing to new style, something like: 828 * parse_crashkernel(arg, sysinfo->system_dram_size, 829 * &crashk_size, &crashk_base); 830 */ 831 #endif 832 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < 833 sizeof(arcs_cmdline) - 1) { 834 strcat(arcs_cmdline, " "); 835 strcat(arcs_cmdline, arg); 836 } 837 } 838 839 if (strstr(arcs_cmdline, "console=") == NULL) { 840 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 841 strcat(arcs_cmdline, " console=ttyS0,115200"); 842 #else 843 if (octeon_uart == 1) 844 strcat(arcs_cmdline, " console=ttyS1,115200"); 845 else 846 strcat(arcs_cmdline, " console=ttyS0,115200"); 847 #endif 848 } 849 850 mips_hpt_frequency = octeon_get_clock_rate(); 851 852 octeon_init_cvmcount(); 853 854 _machine_restart = octeon_restart; 855 _machine_halt = octeon_halt; 856 857 #ifdef CONFIG_KEXEC 858 _machine_kexec_shutdown = octeon_shutdown; 859 _machine_crash_shutdown = octeon_crash_shutdown; 860 _machine_kexec_prepare = octeon_kexec_prepare; 861 #endif 862 863 octeon_user_io_init(); 864 register_smp_ops(&octeon_smp_ops); 865 } 866 867 /* Exclude a single page from the regions obtained in plat_mem_setup. */ 868 #ifndef CONFIG_CRASH_DUMP 869 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) 870 { 871 if (addr > *mem && addr < *mem + *size) { 872 u64 inc = addr - *mem; 873 add_memory_region(*mem, inc, BOOT_MEM_RAM); 874 *mem += inc; 875 *size -= inc; 876 } 877 878 if (addr == *mem && *size > PAGE_SIZE) { 879 *mem += PAGE_SIZE; 880 *size -= PAGE_SIZE; 881 } 882 } 883 #endif /* CONFIG_CRASH_DUMP */ 884 885 void __init plat_mem_setup(void) 886 { 887 uint64_t mem_alloc_size; 888 uint64_t total; 889 uint64_t crashk_end; 890 #ifndef CONFIG_CRASH_DUMP 891 int64_t memory; 892 uint64_t kernel_start; 893 uint64_t kernel_size; 894 #endif 895 896 total = 0; 897 crashk_end = 0; 898 899 /* 900 * The Mips memory init uses the first memory location for 901 * some memory vectors. When SPARSEMEM is in use, it doesn't 902 * verify that the size is big enough for the final 903 * vectors. Making the smallest chuck 4MB seems to be enough 904 * to consistently work. 905 */ 906 mem_alloc_size = 4 << 20; 907 if (mem_alloc_size > MAX_MEMORY) 908 mem_alloc_size = MAX_MEMORY; 909 910 /* Crashkernel ignores bootmem list. It relies on mem=X@Y option */ 911 #ifdef CONFIG_CRASH_DUMP 912 add_memory_region(RESERVE_LOW_MEM, MAX_MEMORY, BOOT_MEM_RAM); 913 total += MAX_MEMORY; 914 #else 915 #ifdef CONFIG_KEXEC 916 if (crashk_size > 0) { 917 add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM); 918 crashk_end = crashk_base + crashk_size; 919 } 920 #endif 921 /* 922 * When allocating memory, we want incrementing addresses from 923 * bootmem_alloc so the code in add_memory_region can merge 924 * regions next to each other. 925 */ 926 cvmx_bootmem_lock(); 927 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) 928 && (total < MAX_MEMORY)) { 929 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 930 __pa_symbol(&__init_end), -1, 931 0x100000, 932 CVMX_BOOTMEM_FLAG_NO_LOCKING); 933 if (memory >= 0) { 934 u64 size = mem_alloc_size; 935 #ifdef CONFIG_KEXEC 936 uint64_t end; 937 #endif 938 939 /* 940 * exclude a page at the beginning and end of 941 * the 256MB PCIe 'hole' so the kernel will not 942 * try to allocate multi-page buffers that 943 * span the discontinuity. 944 */ 945 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE, 946 &memory, &size); 947 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE + 948 CVMX_PCIE_BAR1_PHYS_SIZE, 949 &memory, &size); 950 #ifdef CONFIG_KEXEC 951 end = memory + mem_alloc_size; 952 953 /* 954 * This function automatically merges address regions 955 * next to each other if they are received in 956 * incrementing order 957 */ 958 if (memory < crashk_base && end > crashk_end) { 959 /* region is fully in */ 960 add_memory_region(memory, 961 crashk_base - memory, 962 BOOT_MEM_RAM); 963 total += crashk_base - memory; 964 add_memory_region(crashk_end, 965 end - crashk_end, 966 BOOT_MEM_RAM); 967 total += end - crashk_end; 968 continue; 969 } 970 971 if (memory >= crashk_base && end <= crashk_end) 972 /* 973 * Entire memory region is within the new 974 * kernel's memory, ignore it. 975 */ 976 continue; 977 978 if (memory > crashk_base && memory < crashk_end && 979 end > crashk_end) { 980 /* 981 * Overlap with the beginning of the region, 982 * reserve the beginning. 983 */ 984 mem_alloc_size -= crashk_end - memory; 985 memory = crashk_end; 986 } else if (memory < crashk_base && end > crashk_base && 987 end < crashk_end) 988 /* 989 * Overlap with the beginning of the region, 990 * chop of end. 991 */ 992 mem_alloc_size -= end - crashk_base; 993 #endif 994 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); 995 total += mem_alloc_size; 996 /* Recovering mem_alloc_size */ 997 mem_alloc_size = 4 << 20; 998 } else { 999 break; 1000 } 1001 } 1002 cvmx_bootmem_unlock(); 1003 /* Add the memory region for the kernel. */ 1004 kernel_start = (unsigned long) _text; 1005 kernel_size = _end - _text; 1006 1007 /* Adjust for physical offset. */ 1008 kernel_start &= ~0xffffffff80000000ULL; 1009 add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM); 1010 #endif /* CONFIG_CRASH_DUMP */ 1011 1012 #ifdef CONFIG_CAVIUM_RESERVE32 1013 /* 1014 * Now that we've allocated the kernel memory it is safe to 1015 * free the reserved region. We free it here so that builtin 1016 * drivers can use the memory. 1017 */ 1018 if (octeon_reserve32_memory) 1019 cvmx_bootmem_free_named("CAVIUM_RESERVE32"); 1020 #endif /* CONFIG_CAVIUM_RESERVE32 */ 1021 1022 if (total == 0) 1023 panic("Unable to allocate memory from " 1024 "cvmx_bootmem_phy_alloc"); 1025 } 1026 1027 /* 1028 * Emit one character to the boot UART. Exported for use by the 1029 * watchdog timer. 1030 */ 1031 int prom_putchar(char c) 1032 { 1033 uint64_t lsrval; 1034 1035 /* Spin until there is room */ 1036 do { 1037 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); 1038 } while ((lsrval & 0x20) == 0); 1039 1040 /* Write the byte */ 1041 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); 1042 return 1; 1043 } 1044 EXPORT_SYMBOL(prom_putchar); 1045 1046 void prom_free_prom_memory(void) 1047 { 1048 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) { 1049 /* Check for presence of Core-14449 fix. */ 1050 u32 insn; 1051 u32 *foo; 1052 1053 foo = &insn; 1054 1055 asm volatile("# before" : : : "memory"); 1056 prefetch(foo); 1057 asm volatile( 1058 ".set push\n\t" 1059 ".set noreorder\n\t" 1060 "bal 1f\n\t" 1061 "nop\n" 1062 "1:\tlw %0,-12($31)\n\t" 1063 ".set pop\n\t" 1064 : "=r" (insn) : : "$31", "memory"); 1065 1066 if ((insn >> 26) != 0x33) 1067 panic("No PREF instruction at Core-14449 probe point."); 1068 1069 if (((insn >> 16) & 0x1f) != 28) 1070 panic("OCTEON II DCache prefetch workaround not in place (%04x).\n" 1071 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", 1072 insn); 1073 } 1074 } 1075 1076 int octeon_prune_device_tree(void); 1077 1078 extern const char __dtb_octeon_3xxx_begin; 1079 extern const char __dtb_octeon_68xx_begin; 1080 void __init device_tree_init(void) 1081 { 1082 const void *fdt; 1083 bool do_prune; 1084 1085 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { 1086 fdt = phys_to_virt(octeon_bootinfo->fdt_addr); 1087 if (fdt_check_header(fdt)) 1088 panic("Corrupt Device Tree passed to kernel."); 1089 do_prune = false; 1090 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { 1091 fdt = &__dtb_octeon_68xx_begin; 1092 do_prune = true; 1093 } else { 1094 fdt = &__dtb_octeon_3xxx_begin; 1095 do_prune = true; 1096 } 1097 1098 initial_boot_params = (void *)fdt; 1099 1100 if (do_prune) { 1101 octeon_prune_device_tree(); 1102 pr_info("Using internal Device Tree.\n"); 1103 } else { 1104 pr_info("Using passed Device Tree.\n"); 1105 } 1106 unflatten_and_copy_device_tree(); 1107 } 1108 1109 static int __initdata disable_octeon_edac_p; 1110 1111 static int __init disable_octeon_edac(char *str) 1112 { 1113 disable_octeon_edac_p = 1; 1114 return 0; 1115 } 1116 early_param("disable_octeon_edac", disable_octeon_edac); 1117 1118 static char *edac_device_names[] = { 1119 "octeon_l2c_edac", 1120 "octeon_pc_edac", 1121 }; 1122 1123 static int __init edac_devinit(void) 1124 { 1125 struct platform_device *dev; 1126 int i, err = 0; 1127 int num_lmc; 1128 char *name; 1129 1130 if (disable_octeon_edac_p) 1131 return 0; 1132 1133 for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) { 1134 name = edac_device_names[i]; 1135 dev = platform_device_register_simple(name, -1, NULL, 0); 1136 if (IS_ERR(dev)) { 1137 pr_err("Registration of %s failed!\n", name); 1138 err = PTR_ERR(dev); 1139 } 1140 } 1141 1142 num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 : 1143 (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1); 1144 for (i = 0; i < num_lmc; i++) { 1145 dev = platform_device_register_simple("octeon_lmc_edac", 1146 i, NULL, 0); 1147 if (IS_ERR(dev)) { 1148 pr_err("Registration of octeon_lmc_edac %d failed!\n", i); 1149 err = PTR_ERR(dev); 1150 } 1151 } 1152 1153 return err; 1154 } 1155 device_initcall(edac_devinit); 1156 1157 static void __initdata *octeon_dummy_iospace; 1158 1159 static int __init octeon_no_pci_init(void) 1160 { 1161 /* 1162 * Initially assume there is no PCI. The PCI/PCIe platform code will 1163 * later re-initialize these to correct values if they are present. 1164 */ 1165 octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT); 1166 set_io_port_base((unsigned long)octeon_dummy_iospace); 1167 ioport_resource.start = MAX_RESOURCE; 1168 ioport_resource.end = 0; 1169 return 0; 1170 } 1171 core_initcall(octeon_no_pci_init); 1172 1173 static int __init octeon_no_pci_release(void) 1174 { 1175 /* 1176 * Release the allocated memory if a real IO space is there. 1177 */ 1178 if ((unsigned long)octeon_dummy_iospace != mips_io_port_base) 1179 vfree(octeon_dummy_iospace); 1180 return 0; 1181 } 1182 late_initcall(octeon_no_pci_release); 1183