1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2007 Cavium Networks 7 * Copyright (C) 2008, 2009 Wind River Systems 8 * written by Ralf Baechle <ralf@linux-mips.org> 9 */ 10 #include <linux/compiler.h> 11 #include <linux/vmalloc.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/console.h> 15 #include <linux/delay.h> 16 #include <linux/export.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/serial.h> 20 #include <linux/smp.h> 21 #include <linux/types.h> 22 #include <linux/string.h> /* for memset */ 23 #include <linux/tty.h> 24 #include <linux/time.h> 25 #include <linux/platform_device.h> 26 #include <linux/serial_core.h> 27 #include <linux/serial_8250.h> 28 #include <linux/of_fdt.h> 29 #include <linux/libfdt.h> 30 #include <linux/kexec.h> 31 32 #include <asm/processor.h> 33 #include <asm/reboot.h> 34 #include <asm/smp-ops.h> 35 #include <asm/irq_cpu.h> 36 #include <asm/mipsregs.h> 37 #include <asm/bootinfo.h> 38 #include <asm/sections.h> 39 #include <asm/time.h> 40 41 #include <asm/octeon/octeon.h> 42 #include <asm/octeon/pci-octeon.h> 43 #include <asm/octeon/cvmx-mio-defs.h> 44 45 extern struct plat_smp_ops octeon_smp_ops; 46 47 #ifdef CONFIG_PCI 48 extern void pci_console_init(const char *arg); 49 #endif 50 51 static unsigned long long MAX_MEMORY = 512ull << 20; 52 53 struct octeon_boot_descriptor *octeon_boot_desc_ptr; 54 55 struct cvmx_bootinfo *octeon_bootinfo; 56 EXPORT_SYMBOL(octeon_bootinfo); 57 58 static unsigned long long RESERVE_LOW_MEM = 0ull; 59 #ifdef CONFIG_KEXEC 60 #ifdef CONFIG_SMP 61 /* 62 * Wait for relocation code is prepared and send 63 * secondary CPUs to spin until kernel is relocated. 64 */ 65 static void octeon_kexec_smp_down(void *ignored) 66 { 67 int cpu = smp_processor_id(); 68 69 local_irq_disable(); 70 set_cpu_online(cpu, false); 71 while (!atomic_read(&kexec_ready_to_reboot)) 72 cpu_relax(); 73 74 asm volatile ( 75 " sync \n" 76 " synci ($0) \n"); 77 78 relocated_kexec_smp_wait(NULL); 79 } 80 #endif 81 82 #define OCTEON_DDR0_BASE (0x0ULL) 83 #define OCTEON_DDR0_SIZE (0x010000000ULL) 84 #define OCTEON_DDR1_BASE (0x410000000ULL) 85 #define OCTEON_DDR1_SIZE (0x010000000ULL) 86 #define OCTEON_DDR2_BASE (0x020000000ULL) 87 #define OCTEON_DDR2_SIZE (0x3e0000000ULL) 88 #define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL) 89 90 static struct kimage *kimage_ptr; 91 92 static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes) 93 { 94 int64_t addr; 95 struct cvmx_bootmem_desc *bootmem_desc; 96 97 bootmem_desc = cvmx_bootmem_get_desc(); 98 99 if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) { 100 mem_size = OCTEON_MAX_PHY_MEM_SIZE; 101 pr_err("Error: requested memory too large," 102 "truncating to maximum size\n"); 103 } 104 105 bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER; 106 bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER; 107 108 addr = (OCTEON_DDR0_BASE + RESERVE_LOW_MEM + low_reserved_bytes); 109 bootmem_desc->head_addr = 0; 110 111 if (mem_size <= OCTEON_DDR0_SIZE) { 112 __cvmx_bootmem_phy_free(addr, 113 mem_size - RESERVE_LOW_MEM - 114 low_reserved_bytes, 0); 115 return; 116 } 117 118 __cvmx_bootmem_phy_free(addr, 119 OCTEON_DDR0_SIZE - RESERVE_LOW_MEM - 120 low_reserved_bytes, 0); 121 122 mem_size -= OCTEON_DDR0_SIZE; 123 124 if (mem_size > OCTEON_DDR1_SIZE) { 125 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0); 126 __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE, 127 mem_size - OCTEON_DDR1_SIZE, 0); 128 } else 129 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0); 130 } 131 132 static int octeon_kexec_prepare(struct kimage *image) 133 { 134 int i; 135 char *bootloader = "kexec"; 136 137 octeon_boot_desc_ptr->argc = 0; 138 for (i = 0; i < image->nr_segments; i++) { 139 if (!strncmp(bootloader, (char *)image->segment[i].buf, 140 strlen(bootloader))) { 141 /* 142 * convert command line string to array 143 * of parameters (as bootloader does). 144 */ 145 int argc = 0, offt; 146 char *str = (char *)image->segment[i].buf; 147 char *ptr = strchr(str, ' '); 148 while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) { 149 *ptr = '\0'; 150 if (ptr[1] != ' ') { 151 offt = (int)(ptr - str + 1); 152 octeon_boot_desc_ptr->argv[argc] = 153 image->segment[i].mem + offt; 154 argc++; 155 } 156 ptr = strchr(ptr + 1, ' '); 157 } 158 octeon_boot_desc_ptr->argc = argc; 159 break; 160 } 161 } 162 163 /* 164 * Information about segments will be needed during pre-boot memory 165 * initialization. 166 */ 167 kimage_ptr = image; 168 return 0; 169 } 170 171 static void octeon_generic_shutdown(void) 172 { 173 int i; 174 #ifdef CONFIG_SMP 175 int cpu; 176 #endif 177 struct cvmx_bootmem_desc *bootmem_desc; 178 void *named_block_array_ptr; 179 180 bootmem_desc = cvmx_bootmem_get_desc(); 181 named_block_array_ptr = 182 cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr); 183 184 #ifdef CONFIG_SMP 185 /* disable watchdogs */ 186 for_each_online_cpu(cpu) 187 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 188 #else 189 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 190 #endif 191 if (kimage_ptr != kexec_crash_image) { 192 memset(named_block_array_ptr, 193 0x0, 194 CVMX_BOOTMEM_NUM_NAMED_BLOCKS * 195 sizeof(struct cvmx_bootmem_named_block_desc)); 196 /* 197 * Mark all memory (except low 0x100000 bytes) as free. 198 * It is the same thing that bootloader does. 199 */ 200 kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL, 201 0x100000); 202 /* 203 * Allocate all segments to avoid their corruption during boot. 204 */ 205 for (i = 0; i < kimage_ptr->nr_segments; i++) 206 cvmx_bootmem_alloc_address( 207 kimage_ptr->segment[i].memsz + 2*PAGE_SIZE, 208 kimage_ptr->segment[i].mem - PAGE_SIZE, 209 PAGE_SIZE); 210 } else { 211 /* 212 * Do not mark all memory as free. Free only named sections 213 * leaving the rest of memory unchanged. 214 */ 215 struct cvmx_bootmem_named_block_desc *ptr = 216 (struct cvmx_bootmem_named_block_desc *) 217 named_block_array_ptr; 218 219 for (i = 0; i < bootmem_desc->named_block_num_blocks; i++) 220 if (ptr[i].size) 221 cvmx_bootmem_free_named(ptr[i].name); 222 } 223 kexec_args[2] = 1UL; /* running on octeon_main_processor */ 224 kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; 225 #ifdef CONFIG_SMP 226 secondary_kexec_args[2] = 0UL; /* running on secondary cpu */ 227 secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; 228 #endif 229 } 230 231 static void octeon_shutdown(void) 232 { 233 octeon_generic_shutdown(); 234 #ifdef CONFIG_SMP 235 smp_call_function(octeon_kexec_smp_down, NULL, 0); 236 smp_wmb(); 237 while (num_online_cpus() > 1) { 238 cpu_relax(); 239 mdelay(1); 240 } 241 #endif 242 } 243 244 static void octeon_crash_shutdown(struct pt_regs *regs) 245 { 246 octeon_generic_shutdown(); 247 default_machine_crash_shutdown(regs); 248 } 249 250 #endif /* CONFIG_KEXEC */ 251 252 #ifdef CONFIG_CAVIUM_RESERVE32 253 uint64_t octeon_reserve32_memory; 254 EXPORT_SYMBOL(octeon_reserve32_memory); 255 #endif 256 257 #ifdef CONFIG_KEXEC 258 /* crashkernel cmdline parameter is parsed _after_ memory setup 259 * we also parse it here (workaround for EHB5200) */ 260 static uint64_t crashk_size, crashk_base; 261 #endif 262 263 static int octeon_uart; 264 265 extern asmlinkage void handle_int(void); 266 extern asmlinkage void plat_irq_dispatch(void); 267 268 /** 269 * Return non zero if we are currently running in the Octeon simulator 270 * 271 * Returns 272 */ 273 int octeon_is_simulation(void) 274 { 275 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; 276 } 277 EXPORT_SYMBOL(octeon_is_simulation); 278 279 /** 280 * Return true if Octeon is in PCI Host mode. This means 281 * Linux can control the PCI bus. 282 * 283 * Returns Non zero if Octeon in host mode. 284 */ 285 int octeon_is_pci_host(void) 286 { 287 #ifdef CONFIG_PCI 288 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; 289 #else 290 return 0; 291 #endif 292 } 293 294 /** 295 * Get the clock rate of Octeon 296 * 297 * Returns Clock rate in HZ 298 */ 299 uint64_t octeon_get_clock_rate(void) 300 { 301 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); 302 303 return sysinfo->cpu_clock_hz; 304 } 305 EXPORT_SYMBOL(octeon_get_clock_rate); 306 307 static u64 octeon_io_clock_rate; 308 309 u64 octeon_get_io_clock_rate(void) 310 { 311 return octeon_io_clock_rate; 312 } 313 EXPORT_SYMBOL(octeon_get_io_clock_rate); 314 315 316 /** 317 * Write to the LCD display connected to the bootbus. This display 318 * exists on most Cavium evaluation boards. If it doesn't exist, then 319 * this function doesn't do anything. 320 * 321 * @s: String to write 322 */ 323 void octeon_write_lcd(const char *s) 324 { 325 if (octeon_bootinfo->led_display_base_addr) { 326 void __iomem *lcd_address = 327 ioremap_nocache(octeon_bootinfo->led_display_base_addr, 328 8); 329 int i; 330 for (i = 0; i < 8; i++, s++) { 331 if (*s) 332 iowrite8(*s, lcd_address + i); 333 else 334 iowrite8(' ', lcd_address + i); 335 } 336 iounmap(lcd_address); 337 } 338 } 339 340 /** 341 * Return the console uart passed by the bootloader 342 * 343 * Returns uart (0 or 1) 344 */ 345 int octeon_get_boot_uart(void) 346 { 347 int uart; 348 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 349 uart = 1; 350 #else 351 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? 352 1 : 0; 353 #endif 354 return uart; 355 } 356 357 /** 358 * Get the coremask Linux was booted on. 359 * 360 * Returns Core mask 361 */ 362 int octeon_get_boot_coremask(void) 363 { 364 return octeon_boot_desc_ptr->core_mask; 365 } 366 367 /** 368 * Check the hardware BIST results for a CPU 369 */ 370 void octeon_check_cpu_bist(void) 371 { 372 const int coreid = cvmx_get_core_num(); 373 unsigned long long mask; 374 unsigned long long bist_val; 375 376 /* Check BIST results for COP0 registers */ 377 mask = 0x1f00000000ull; 378 bist_val = read_octeon_c0_icacheerr(); 379 if (bist_val & mask) 380 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", 381 coreid, bist_val); 382 383 bist_val = read_octeon_c0_dcacheerr(); 384 if (bist_val & 1) 385 pr_err("Core%d L1 Dcache parity error: " 386 "CacheErr(dcache) = 0x%llx\n", 387 coreid, bist_val); 388 389 mask = 0xfc00000000000000ull; 390 bist_val = read_c0_cvmmemctl(); 391 if (bist_val & mask) 392 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", 393 coreid, bist_val); 394 395 write_octeon_c0_dcacheerr(0); 396 } 397 398 /** 399 * Reboot Octeon 400 * 401 * @command: Command to pass to the bootloader. Currently ignored. 402 */ 403 static void octeon_restart(char *command) 404 { 405 /* Disable all watchdogs before soft reset. They don't get cleared */ 406 #ifdef CONFIG_SMP 407 int cpu; 408 for_each_online_cpu(cpu) 409 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 410 #else 411 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 412 #endif 413 414 mb(); 415 while (1) 416 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 417 } 418 419 420 /** 421 * Permanently stop a core. 422 * 423 * @arg: Ignored. 424 */ 425 static void octeon_kill_core(void *arg) 426 { 427 if (octeon_is_simulation()) 428 /* A break instruction causes the simulator stop a core */ 429 asm volatile ("break" ::: "memory"); 430 431 local_irq_disable(); 432 /* Disable watchdog on this core. */ 433 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 434 /* Spin in a low power mode. */ 435 while (true) 436 asm volatile ("wait" ::: "memory"); 437 } 438 439 440 /** 441 * Halt the system 442 */ 443 static void octeon_halt(void) 444 { 445 smp_call_function(octeon_kill_core, NULL, 0); 446 447 switch (octeon_bootinfo->board_type) { 448 case CVMX_BOARD_TYPE_NAO38: 449 /* Driving a 1 to GPIO 12 shuts off this board */ 450 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); 451 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); 452 break; 453 default: 454 octeon_write_lcd("PowerOff"); 455 break; 456 } 457 458 octeon_kill_core(NULL); 459 } 460 461 /** 462 * Return a string representing the system type 463 * 464 * Returns 465 */ 466 const char *octeon_board_type_string(void) 467 { 468 static char name[80]; 469 sprintf(name, "%s (%s)", 470 cvmx_board_type_to_string(octeon_bootinfo->board_type), 471 octeon_model_get_string(read_c0_prid())); 472 return name; 473 } 474 475 const char *get_system_type(void) 476 __attribute__ ((alias("octeon_board_type_string"))); 477 478 void octeon_user_io_init(void) 479 { 480 union octeon_cvmemctl cvmmemctl; 481 union cvmx_iob_fau_timeout fau_timeout; 482 union cvmx_pow_nw_tim nm_tim; 483 484 /* Get the current settings for CP0_CVMMEMCTL_REG */ 485 cvmmemctl.u64 = read_c0_cvmmemctl(); 486 /* R/W If set, marked write-buffer entries time out the same 487 * as as other entries; if clear, marked write-buffer entries 488 * use the maximum timeout. */ 489 cvmmemctl.s.dismarkwblongto = 1; 490 /* R/W If set, a merged store does not clear the write-buffer 491 * entry timeout state. */ 492 cvmmemctl.s.dismrgclrwbto = 0; 493 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM 494 * word location for an IOBDMA. The other 8 bits come from the 495 * SCRADDR field of the IOBDMA. */ 496 cvmmemctl.s.iobdmascrmsb = 0; 497 /* R/W If set, SYNCWS and SYNCS only order marked stores; if 498 * clear, SYNCWS and SYNCS only order unmarked 499 * stores. SYNCWSMARKED has no effect when DISSYNCWS is 500 * set. */ 501 cvmmemctl.s.syncwsmarked = 0; 502 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ 503 cvmmemctl.s.dissyncws = 0; 504 /* R/W If set, no stall happens on write buffer full. */ 505 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) 506 cvmmemctl.s.diswbfst = 1; 507 else 508 cvmmemctl.s.diswbfst = 0; 509 /* R/W If set (and SX set), supervisor-level loads/stores can 510 * use XKPHYS addresses with <48>==0 */ 511 cvmmemctl.s.xkmemenas = 0; 512 513 /* R/W If set (and UX set), user-level loads/stores can use 514 * XKPHYS addresses with VA<48>==0 */ 515 cvmmemctl.s.xkmemenau = 0; 516 517 /* R/W If set (and SX set), supervisor-level loads/stores can 518 * use XKPHYS addresses with VA<48>==1 */ 519 cvmmemctl.s.xkioenas = 0; 520 521 /* R/W If set (and UX set), user-level loads/stores can use 522 * XKPHYS addresses with VA<48>==1 */ 523 cvmmemctl.s.xkioenau = 0; 524 525 /* R/W If set, all stores act as SYNCW (NOMERGE must be set 526 * when this is set) RW, reset to 0. */ 527 cvmmemctl.s.allsyncw = 0; 528 529 /* R/W If set, no stores merge, and all stores reach the 530 * coherent bus in order. */ 531 cvmmemctl.s.nomerge = 0; 532 /* R/W Selects the bit in the counter used for DID time-outs 0 533 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is 534 * between 1x and 2x this interval. For example, with 535 * DIDTTO=3, expiration interval is between 16K and 32K. */ 536 cvmmemctl.s.didtto = 0; 537 /* R/W If set, the (mem) CSR clock never turns off. */ 538 cvmmemctl.s.csrckalwys = 0; 539 /* R/W If set, mclk never turns off. */ 540 cvmmemctl.s.mclkalwys = 0; 541 /* R/W Selects the bit in the counter used for write buffer 542 * flush time-outs (WBFLT+11) is the bit position in an 543 * internal counter used to determine expiration. The write 544 * buffer expires between 1x and 2x this interval. For 545 * example, with WBFLT = 0, a write buffer expires between 2K 546 * and 4K cycles after the write buffer entry is allocated. */ 547 cvmmemctl.s.wbfltime = 0; 548 /* R/W If set, do not put Istream in the L2 cache. */ 549 cvmmemctl.s.istrnol2 = 0; 550 551 /* 552 * R/W The write buffer threshold. As per erratum Core-14752 553 * for CN63XX, a sc/scd might fail if the write buffer is 554 * full. Lowering WBTHRESH greatly lowers the chances of the 555 * write buffer ever being full and triggering the erratum. 556 */ 557 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) 558 cvmmemctl.s.wbthresh = 4; 559 else 560 cvmmemctl.s.wbthresh = 10; 561 562 /* R/W If set, CVMSEG is available for loads/stores in 563 * kernel/debug mode. */ 564 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 565 cvmmemctl.s.cvmsegenak = 1; 566 #else 567 cvmmemctl.s.cvmsegenak = 0; 568 #endif 569 /* R/W If set, CVMSEG is available for loads/stores in 570 * supervisor mode. */ 571 cvmmemctl.s.cvmsegenas = 0; 572 /* R/W If set, CVMSEG is available for loads/stores in user 573 * mode. */ 574 cvmmemctl.s.cvmsegenau = 0; 575 /* R/W Size of local memory in cache blocks, 54 (6912 bytes) 576 * is max legal value. */ 577 cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE; 578 579 write_c0_cvmmemctl(cvmmemctl.u64); 580 581 if (smp_processor_id() == 0) 582 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", 583 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, 584 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); 585 586 /* Set a default for the hardware timeouts */ 587 fau_timeout.u64 = 0; 588 fau_timeout.s.tout_val = 0xfff; 589 /* Disable tagwait FAU timeout */ 590 fau_timeout.s.tout_enb = 0; 591 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); 592 593 nm_tim.u64 = 0; 594 /* 4096 cycles */ 595 nm_tim.s.nw_tim = 3; 596 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); 597 598 write_octeon_c0_icacheerr(0); 599 write_c0_derraddr1(0); 600 } 601 602 /** 603 * Early entry point for arch setup 604 */ 605 void __init prom_init(void) 606 { 607 struct cvmx_sysinfo *sysinfo; 608 const char *arg; 609 char *p; 610 int i; 611 int argc; 612 #ifdef CONFIG_CAVIUM_RESERVE32 613 int64_t addr = -1; 614 #endif 615 /* 616 * The bootloader passes a pointer to the boot descriptor in 617 * $a3, this is available as fw_arg3. 618 */ 619 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; 620 octeon_bootinfo = 621 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); 622 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); 623 624 sysinfo = cvmx_sysinfo_get(); 625 memset(sysinfo, 0, sizeof(*sysinfo)); 626 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; 627 sysinfo->phy_mem_desc_ptr = 628 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr); 629 sysinfo->core_mask = octeon_bootinfo->core_mask; 630 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; 631 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; 632 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; 633 sysinfo->board_type = octeon_bootinfo->board_type; 634 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; 635 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; 636 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, 637 sizeof(sysinfo->mac_addr_base)); 638 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; 639 memcpy(sysinfo->board_serial_number, 640 octeon_bootinfo->board_serial_number, 641 sizeof(sysinfo->board_serial_number)); 642 sysinfo->compact_flash_common_base_addr = 643 octeon_bootinfo->compact_flash_common_base_addr; 644 sysinfo->compact_flash_attribute_base_addr = 645 octeon_bootinfo->compact_flash_attribute_base_addr; 646 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; 647 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; 648 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; 649 650 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { 651 /* I/O clock runs at a different rate than the CPU. */ 652 union cvmx_mio_rst_boot rst_boot; 653 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); 654 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; 655 } else { 656 octeon_io_clock_rate = sysinfo->cpu_clock_hz; 657 } 658 659 /* 660 * Only enable the LED controller if we're running on a CN38XX, CN58XX, 661 * or CN56XX. The CN30XX and CN31XX don't have an LED controller. 662 */ 663 if (!octeon_is_simulation() && 664 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { 665 cvmx_write_csr(CVMX_LED_EN, 0); 666 cvmx_write_csr(CVMX_LED_PRT, 0); 667 cvmx_write_csr(CVMX_LED_DBG, 0); 668 cvmx_write_csr(CVMX_LED_PRT_FMT, 0); 669 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); 670 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); 671 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); 672 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); 673 cvmx_write_csr(CVMX_LED_EN, 1); 674 } 675 #ifdef CONFIG_CAVIUM_RESERVE32 676 /* 677 * We need to temporarily allocate all memory in the reserve32 678 * region. This makes sure the kernel doesn't allocate this 679 * memory when it is getting memory from the 680 * bootloader. Later, after the memory allocations are 681 * complete, the reserve32 will be freed. 682 * 683 * Allocate memory for RESERVED32 aligned on 2MB boundary. This 684 * is in case we later use hugetlb entries with it. 685 */ 686 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, 687 0, 0, 2 << 20, 688 "CAVIUM_RESERVE32", 0); 689 if (addr < 0) 690 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); 691 else 692 octeon_reserve32_memory = addr; 693 #endif 694 695 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 696 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { 697 pr_info("Skipping L2 locking due to reduced L2 cache size\n"); 698 } else { 699 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000; 700 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB 701 /* TLB refill */ 702 cvmx_l2c_lock_mem_region(ebase, 0x100); 703 #endif 704 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION 705 /* General exception */ 706 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); 707 #endif 708 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 709 /* Interrupt handler */ 710 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); 711 #endif 712 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT 713 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); 714 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); 715 #endif 716 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY 717 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); 718 #endif 719 } 720 #endif 721 722 octeon_check_cpu_bist(); 723 724 octeon_uart = octeon_get_boot_uart(); 725 726 #ifdef CONFIG_SMP 727 octeon_write_lcd("LinuxSMP"); 728 #else 729 octeon_write_lcd("Linux"); 730 #endif 731 732 #ifdef CONFIG_CAVIUM_GDB 733 /* 734 * When debugging the linux kernel, force the cores to enter 735 * the debug exception handler to break in. 736 */ 737 if (octeon_get_boot_debug_flag()) { 738 cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num()); 739 cvmx_read_csr(CVMX_CIU_DINT); 740 } 741 #endif 742 743 octeon_setup_delays(); 744 745 /* 746 * BIST should always be enabled when doing a soft reset. L2 747 * Cache locking for instance is not cleared unless BIST is 748 * enabled. Unfortunately due to a chip errata G-200 for 749 * Cn38XX and CN31XX, BIST msut be disabled on these parts. 750 */ 751 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || 752 OCTEON_IS_MODEL(OCTEON_CN31XX)) 753 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); 754 else 755 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); 756 757 /* Default to 64MB in the simulator to speed things up */ 758 if (octeon_is_simulation()) 759 MAX_MEMORY = 64ull << 20; 760 761 arg = strstr(arcs_cmdline, "mem="); 762 if (arg) { 763 MAX_MEMORY = memparse(arg + 4, &p); 764 if (MAX_MEMORY == 0) 765 MAX_MEMORY = 32ull << 30; 766 if (*p == '@') 767 RESERVE_LOW_MEM = memparse(p + 1, &p); 768 } 769 770 arcs_cmdline[0] = 0; 771 argc = octeon_boot_desc_ptr->argc; 772 for (i = 0; i < argc; i++) { 773 const char *arg = 774 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); 775 if ((strncmp(arg, "MEM=", 4) == 0) || 776 (strncmp(arg, "mem=", 4) == 0)) { 777 MAX_MEMORY = memparse(arg + 4, &p); 778 if (MAX_MEMORY == 0) 779 MAX_MEMORY = 32ull << 30; 780 if (*p == '@') 781 RESERVE_LOW_MEM = memparse(p + 1, &p); 782 } else if (strcmp(arg, "ecc_verbose") == 0) { 783 #ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC 784 __cvmx_interrupt_ecc_report_single_bit_errors = 1; 785 pr_notice("Reporting of single bit ECC errors is " 786 "turned on\n"); 787 #endif 788 #ifdef CONFIG_KEXEC 789 } else if (strncmp(arg, "crashkernel=", 12) == 0) { 790 crashk_size = memparse(arg+12, &p); 791 if (*p == '@') 792 crashk_base = memparse(p+1, &p); 793 strcat(arcs_cmdline, " "); 794 strcat(arcs_cmdline, arg); 795 /* 796 * To do: switch parsing to new style, something like: 797 * parse_crashkernel(arg, sysinfo->system_dram_size, 798 * &crashk_size, &crashk_base); 799 */ 800 #endif 801 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < 802 sizeof(arcs_cmdline) - 1) { 803 strcat(arcs_cmdline, " "); 804 strcat(arcs_cmdline, arg); 805 } 806 } 807 808 if (strstr(arcs_cmdline, "console=") == NULL) { 809 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 810 strcat(arcs_cmdline, " console=ttyS0,115200"); 811 #else 812 if (octeon_uart == 1) 813 strcat(arcs_cmdline, " console=ttyS1,115200"); 814 else 815 strcat(arcs_cmdline, " console=ttyS0,115200"); 816 #endif 817 } 818 819 if (octeon_is_simulation()) { 820 /* 821 * The simulator uses a mtdram device pre filled with 822 * the filesystem. Also specify the calibration delay 823 * to avoid calculating it every time. 824 */ 825 strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824"); 826 } 827 828 mips_hpt_frequency = octeon_get_clock_rate(); 829 830 octeon_init_cvmcount(); 831 832 _machine_restart = octeon_restart; 833 _machine_halt = octeon_halt; 834 835 #ifdef CONFIG_KEXEC 836 _machine_kexec_shutdown = octeon_shutdown; 837 _machine_crash_shutdown = octeon_crash_shutdown; 838 _machine_kexec_prepare = octeon_kexec_prepare; 839 #endif 840 841 octeon_user_io_init(); 842 register_smp_ops(&octeon_smp_ops); 843 } 844 845 /* Exclude a single page from the regions obtained in plat_mem_setup. */ 846 #ifndef CONFIG_CRASH_DUMP 847 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) 848 { 849 if (addr > *mem && addr < *mem + *size) { 850 u64 inc = addr - *mem; 851 add_memory_region(*mem, inc, BOOT_MEM_RAM); 852 *mem += inc; 853 *size -= inc; 854 } 855 856 if (addr == *mem && *size > PAGE_SIZE) { 857 *mem += PAGE_SIZE; 858 *size -= PAGE_SIZE; 859 } 860 } 861 #endif /* CONFIG_CRASH_DUMP */ 862 863 void __init plat_mem_setup(void) 864 { 865 uint64_t mem_alloc_size; 866 uint64_t total; 867 uint64_t crashk_end; 868 #ifndef CONFIG_CRASH_DUMP 869 int64_t memory; 870 uint64_t kernel_start; 871 uint64_t kernel_size; 872 #endif 873 874 total = 0; 875 crashk_end = 0; 876 877 /* 878 * The Mips memory init uses the first memory location for 879 * some memory vectors. When SPARSEMEM is in use, it doesn't 880 * verify that the size is big enough for the final 881 * vectors. Making the smallest chuck 4MB seems to be enough 882 * to consistently work. 883 */ 884 mem_alloc_size = 4 << 20; 885 if (mem_alloc_size > MAX_MEMORY) 886 mem_alloc_size = MAX_MEMORY; 887 888 /* Crashkernel ignores bootmem list. It relies on mem=X@Y option */ 889 #ifdef CONFIG_CRASH_DUMP 890 add_memory_region(RESERVE_LOW_MEM, MAX_MEMORY, BOOT_MEM_RAM); 891 total += MAX_MEMORY; 892 #else 893 #ifdef CONFIG_KEXEC 894 if (crashk_size > 0) { 895 add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM); 896 crashk_end = crashk_base + crashk_size; 897 } 898 #endif 899 /* 900 * When allocating memory, we want incrementing addresses from 901 * bootmem_alloc so the code in add_memory_region can merge 902 * regions next to each other. 903 */ 904 cvmx_bootmem_lock(); 905 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) 906 && (total < MAX_MEMORY)) { 907 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 908 __pa_symbol(&__init_end), -1, 909 0x100000, 910 CVMX_BOOTMEM_FLAG_NO_LOCKING); 911 if (memory >= 0) { 912 u64 size = mem_alloc_size; 913 #ifdef CONFIG_KEXEC 914 uint64_t end; 915 #endif 916 917 /* 918 * exclude a page at the beginning and end of 919 * the 256MB PCIe 'hole' so the kernel will not 920 * try to allocate multi-page buffers that 921 * span the discontinuity. 922 */ 923 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE, 924 &memory, &size); 925 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE + 926 CVMX_PCIE_BAR1_PHYS_SIZE, 927 &memory, &size); 928 #ifdef CONFIG_KEXEC 929 end = memory + mem_alloc_size; 930 931 /* 932 * This function automatically merges address regions 933 * next to each other if they are received in 934 * incrementing order 935 */ 936 if (memory < crashk_base && end > crashk_end) { 937 /* region is fully in */ 938 add_memory_region(memory, 939 crashk_base - memory, 940 BOOT_MEM_RAM); 941 total += crashk_base - memory; 942 add_memory_region(crashk_end, 943 end - crashk_end, 944 BOOT_MEM_RAM); 945 total += end - crashk_end; 946 continue; 947 } 948 949 if (memory >= crashk_base && end <= crashk_end) 950 /* 951 * Entire memory region is within the new 952 * kernel's memory, ignore it. 953 */ 954 continue; 955 956 if (memory > crashk_base && memory < crashk_end && 957 end > crashk_end) { 958 /* 959 * Overlap with the beginning of the region, 960 * reserve the beginning. 961 */ 962 mem_alloc_size -= crashk_end - memory; 963 memory = crashk_end; 964 } else if (memory < crashk_base && end > crashk_base && 965 end < crashk_end) 966 /* 967 * Overlap with the beginning of the region, 968 * chop of end. 969 */ 970 mem_alloc_size -= end - crashk_base; 971 #endif 972 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); 973 total += mem_alloc_size; 974 /* Recovering mem_alloc_size */ 975 mem_alloc_size = 4 << 20; 976 } else { 977 break; 978 } 979 } 980 cvmx_bootmem_unlock(); 981 /* Add the memory region for the kernel. */ 982 kernel_start = (unsigned long) _text; 983 kernel_size = _end - _text; 984 985 /* Adjust for physical offset. */ 986 kernel_start &= ~0xffffffff80000000ULL; 987 add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM); 988 #endif /* CONFIG_CRASH_DUMP */ 989 990 #ifdef CONFIG_CAVIUM_RESERVE32 991 /* 992 * Now that we've allocated the kernel memory it is safe to 993 * free the reserved region. We free it here so that builtin 994 * drivers can use the memory. 995 */ 996 if (octeon_reserve32_memory) 997 cvmx_bootmem_free_named("CAVIUM_RESERVE32"); 998 #endif /* CONFIG_CAVIUM_RESERVE32 */ 999 1000 if (total == 0) 1001 panic("Unable to allocate memory from " 1002 "cvmx_bootmem_phy_alloc"); 1003 } 1004 1005 /* 1006 * Emit one character to the boot UART. Exported for use by the 1007 * watchdog timer. 1008 */ 1009 int prom_putchar(char c) 1010 { 1011 uint64_t lsrval; 1012 1013 /* Spin until there is room */ 1014 do { 1015 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); 1016 } while ((lsrval & 0x20) == 0); 1017 1018 /* Write the byte */ 1019 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); 1020 return 1; 1021 } 1022 EXPORT_SYMBOL(prom_putchar); 1023 1024 void prom_free_prom_memory(void) 1025 { 1026 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) { 1027 /* Check for presence of Core-14449 fix. */ 1028 u32 insn; 1029 u32 *foo; 1030 1031 foo = &insn; 1032 1033 asm volatile("# before" : : : "memory"); 1034 prefetch(foo); 1035 asm volatile( 1036 ".set push\n\t" 1037 ".set noreorder\n\t" 1038 "bal 1f\n\t" 1039 "nop\n" 1040 "1:\tlw %0,-12($31)\n\t" 1041 ".set pop\n\t" 1042 : "=r" (insn) : : "$31", "memory"); 1043 1044 if ((insn >> 26) != 0x33) 1045 panic("No PREF instruction at Core-14449 probe point."); 1046 1047 if (((insn >> 16) & 0x1f) != 28) 1048 panic("Core-14449 WAR not in place (%04x).\n" 1049 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn); 1050 } 1051 } 1052 1053 int octeon_prune_device_tree(void); 1054 1055 extern const char __dtb_octeon_3xxx_begin; 1056 extern const char __dtb_octeon_3xxx_end; 1057 extern const char __dtb_octeon_68xx_begin; 1058 extern const char __dtb_octeon_68xx_end; 1059 void __init device_tree_init(void) 1060 { 1061 int dt_size; 1062 struct boot_param_header *fdt; 1063 bool do_prune; 1064 1065 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { 1066 fdt = phys_to_virt(octeon_bootinfo->fdt_addr); 1067 if (fdt_check_header(fdt)) 1068 panic("Corrupt Device Tree passed to kernel."); 1069 dt_size = be32_to_cpu(fdt->totalsize); 1070 do_prune = false; 1071 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { 1072 fdt = (struct boot_param_header *)&__dtb_octeon_68xx_begin; 1073 dt_size = &__dtb_octeon_68xx_end - &__dtb_octeon_68xx_begin; 1074 do_prune = true; 1075 } else { 1076 fdt = (struct boot_param_header *)&__dtb_octeon_3xxx_begin; 1077 dt_size = &__dtb_octeon_3xxx_end - &__dtb_octeon_3xxx_begin; 1078 do_prune = true; 1079 } 1080 1081 /* Copy the default tree from init memory. */ 1082 initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8); 1083 if (initial_boot_params == NULL) 1084 panic("Could not allocate initial_boot_params"); 1085 memcpy(initial_boot_params, fdt, dt_size); 1086 1087 if (do_prune) { 1088 octeon_prune_device_tree(); 1089 pr_info("Using internal Device Tree.\n"); 1090 } else { 1091 pr_info("Using passed Device Tree.\n"); 1092 } 1093 unflatten_device_tree(); 1094 } 1095 1096 static int __initdata disable_octeon_edac_p; 1097 1098 static int __init disable_octeon_edac(char *str) 1099 { 1100 disable_octeon_edac_p = 1; 1101 return 0; 1102 } 1103 early_param("disable_octeon_edac", disable_octeon_edac); 1104 1105 static char *edac_device_names[] = { 1106 "octeon_l2c_edac", 1107 "octeon_pc_edac", 1108 }; 1109 1110 static int __init edac_devinit(void) 1111 { 1112 struct platform_device *dev; 1113 int i, err = 0; 1114 int num_lmc; 1115 char *name; 1116 1117 if (disable_octeon_edac_p) 1118 return 0; 1119 1120 for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) { 1121 name = edac_device_names[i]; 1122 dev = platform_device_register_simple(name, -1, NULL, 0); 1123 if (IS_ERR(dev)) { 1124 pr_err("Registation of %s failed!\n", name); 1125 err = PTR_ERR(dev); 1126 } 1127 } 1128 1129 num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 : 1130 (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1); 1131 for (i = 0; i < num_lmc; i++) { 1132 dev = platform_device_register_simple("octeon_lmc_edac", 1133 i, NULL, 0); 1134 if (IS_ERR(dev)) { 1135 pr_err("Registation of octeon_lmc_edac %d failed!\n", i); 1136 err = PTR_ERR(dev); 1137 } 1138 } 1139 1140 return err; 1141 } 1142 device_initcall(edac_devinit); 1143 1144 static void __initdata *octeon_dummy_iospace; 1145 1146 static int __init octeon_no_pci_init(void) 1147 { 1148 /* 1149 * Initially assume there is no PCI. The PCI/PCIe platform code will 1150 * later re-initialize these to correct values if they are present. 1151 */ 1152 octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT); 1153 set_io_port_base((unsigned long)octeon_dummy_iospace); 1154 ioport_resource.start = MAX_RESOURCE; 1155 ioport_resource.end = 0; 1156 return 0; 1157 } 1158 core_initcall(octeon_no_pci_init); 1159 1160 static int __init octeon_no_pci_release(void) 1161 { 1162 /* 1163 * Release the allocated memory if a real IO space is there. 1164 */ 1165 if ((unsigned long)octeon_dummy_iospace != mips_io_port_base) 1166 vfree(octeon_dummy_iospace); 1167 return 0; 1168 } 1169 late_initcall(octeon_no_pci_release); 1170