1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2007 Cavium Networks 7 * Copyright (C) 2008 Wind River Systems 8 */ 9 #include <linux/init.h> 10 #include <linux/console.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/serial.h> 15 #include <linux/smp.h> 16 #include <linux/types.h> 17 #include <linux/string.h> /* for memset */ 18 #include <linux/tty.h> 19 #include <linux/time.h> 20 #include <linux/platform_device.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial_8250.h> 23 24 #include <asm/processor.h> 25 #include <asm/reboot.h> 26 #include <asm/smp-ops.h> 27 #include <asm/system.h> 28 #include <asm/irq_cpu.h> 29 #include <asm/mipsregs.h> 30 #include <asm/bootinfo.h> 31 #include <asm/sections.h> 32 #include <asm/time.h> 33 34 #include <asm/octeon/octeon.h> 35 #include <asm/octeon/pci-octeon.h> 36 37 #ifdef CONFIG_CAVIUM_DECODE_RSL 38 extern void cvmx_interrupt_rsl_decode(void); 39 extern int __cvmx_interrupt_ecc_report_single_bit_errors; 40 extern void cvmx_interrupt_rsl_enable(void); 41 #endif 42 43 extern struct plat_smp_ops octeon_smp_ops; 44 45 #ifdef CONFIG_PCI 46 extern void pci_console_init(const char *arg); 47 #endif 48 49 static unsigned long long MAX_MEMORY = 512ull << 20; 50 51 struct octeon_boot_descriptor *octeon_boot_desc_ptr; 52 53 struct cvmx_bootinfo *octeon_bootinfo; 54 EXPORT_SYMBOL(octeon_bootinfo); 55 56 #ifdef CONFIG_CAVIUM_RESERVE32 57 uint64_t octeon_reserve32_memory; 58 EXPORT_SYMBOL(octeon_reserve32_memory); 59 #endif 60 61 static int octeon_uart; 62 63 extern asmlinkage void handle_int(void); 64 extern asmlinkage void plat_irq_dispatch(void); 65 66 /** 67 * Return non zero if we are currently running in the Octeon simulator 68 * 69 * Returns 70 */ 71 int octeon_is_simulation(void) 72 { 73 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; 74 } 75 EXPORT_SYMBOL(octeon_is_simulation); 76 77 /** 78 * Return true if Octeon is in PCI Host mode. This means 79 * Linux can control the PCI bus. 80 * 81 * Returns Non zero if Octeon in host mode. 82 */ 83 int octeon_is_pci_host(void) 84 { 85 #ifdef CONFIG_PCI 86 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; 87 #else 88 return 0; 89 #endif 90 } 91 92 /** 93 * Get the clock rate of Octeon 94 * 95 * Returns Clock rate in HZ 96 */ 97 uint64_t octeon_get_clock_rate(void) 98 { 99 if (octeon_is_simulation()) 100 octeon_bootinfo->eclock_hz = 6000000; 101 return octeon_bootinfo->eclock_hz; 102 } 103 EXPORT_SYMBOL(octeon_get_clock_rate); 104 105 /** 106 * Write to the LCD display connected to the bootbus. This display 107 * exists on most Cavium evaluation boards. If it doesn't exist, then 108 * this function doesn't do anything. 109 * 110 * @s: String to write 111 */ 112 void octeon_write_lcd(const char *s) 113 { 114 if (octeon_bootinfo->led_display_base_addr) { 115 void __iomem *lcd_address = 116 ioremap_nocache(octeon_bootinfo->led_display_base_addr, 117 8); 118 int i; 119 for (i = 0; i < 8; i++, s++) { 120 if (*s) 121 iowrite8(*s, lcd_address + i); 122 else 123 iowrite8(' ', lcd_address + i); 124 } 125 iounmap(lcd_address); 126 } 127 } 128 129 /** 130 * Return the console uart passed by the bootloader 131 * 132 * Returns uart (0 or 1) 133 */ 134 int octeon_get_boot_uart(void) 135 { 136 int uart; 137 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 138 uart = 1; 139 #else 140 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? 141 1 : 0; 142 #endif 143 return uart; 144 } 145 146 /** 147 * Get the coremask Linux was booted on. 148 * 149 * Returns Core mask 150 */ 151 int octeon_get_boot_coremask(void) 152 { 153 return octeon_boot_desc_ptr->core_mask; 154 } 155 156 /** 157 * Check the hardware BIST results for a CPU 158 */ 159 void octeon_check_cpu_bist(void) 160 { 161 const int coreid = cvmx_get_core_num(); 162 unsigned long long mask; 163 unsigned long long bist_val; 164 165 /* Check BIST results for COP0 registers */ 166 mask = 0x1f00000000ull; 167 bist_val = read_octeon_c0_icacheerr(); 168 if (bist_val & mask) 169 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", 170 coreid, bist_val); 171 172 bist_val = read_octeon_c0_dcacheerr(); 173 if (bist_val & 1) 174 pr_err("Core%d L1 Dcache parity error: " 175 "CacheErr(dcache) = 0x%llx\n", 176 coreid, bist_val); 177 178 mask = 0xfc00000000000000ull; 179 bist_val = read_c0_cvmmemctl(); 180 if (bist_val & mask) 181 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", 182 coreid, bist_val); 183 184 write_octeon_c0_dcacheerr(0); 185 } 186 187 /** 188 * Reboot Octeon 189 * 190 * @command: Command to pass to the bootloader. Currently ignored. 191 */ 192 static void octeon_restart(char *command) 193 { 194 /* Disable all watchdogs before soft reset. They don't get cleared */ 195 #ifdef CONFIG_SMP 196 int cpu; 197 for_each_online_cpu(cpu) 198 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); 199 #else 200 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 201 #endif 202 203 mb(); 204 while (1) 205 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 206 } 207 208 209 /** 210 * Permanently stop a core. 211 * 212 * @arg: Ignored. 213 */ 214 static void octeon_kill_core(void *arg) 215 { 216 mb(); 217 if (octeon_is_simulation()) { 218 /* The simulator needs the watchdog to stop for dead cores */ 219 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); 220 /* A break instruction causes the simulator stop a core */ 221 asm volatile ("sync\nbreak"); 222 } 223 } 224 225 226 /** 227 * Halt the system 228 */ 229 static void octeon_halt(void) 230 { 231 smp_call_function(octeon_kill_core, NULL, 0); 232 233 switch (octeon_bootinfo->board_type) { 234 case CVMX_BOARD_TYPE_NAO38: 235 /* Driving a 1 to GPIO 12 shuts off this board */ 236 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); 237 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); 238 break; 239 default: 240 octeon_write_lcd("PowerOff"); 241 break; 242 } 243 244 octeon_kill_core(NULL); 245 } 246 247 /** 248 * Handle all the error condition interrupts that might occur. 249 * 250 */ 251 #ifdef CONFIG_CAVIUM_DECODE_RSL 252 static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id) 253 { 254 cvmx_interrupt_rsl_decode(); 255 return IRQ_HANDLED; 256 } 257 #endif 258 259 /** 260 * Return a string representing the system type 261 * 262 * Returns 263 */ 264 const char *octeon_board_type_string(void) 265 { 266 static char name[80]; 267 sprintf(name, "%s (%s)", 268 cvmx_board_type_to_string(octeon_bootinfo->board_type), 269 octeon_model_get_string(read_c0_prid())); 270 return name; 271 } 272 273 const char *get_system_type(void) 274 __attribute__ ((alias("octeon_board_type_string"))); 275 276 void octeon_user_io_init(void) 277 { 278 union octeon_cvmemctl cvmmemctl; 279 union cvmx_iob_fau_timeout fau_timeout; 280 union cvmx_pow_nw_tim nm_tim; 281 uint64_t cvmctl; 282 283 /* Get the current settings for CP0_CVMMEMCTL_REG */ 284 cvmmemctl.u64 = read_c0_cvmmemctl(); 285 /* R/W If set, marked write-buffer entries time out the same 286 * as as other entries; if clear, marked write-buffer entries 287 * use the maximum timeout. */ 288 cvmmemctl.s.dismarkwblongto = 1; 289 /* R/W If set, a merged store does not clear the write-buffer 290 * entry timeout state. */ 291 cvmmemctl.s.dismrgclrwbto = 0; 292 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM 293 * word location for an IOBDMA. The other 8 bits come from the 294 * SCRADDR field of the IOBDMA. */ 295 cvmmemctl.s.iobdmascrmsb = 0; 296 /* R/W If set, SYNCWS and SYNCS only order marked stores; if 297 * clear, SYNCWS and SYNCS only order unmarked 298 * stores. SYNCWSMARKED has no effect when DISSYNCWS is 299 * set. */ 300 cvmmemctl.s.syncwsmarked = 0; 301 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ 302 cvmmemctl.s.dissyncws = 0; 303 /* R/W If set, no stall happens on write buffer full. */ 304 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) 305 cvmmemctl.s.diswbfst = 1; 306 else 307 cvmmemctl.s.diswbfst = 0; 308 /* R/W If set (and SX set), supervisor-level loads/stores can 309 * use XKPHYS addresses with <48>==0 */ 310 cvmmemctl.s.xkmemenas = 0; 311 312 /* R/W If set (and UX set), user-level loads/stores can use 313 * XKPHYS addresses with VA<48>==0 */ 314 cvmmemctl.s.xkmemenau = 0; 315 316 /* R/W If set (and SX set), supervisor-level loads/stores can 317 * use XKPHYS addresses with VA<48>==1 */ 318 cvmmemctl.s.xkioenas = 0; 319 320 /* R/W If set (and UX set), user-level loads/stores can use 321 * XKPHYS addresses with VA<48>==1 */ 322 cvmmemctl.s.xkioenau = 0; 323 324 /* R/W If set, all stores act as SYNCW (NOMERGE must be set 325 * when this is set) RW, reset to 0. */ 326 cvmmemctl.s.allsyncw = 0; 327 328 /* R/W If set, no stores merge, and all stores reach the 329 * coherent bus in order. */ 330 cvmmemctl.s.nomerge = 0; 331 /* R/W Selects the bit in the counter used for DID time-outs 0 332 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is 333 * between 1x and 2x this interval. For example, with 334 * DIDTTO=3, expiration interval is between 16K and 32K. */ 335 cvmmemctl.s.didtto = 0; 336 /* R/W If set, the (mem) CSR clock never turns off. */ 337 cvmmemctl.s.csrckalwys = 0; 338 /* R/W If set, mclk never turns off. */ 339 cvmmemctl.s.mclkalwys = 0; 340 /* R/W Selects the bit in the counter used for write buffer 341 * flush time-outs (WBFLT+11) is the bit position in an 342 * internal counter used to determine expiration. The write 343 * buffer expires between 1x and 2x this interval. For 344 * example, with WBFLT = 0, a write buffer expires between 2K 345 * and 4K cycles after the write buffer entry is allocated. */ 346 cvmmemctl.s.wbfltime = 0; 347 /* R/W If set, do not put Istream in the L2 cache. */ 348 cvmmemctl.s.istrnol2 = 0; 349 /* R/W The write buffer threshold. */ 350 cvmmemctl.s.wbthresh = 10; 351 /* R/W If set, CVMSEG is available for loads/stores in 352 * kernel/debug mode. */ 353 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 354 cvmmemctl.s.cvmsegenak = 1; 355 #else 356 cvmmemctl.s.cvmsegenak = 0; 357 #endif 358 /* R/W If set, CVMSEG is available for loads/stores in 359 * supervisor mode. */ 360 cvmmemctl.s.cvmsegenas = 0; 361 /* R/W If set, CVMSEG is available for loads/stores in user 362 * mode. */ 363 cvmmemctl.s.cvmsegenau = 0; 364 /* R/W Size of local memory in cache blocks, 54 (6912 bytes) 365 * is max legal value. */ 366 cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE; 367 368 369 if (smp_processor_id() == 0) 370 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", 371 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, 372 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); 373 374 write_c0_cvmmemctl(cvmmemctl.u64); 375 376 /* Move the performance counter interrupts to IRQ 6 */ 377 cvmctl = read_c0_cvmctl(); 378 cvmctl &= ~(7 << 7); 379 cvmctl |= 6 << 7; 380 write_c0_cvmctl(cvmctl); 381 382 /* Set a default for the hardware timeouts */ 383 fau_timeout.u64 = 0; 384 fau_timeout.s.tout_val = 0xfff; 385 /* Disable tagwait FAU timeout */ 386 fau_timeout.s.tout_enb = 0; 387 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); 388 389 nm_tim.u64 = 0; 390 /* 4096 cycles */ 391 nm_tim.s.nw_tim = 3; 392 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); 393 394 write_octeon_c0_icacheerr(0); 395 write_c0_derraddr1(0); 396 } 397 398 /** 399 * Early entry point for arch setup 400 */ 401 void __init prom_init(void) 402 { 403 struct cvmx_sysinfo *sysinfo; 404 const int coreid = cvmx_get_core_num(); 405 int i; 406 int argc; 407 #ifdef CONFIG_CAVIUM_RESERVE32 408 int64_t addr = -1; 409 #endif 410 /* 411 * The bootloader passes a pointer to the boot descriptor in 412 * $a3, this is available as fw_arg3. 413 */ 414 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; 415 octeon_bootinfo = 416 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); 417 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); 418 419 /* 420 * Only enable the LED controller if we're running on a CN38XX, CN58XX, 421 * or CN56XX. The CN30XX and CN31XX don't have an LED controller. 422 */ 423 if (!octeon_is_simulation() && 424 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { 425 cvmx_write_csr(CVMX_LED_EN, 0); 426 cvmx_write_csr(CVMX_LED_PRT, 0); 427 cvmx_write_csr(CVMX_LED_DBG, 0); 428 cvmx_write_csr(CVMX_LED_PRT_FMT, 0); 429 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); 430 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); 431 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); 432 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); 433 cvmx_write_csr(CVMX_LED_EN, 1); 434 } 435 #ifdef CONFIG_CAVIUM_RESERVE32 436 /* 437 * We need to temporarily allocate all memory in the reserve32 438 * region. This makes sure the kernel doesn't allocate this 439 * memory when it is getting memory from the 440 * bootloader. Later, after the memory allocations are 441 * complete, the reserve32 will be freed. 442 * 443 * Allocate memory for RESERVED32 aligned on 2MB boundary. This 444 * is in case we later use hugetlb entries with it. 445 */ 446 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, 447 0, 0, 2 << 20, 448 "CAVIUM_RESERVE32", 0); 449 if (addr < 0) 450 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); 451 else 452 octeon_reserve32_memory = addr; 453 #endif 454 455 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 456 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { 457 pr_info("Skipping L2 locking due to reduced L2 cache size\n"); 458 } else { 459 uint32_t ebase = read_c0_ebase() & 0x3ffff000; 460 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB 461 /* TLB refill */ 462 cvmx_l2c_lock_mem_region(ebase, 0x100); 463 #endif 464 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION 465 /* General exception */ 466 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); 467 #endif 468 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 469 /* Interrupt handler */ 470 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); 471 #endif 472 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT 473 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); 474 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); 475 #endif 476 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY 477 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); 478 #endif 479 } 480 #endif 481 482 sysinfo = cvmx_sysinfo_get(); 483 memset(sysinfo, 0, sizeof(*sysinfo)); 484 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; 485 sysinfo->phy_mem_desc_ptr = 486 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr); 487 sysinfo->core_mask = octeon_bootinfo->core_mask; 488 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; 489 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; 490 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; 491 sysinfo->board_type = octeon_bootinfo->board_type; 492 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; 493 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; 494 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, 495 sizeof(sysinfo->mac_addr_base)); 496 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; 497 memcpy(sysinfo->board_serial_number, 498 octeon_bootinfo->board_serial_number, 499 sizeof(sysinfo->board_serial_number)); 500 sysinfo->compact_flash_common_base_addr = 501 octeon_bootinfo->compact_flash_common_base_addr; 502 sysinfo->compact_flash_attribute_base_addr = 503 octeon_bootinfo->compact_flash_attribute_base_addr; 504 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; 505 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; 506 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; 507 508 509 octeon_check_cpu_bist(); 510 511 octeon_uart = octeon_get_boot_uart(); 512 513 /* 514 * Disable All CIU Interrupts. The ones we need will be 515 * enabled later. Read the SUM register so we know the write 516 * completed. 517 */ 518 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); 519 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); 520 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); 521 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); 522 cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); 523 524 #ifdef CONFIG_SMP 525 octeon_write_lcd("LinuxSMP"); 526 #else 527 octeon_write_lcd("Linux"); 528 #endif 529 530 #ifdef CONFIG_CAVIUM_GDB 531 /* 532 * When debugging the linux kernel, force the cores to enter 533 * the debug exception handler to break in. 534 */ 535 if (octeon_get_boot_debug_flag()) { 536 cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num()); 537 cvmx_read_csr(CVMX_CIU_DINT); 538 } 539 #endif 540 541 /* 542 * BIST should always be enabled when doing a soft reset. L2 543 * Cache locking for instance is not cleared unless BIST is 544 * enabled. Unfortunately due to a chip errata G-200 for 545 * Cn38XX and CN31XX, BIST msut be disabled on these parts. 546 */ 547 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || 548 OCTEON_IS_MODEL(OCTEON_CN31XX)) 549 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); 550 else 551 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); 552 553 /* Default to 64MB in the simulator to speed things up */ 554 if (octeon_is_simulation()) 555 MAX_MEMORY = 64ull << 20; 556 557 arcs_cmdline[0] = 0; 558 argc = octeon_boot_desc_ptr->argc; 559 for (i = 0; i < argc; i++) { 560 const char *arg = 561 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); 562 if ((strncmp(arg, "MEM=", 4) == 0) || 563 (strncmp(arg, "mem=", 4) == 0)) { 564 sscanf(arg + 4, "%llu", &MAX_MEMORY); 565 MAX_MEMORY <<= 20; 566 if (MAX_MEMORY == 0) 567 MAX_MEMORY = 32ull << 30; 568 } else if (strcmp(arg, "ecc_verbose") == 0) { 569 #ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC 570 __cvmx_interrupt_ecc_report_single_bit_errors = 1; 571 pr_notice("Reporting of single bit ECC errors is " 572 "turned on\n"); 573 #endif 574 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < 575 sizeof(arcs_cmdline) - 1) { 576 strcat(arcs_cmdline, " "); 577 strcat(arcs_cmdline, arg); 578 } 579 } 580 581 if (strstr(arcs_cmdline, "console=") == NULL) { 582 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 583 strcat(arcs_cmdline, " console=ttyS0,115200"); 584 #else 585 if (octeon_uart == 1) 586 strcat(arcs_cmdline, " console=ttyS1,115200"); 587 else 588 strcat(arcs_cmdline, " console=ttyS0,115200"); 589 #endif 590 } 591 592 if (octeon_is_simulation()) { 593 /* 594 * The simulator uses a mtdram device pre filled with 595 * the filesystem. Also specify the calibration delay 596 * to avoid calculating it every time. 597 */ 598 strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824"); 599 } 600 601 mips_hpt_frequency = octeon_get_clock_rate(); 602 603 octeon_init_cvmcount(); 604 octeon_setup_delays(); 605 606 _machine_restart = octeon_restart; 607 _machine_halt = octeon_halt; 608 609 octeon_user_io_init(); 610 register_smp_ops(&octeon_smp_ops); 611 } 612 613 /* Exclude a single page from the regions obtained in plat_mem_setup. */ 614 static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) 615 { 616 if (addr > *mem && addr < *mem + *size) { 617 u64 inc = addr - *mem; 618 add_memory_region(*mem, inc, BOOT_MEM_RAM); 619 *mem += inc; 620 *size -= inc; 621 } 622 623 if (addr == *mem && *size > PAGE_SIZE) { 624 *mem += PAGE_SIZE; 625 *size -= PAGE_SIZE; 626 } 627 } 628 629 void __init plat_mem_setup(void) 630 { 631 uint64_t mem_alloc_size; 632 uint64_t total; 633 int64_t memory; 634 635 total = 0; 636 637 /* First add the init memory we will be returning. */ 638 memory = __pa_symbol(&__init_begin) & PAGE_MASK; 639 mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory; 640 if (mem_alloc_size > 0) { 641 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); 642 total += mem_alloc_size; 643 } 644 645 /* 646 * The Mips memory init uses the first memory location for 647 * some memory vectors. When SPARSEMEM is in use, it doesn't 648 * verify that the size is big enough for the final 649 * vectors. Making the smallest chuck 4MB seems to be enough 650 * to consistantly work. 651 */ 652 mem_alloc_size = 4 << 20; 653 if (mem_alloc_size > MAX_MEMORY) 654 mem_alloc_size = MAX_MEMORY; 655 656 /* 657 * When allocating memory, we want incrementing addresses from 658 * bootmem_alloc so the code in add_memory_region can merge 659 * regions next to each other. 660 */ 661 cvmx_bootmem_lock(); 662 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) 663 && (total < MAX_MEMORY)) { 664 #if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR) 665 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 666 __pa_symbol(&__init_end), -1, 667 0x100000, 668 CVMX_BOOTMEM_FLAG_NO_LOCKING); 669 #elif defined(CONFIG_HIGHMEM) 670 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31, 671 0x100000, 672 CVMX_BOOTMEM_FLAG_NO_LOCKING); 673 #else 674 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20, 675 0x100000, 676 CVMX_BOOTMEM_FLAG_NO_LOCKING); 677 #endif 678 if (memory >= 0) { 679 u64 size = mem_alloc_size; 680 681 /* 682 * exclude a page at the beginning and end of 683 * the 256MB PCIe 'hole' so the kernel will not 684 * try to allocate multi-page buffers that 685 * span the discontinuity. 686 */ 687 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE, 688 &memory, &size); 689 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE + 690 CVMX_PCIE_BAR1_PHYS_SIZE, 691 &memory, &size); 692 693 /* 694 * This function automatically merges address 695 * regions next to each other if they are 696 * received in incrementing order. 697 */ 698 if (size) 699 add_memory_region(memory, size, BOOT_MEM_RAM); 700 total += mem_alloc_size; 701 } else { 702 break; 703 } 704 } 705 cvmx_bootmem_unlock(); 706 707 #ifdef CONFIG_CAVIUM_RESERVE32 708 /* 709 * Now that we've allocated the kernel memory it is safe to 710 * free the reserved region. We free it here so that builtin 711 * drivers can use the memory. 712 */ 713 if (octeon_reserve32_memory) 714 cvmx_bootmem_free_named("CAVIUM_RESERVE32"); 715 #endif /* CONFIG_CAVIUM_RESERVE32 */ 716 717 if (total == 0) 718 panic("Unable to allocate memory from " 719 "cvmx_bootmem_phy_alloc\n"); 720 } 721 722 /* 723 * Emit one character to the boot UART. Exported for use by the 724 * watchdog timer. 725 */ 726 int prom_putchar(char c) 727 { 728 uint64_t lsrval; 729 730 /* Spin until there is room */ 731 do { 732 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); 733 } while ((lsrval & 0x20) == 0); 734 735 /* Write the byte */ 736 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); 737 return 1; 738 } 739 EXPORT_SYMBOL(prom_putchar); 740 741 void prom_free_prom_memory(void) 742 { 743 #ifdef CONFIG_CAVIUM_DECODE_RSL 744 cvmx_interrupt_rsl_enable(); 745 746 /* Add an interrupt handler for general failures. */ 747 if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, 748 "RML/RSL", octeon_rlm_interrupt)) { 749 panic("Unable to request_irq(OCTEON_IRQ_RML)\n"); 750 } 751 #endif 752 } 753